From 7a6235183cb00716df2d57957f577fa0d9509cfb Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 29 Oct 2014 13:03:19 +0000
Subject: [PATCH] Added TSE IP for GX.
---
.../ip_arria10/tse_sgmii_gx/README.txt | 6 +
.../ip_arria10/tse_sgmii_gx/compile_ip.tcl | 310 ++++++++++++++++++
.../ip_arria10/tse_sgmii_gx/generate_ip.sh | 54 +++
.../ip_arria10/tse_sgmii_gx/hdllib.cfg | 22 ++
.../tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys | 302 +++++++++++++++++
5 files changed, 694 insertions(+)
create mode 100755 libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
create mode 100644 libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
new file mode 100755
index 0000000000..118ad12219
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -0,0 +1,6 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+
+
+The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
+
+The ip_arria10_tse_sgmii_gx was not verified.
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
new file mode 100644
index 0000000000..24160d1cea
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -0,0 +1,310 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - compile_ip.tcl: vmap the IP specific libraries to ./work and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - compile_ip.tcl: replace QSYS_SIMDIR by IP_DIR
+# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
+# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_tse_sgmii_gx_altera_reset_controller_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_eth_tse_nf_phyip_terminator_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_eth_tse_avalon_arbiter_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140 ./work/
+vmap ip_arria10_tse_sgmii_gx_altera_eth_tse_140 ./work/
+
+vlog "$IP_DIR/../altera_reset_controller_140/sim/altera_reset_controller.v" -work ip_arria10_tse_sgmii_gx_altera_reset_controller_140
+vlog "$IP_DIR/../altera_reset_controller_140/sim/altera_reset_synchronizer.v" -work ip_arria10_tse_sgmii_gx_altera_reset_controller_140
+vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_140/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_nf_phyip_terminator_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/altera_xcvr_functions.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pcs.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pcs_ch.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pma.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pma_ch.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_xcvr_native.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pcs.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pcs_ch.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pma.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pma_ch.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_xcvr_native.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/altera_xcvr_native_a10.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/altera_xcvr_native_a10.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_tse_sgmii_gx_altera_xcvr_native_a10_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_align_sync.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_dec10b8b.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_dec_func.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_enc8b10b.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_autoneg.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_carrier_sense.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_clk_gen.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_sgmii_clk_div.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_sgmii_clk_enable.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_rx_encapsulation.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_tx_encapsulation.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_pcs_control.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_pcs_host_control.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_mdio_reg.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_rx_sync.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_colision_detect.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_rx_converter.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_rx_fifo_rd.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_rx_converter.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_sgmii.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_tx_converter.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_tx_converter.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_1000_base_x.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_pcs.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_rx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_top_tx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_reset_sequencer.sv" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_reset_ctrl_lego.sv" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_xcvr_resync.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_false_path_marker.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_reset_synchronizer.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_clock_crosser.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_13.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_24.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_34.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_gray_cnt.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_sdpm_altsyncram.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_bin_cnt.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ph_calculator.sv" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_sdpm_gen.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_dc_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x14.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x14.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x2.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x2.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x23.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x23.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x36.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x36.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x40.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x40.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_dec_x30.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x30.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_140/sim/mentor/altera_tse_ecc_status_crosser.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_pcs_pma_nf_phyip_140
+vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_140/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_avalon_arbiter_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_eth_tse_mac.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_clk_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_crc328checker.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_crc328generator.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_crc32ctl8.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_crc32galois8.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_gmii_io.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_lb_read_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_lb_wrt_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_hashing.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_host_control.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_host_control_small.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mac_control.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_register_map.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_register_map_small.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_counter_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_shared_mac_control.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_shared_register_map.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_counter_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_lfsr_10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_loopback_ff.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_altshifttaps.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_fifoless_mac_rx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mac_rx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_fifoless_mac_tx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mac_tx.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_magic_detection.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mdio.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mdio_clk_gen.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mdio_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_mdio.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mii_rx_if.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_mii_tx_if.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_pipeline_base.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog -sv "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_pipeline_stage.sv" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_dpram_16x32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_dpram_8x32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_quad_16x32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_quad_8x32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_retransmit_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rgmii_in1.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rgmii_in4.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_nf_rgmii_module.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rgmii_module.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rgmii_out1.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rgmii_out4.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_ff.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_min_ff.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_ff_cntrl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_ff_length.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_rx_stat_extract.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_timing_adapter32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_timing_adapter8.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_1geth.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_fifoless_1geth.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_w_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_wo_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_top_gen_host.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_min_ff.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff_cntrl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff_length.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_tx_stat_extract.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_false_path_marker.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_reset_synchronizer.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_clock_crosser.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_13.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_24.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_34.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_gray_cnt.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_sdpm_altsyncram.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_bin_cnt.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog -sv "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ph_calculator.sv" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_sdpm_gen.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_dc_fifo.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x10.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x14.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x14.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x2.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x2.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x23.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x23.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x36.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x36.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x40.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x40.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_dec_x30.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x30.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_mac_140/sim/mentor/altera_tse_ecc_status_crosser.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_mac_140
+vlog "$IP_DIR/../altera_eth_tse_140/sim/ip_arria10_tse_sgmii_gx_altera_eth_tse_140_l2suray.v" -work ip_arria10_tse_sgmii_gx_altera_eth_tse_140
+vcom "$IP_DIR/ip_arria10_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
new file mode 100755
index 0000000000..c993bc3aa3
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_tse_sgmii_gx.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP
+#qsys-generate ip_arria10_tse_sgmii_gx.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
new file mode 100644
index 0000000000..2fe8756e05
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -0,0 +1,22 @@
+hdl_lib_name = ip_arria10_tse_sgmii_gx
+hdl_library_clause_name = ip_arria10_tse_sgmii_gx_lib
+hdl_lib_uses = common
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+ #tb_ip_arria10_tse_sgmii_gx.vhd
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
+
+quartus_qip_files =
+ generated/ip_arria10_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
new file mode 100644
index 0000000000..00db94bdaf
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/ip_arria10_tse_sgmii_gx.qsys
@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="control_port_clock_connection"
+ internal="eth_tse_0.control_port_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="clk" internal="clk" />
+ </interface>
+ <interface
+ name="reset_connection"
+ internal="eth_tse_0.reset_connection"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="control_port"
+ internal="eth_tse_0.control_port"
+ type="avalon"
+ dir="end">
+ <port name="reg_data_out" internal="reg_data_out" />
+ <port name="reg_rd" internal="reg_rd" />
+ <port name="reg_data_in" internal="reg_data_in" />
+ <port name="reg_wr" internal="reg_wr" />
+ <port name="reg_busy" internal="reg_busy" />
+ <port name="reg_addr" internal="reg_addr" />
+ </interface>
+ <interface
+ name="pcs_mac_tx_clock_connection"
+ internal="eth_tse_0.pcs_mac_tx_clock_connection" />
+ <interface
+ name="pcs_mac_rx_clock_connection"
+ internal="eth_tse_0.pcs_mac_rx_clock_connection" />
+ <interface
+ name="mac_status_connection"
+ internal="eth_tse_0.mac_status_connection" />
+ <interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
+ <interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
+ <interface
+ name="receive_clock_connection"
+ internal="eth_tse_0.receive_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_rx_clk" internal="ff_rx_clk" />
+ </interface>
+ <interface
+ name="transmit_clock_connection"
+ internal="eth_tse_0.transmit_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_tx_clk" internal="ff_tx_clk" />
+ </interface>
+ <interface
+ name="receive"
+ internal="eth_tse_0.receive"
+ type="avalon_streaming"
+ dir="start">
+ <port name="ff_rx_data" internal="ff_rx_data" />
+ <port name="ff_rx_eop" internal="ff_rx_eop" />
+ <port name="rx_err" internal="rx_err" />
+ <port name="ff_rx_mod" internal="ff_rx_mod" />
+ <port name="ff_rx_rdy" internal="ff_rx_rdy" />
+ <port name="ff_rx_sop" internal="ff_rx_sop" />
+ <port name="ff_rx_dval" internal="ff_rx_dval" />
+ </interface>
+ <interface
+ name="transmit"
+ internal="eth_tse_0.transmit"
+ type="avalon_streaming"
+ dir="end">
+ <port name="ff_tx_data" internal="ff_tx_data" />
+ <port name="ff_tx_eop" internal="ff_tx_eop" />
+ <port name="ff_tx_err" internal="ff_tx_err" />
+ <port name="ff_tx_mod" internal="ff_tx_mod" />
+ <port name="ff_tx_rdy" internal="ff_tx_rdy" />
+ <port name="ff_tx_sop" internal="ff_tx_sop" />
+ <port name="ff_tx_wren" internal="ff_tx_wren" />
+ </interface>
+ <interface
+ name="mac_misc_connection"
+ internal="eth_tse_0.mac_misc_connection"
+ type="conduit"
+ dir="end">
+ <port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
+ <port name="ff_tx_septy" internal="ff_tx_septy" />
+ <port name="tx_ff_uflow" internal="tx_ff_uflow" />
+ <port name="ff_tx_a_full" internal="ff_tx_a_full" />
+ <port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
+ <port name="rx_err_stat" internal="rx_err_stat" />
+ <port name="rx_frm_type" internal="rx_frm_type" />
+ <port name="ff_rx_dsav" internal="ff_rx_dsav" />
+ <port name="ff_rx_a_full" internal="ff_rx_a_full" />
+ <port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
+ </interface>
+ <interface
+ name="status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end">
+ <port name="led_crs" internal="led_crs" />
+ <port name="led_link" internal="led_link" />
+ <port name="led_col" internal="led_col" />
+ <port name="led_an" internal="led_an" />
+ <port name="led_char_err" internal="led_char_err" />
+ <port name="led_disp_err" internal="led_disp_err" />
+ </interface>
+ <interface
+ name="serdes_control_connection"
+ internal="eth_tse_0.serdes_control_connection"
+ type="conduit"
+ dir="end">
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
+ </interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
+ <interface
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end">
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="eth_tse_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="end">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk"
+ internal="eth_tse_0.rx_cdr_refclk"
+ type="clock"
+ dir="end">
+ <port name="rx_cdr_refclk" internal="rx_cdr_refclk" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="eth_tse_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="eth_tse_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="eth_tse_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="eth_tse_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="eth_tse_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="eth_tse_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_set_locktodata"
+ internal="eth_tse_0.rx_set_locktodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktodata" internal="rx_set_locktodata" />
+ </interface>
+ <interface
+ name="rx_set_locktoref"
+ internal="eth_tse_0.rx_set_locktoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktoref" internal="rx_set_locktoref" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="eth_tse_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="eth_tse_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <module
+ kind="altera_eth_tse"
+ version="14.0"
+ enabled="1"
+ name="eth_tse_0"
+ autoexport="1">
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="use_misc_ports" value="true" />
+ <parameter name="transceiver_type" value="GXB" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_gmii_loopback" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="stat_cnt_ena" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="false" />
+ <parameter name="useMDIO" value="false" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="eg_addr" value="8" />
+ <parameter name="ing_addr" value="8" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="enable_sgmii" value="false" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="AUTO_DEVICE" value="Unknown" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
--
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