diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 11271b1537b61de03e096f7ee3d0cfbf0230dc58..61b1c01df6f6f939664998cdeec1002c4364b1dc 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -51,13 +51,16 @@ ARCHITECTURE tb OF tb_ddrctrl IS
CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
+ CONSTANT c_adr_w : NATURAL := 4;
+ CONSTANT c_max_adr : NATURAL := 2**c_adr_w-1;
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*g_sim_lengt-1 DOWNTO 0);
BEGIN
- FOR I IN 0 TO g_sim_lengt-1 LOOP
- temp(c_in_data_w*(I+1)-1 DOWNTO c_in_data_w*I) := TO_UVEC(I, c_in_data_w);
+ --temp(c_out_data_w-1 DOWNTO 0) := (OTHERS => '0');
+ FOR I IN 0 TO g_sim_lengt*g_nof_streams-1 LOOP
+ temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
@@ -65,11 +68,11 @@ ARCHITECTURE tb OF tb_ddrctrl IS
- SIGNAL ctr_of : NATURAL := 0; -- signal which contains the amount of overflow for checking
SIGNAL in_data_cnt : NATURAL := 0;
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell when the testing has started
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+ SIGNAL lag_due_reset : NATURAL := 0;
SIGNAL clk : STD_LOGIC := '1'; -- clock signal
@@ -77,15 +80,19 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input signal for ddrctrl_pack.vhd
SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
- SIGNAL out_mosi : t_mem_ctlr_mosi; -- output signal from ddrctrl_pack.vhd
+ SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- output signal from ddrctrl_pack.vhd
BEGIN
clk <= NOT clk OR tb_end AFTER c_clk_period/2; -- generating clock signal
- p_mm : PROCESS
+ p_test : PROCESS
BEGIN
+ fill_in_sosi_arr_1 : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
+ END LOOP;
+
-- Start the testbench.
tb_end <= '0';
WAIT UNTIL rising_edge(clk); -- align to rising edge
@@ -93,28 +100,40 @@ BEGIN
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
test_running <= '1'; -- start of test
-
-- The input data vectors get filled with the corresponding numbers.
- make_data : FOR J IN 0 TO g_sim_lengt-1 LOOP
+ WAIT FOR c_clk_period*1;
+ make_data : FOR J IN 1 TO g_sim_lengt-1 LOOP
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(c_in_data_w - 1 DOWNTO 0) <= c_total_vector(c_in_data_w*(I+1)+(J+1)-1 DOWNTO c_in_data_w*I+(J+1));
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
END LOOP;
- WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1;
+ WAIT FOR c_clk_period*1;
END LOOP;
test_running <= '0';
-
-- Stop the testbench.
WAIT FOR c_clk_period*4;
tb_end <= '1';
-
WAIT;
END PROCESS;
+
+ p_test_reset : PROCESS
+ BEGIN
+
+ WAIT FOR c_clk_period*32;
+ rst <= '1';
+ lag_due_reset <= TO_UINT(out_mosi.address)+1;
+ WAIT FOR c_clk_period*1;
+ rst <= '0';
+ WAIT;
+ END PROCESS;
+
+
+
-- Verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected.
- p_verify : PROCESS
+ p_verify_of_data : PROCESS
VARIABLE ctr_of : NATURAL := 0;
VARIABLE out_data_cnt : NATURAL := 0;
@@ -122,19 +141,36 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(out_mosi.wr);
- --WAIT FOR c_clk_period*1;
+
+
IF test_running = '1' THEN
- -- ASSERT FALSE REPORT "ik werk" SEVERITY NOTE;
- IF out_data_cnt mod 2 = 0 THEN
- ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*(out_data_cnt);
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
+ IF out_data_cnt > 0 THEN
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
+ END IF;
+ ASSERT out_mosi.wrdata(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt)-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
- ASSERT out_mosi.wrdata(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt+1)-1 DOWNTO c_out_data_w*out_data_cnt) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
out_data_cnt := out_data_cnt + 1;
END IF;
END PROCESS;
+ p_verify_address : PROCESS
+ BEGIN
+ FOR I IN 0 TO c_max_adr LOOP
+ WAIT UNTIL rising_edge(out_mosi.wr);
+ IF I >= lag_due_reset THEN
+ ASSERT I-lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-lag_due_reset) SEVERITY ERROR;
+ ELSE
+ ASSERT I+c_max_adr-lag_due_reset+1 = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image(I+c_max_adr-lag_due_reset+1) SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+
+
+
u_ddrctrl_pack : ENTITY work.ddrctrl
GENERIC MAP (
g_tech_ddr => g_tech_ddr,