diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index 6429d493b301020e4d6c9c20c04c35cf63f161fc..0125a8bca8339da07b60c5077dd265248a75b65a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -127,15 +127,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -150,17 +145,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -194,14 +184,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index b1bcaf67b4002929f2c81963abdd06d4770a9ceb..b5bc94fa3071de4b1ab1e23e065299114b763f0e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -163,15 +163,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
SIGNAL SA_CLK : STD_LOGIC := '1';
SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
@@ -189,7 +184,7 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
pps_rst <= '0' AFTER c_ext_clk_period*2;
@@ -197,11 +192,6 @@ BEGIN
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -236,14 +226,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index 2c9a58252bab37ab74ec2b492587acf7bf1aca3a..6380bbc3993f6e023810a4833756b43153cf417f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -104,15 +104,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_bst_offload IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -127,17 +122,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -171,14 +161,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index e72382cdf91a88b121af42c6ad312eea319c1d16..4ed4f92c2984100c12e91036f622b74efbcd9386 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -140,15 +140,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_fsub IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -163,16 +158,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -207,14 +198,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
index e8cf7a543155cf4a473c4a8bdea20d06a28fb1a1..f44cc338e1fccca4dc3d3d8be925c1e9c784261e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
@@ -104,15 +104,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_fsub_sst_offload IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -127,17 +122,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -171,14 +161,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index 3abc49be1cbb5d8a386971d9e506ffc644b1319b..4f02a42b4e949f5477b9c854334df333b117df89 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -137,15 +137,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -160,16 +155,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -204,14 +195,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 1a4861582bdb31a71dfec1191a5b2602de49dbd9..71ddb5d5d2ea7014a3252fee1395afa060bc522a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -105,15 +105,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
- SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
-- back transceivers
SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
@@ -128,17 +123,12 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
@@ -172,14 +162,6 @@ BEGIN
ID => c_id,
TESTIO => open,
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
index c230b8946ad4a76b96b85f60d04b5c59d02479d7..e8a8b744ffd4c43a5bc1628abfdb805c0a2ab153 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
@@ -89,8 +89,8 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
# phy_10gbase_r
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_hsgyevq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_hsgyevq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# tse_sgmii_gx
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"