diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index e013abb8e6e089ca931cd1fe74ca032c039add0c..1fa6419d859b6ff4a86641d8274badb8178adffc 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -36,25 +36,23 @@
-- . snk_in.sync determines the RAM pointer 0 or 1.
-- . The data read from that adress, the bin count, is incremented and written
-- back by bin_writer.
--- . bin_arbiter decides whether a read or write accessw takes precedence, in case
--- of simultanious RAM access requests by both bin_reader and bin_writer.
-- . Upon request (ram_miso), the bin counts (the histogram) are output on
-- ram_mosi.
--- bin_reader_miso bin_arbiter_rd_miso
--- __________ | ___________ | ___________
--- | | | | | | | |
--- ---snk_in--->|bin_reader|<--+--| |<--+--| |
--- |__________| | | | |
--- | | | | |
--- | | | | |
--- bin_reader_to_writer_mosi |bin_arbiter| | RAM(1..0) |----ram_mosi--->
--- | | | | |
--- ____v_____ | | | |
--- | | | | | |
--- |bin_writer|---+->| |---+->| |
--- |__________| | |___________| | |___________|
--- | |
--- bin_writer_mosi bin_arbiter_wr_mosi
+-- bin_reader_miso
+-- __________ __________ | ___________
+-- | | | | | | |
+-- ---snk_in--->| reduce |----->|bin_reader|<--+---| |
+-- |__________| |__________| | |
+-- | | |
+-- | | |
+-- bin_reader_to_writer_mosi | RAM(1..0) |----ram_mosi--->
+-- | | |
+-- ____v_____ | |
+-- | | | |
+-- |bin_writer|---+-->| |
+-- |__________| | |___________|
+-- |
+-- bin_writer_mosi
-- Usage:
-- . The ram_mosi input applies to the RAM page that is inactive (not
-- being written to from data path) *at that time*. The user should take care to
@@ -137,8 +135,8 @@ ARCHITECTURE rtl OF st_histogram IS
-------------------------------------------------------------------------------
SIGNAL bin_reader_mosi : t_mem_mosi;
SIGNAL bin_reader_miso : t_mem_miso;
-
SIGNAL prv_bin_reader_mosi : t_mem_mosi;
+
-------------------------------------------------------------------------------
-- bin_writer
-------------------------------------------------------------------------------
@@ -146,31 +144,26 @@ ARCHITECTURE rtl OF st_histogram IS
SIGNAL bin_reader_to_writer_count : NATURAL;
SIGNAL nxt_bin_reader_to_writer_count : NATURAL;
- SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
- SIGNAL bin_writer_mosi : t_mem_mosi;
+ SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
+ SIGNAL bin_writer_mosi : t_mem_mosi;
-------------------------------------------------------------------------------
-- bin_arbiter
-------------------------------------------------------------------------------
- SIGNAL bin_arbiter_wr_ram_pointer : STD_LOGIC;
- SIGNAL bin_arbiter_rd_ram_pointer : STD_LOGIC;
- SIGNAL prv_bin_arbiter_rd_ram_pointer : STD_LOGIC;
+ SIGNAL bin_writer_ram_pointer : STD_LOGIC;
+ SIGNAL bin_reader_ram_pointer : STD_LOGIC;
+ SIGNAL prv_bin_reader_ram_pointer : STD_LOGIC;
- SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_miso : t_mem_miso;
-------------------------------------------------------------------------------
-- 2x RAM (common_ram_r_w) instances
-------------------------------------------------------------------------------
CONSTANT c_nof_ram_pages : NATURAL := 2;
-
- CONSTANT c_ram : t_c_mem := (latency => 1,
- adr_w => c_ram_adr_w,
- dat_w => c_ram_dat_w,
- nof_dat => g_nof_bins,
- init_sl => '0');
+ CONSTANT c_ram : t_c_mem := (latency => 1,
+ adr_w => c_ram_adr_w,
+ dat_w => c_ram_dat_w,
+ nof_dat => g_nof_bins,
+ init_sl => '0');
SIGNAL common_ram_r_w_wr_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
SIGNAL common_ram_r_w_rd_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
@@ -357,16 +350,16 @@ BEGIN
-------------------------------------------------------------------------------
- -- bin_writer : Increment the bin, forward write request to bin_arbiter
+ -- bin_writer : Increment the bin, do write request
-- . Input : bin_reader_to_writer_mosi (from bin_reader = bin + bin count)
- -- . Output : bin_writer_mosi (to bin_arbiter = bin + incremented bin count)
+ -- . Output : bin_writer_mosi
-------------------------------------------------------------------------------
nxt_bin_writer_mosi.rd <= '0';
nxt_bin_writer_mosi.wr <= bin_reader_to_writer_mosi.wr;
nxt_bin_writer_mosi.address <= bin_reader_to_writer_mosi.address;
nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_to_writer_mosi.wrdata, bin_reader_to_writer_count) WHEN bin_reader_to_writer_mosi.wr='1' ELSE bin_writer_mosi.wrdata;
- -- Register the outputs to bin_arbiter (above we have a combinational adder = propagation delay)
+ -- Register the outputs (above we have a combinational adder = propagation delay)
p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS
BEGIN
IF dp_rst = '1' THEN
@@ -377,66 +370,42 @@ BEGIN
END PROCESS;
- -------------------------------------------------------------------------------
- -- bin_arbiter : Take care of simultaneous rd/wr to the same RAM address
- -- . Input: bin_reader_mosi (wants to read bins)
- -- bin_writer_mosi (wants to write to bins)
- -- bin_arbiter_rd_miso (carries the bins requested by bin_reader)
- -- . Output: bin_arbiter_wr_mosi (wr requests to RAM)
- -- bin_arbiter_rd_mosi (rd requests to RAM)
- -- bin_reader_miso (carries the bins requested by bin_reader)
- -------------------------------------------------------------------------------
-
- -- Forward MOSI buses
- -- . RD MOSI
- bin_arbiter_rd_mosi.wr <= '0';
- bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd;
- bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
- -- . WR MOSI
- bin_arbiter_wr_mosi.rd <= '0';
- bin_arbiter_wr_mosi.wr <= bin_writer_mosi.wr;
- bin_arbiter_wr_mosi.wrdata <= bin_writer_mosi.wrdata;
- bin_arbiter_wr_mosi.address <= bin_writer_mosi.address;
-
- bin_reader_miso <= bin_arbiter_rd_miso;
-
-
-------------------------------------------------------------------------------
-- Two RAM (common_ram_r_w) instances. The user can read the histogram from the
- -- instance that is not being written to by the bin_arbiter.
- -- . Input: bin_arbiter_wr_mosi (writes bins)
- -- bin_arbiter_rd_mosi (requests to read bins to increment bin count)
+ -- instance that is not being written to by the bin_writer.
+ -- . Input: bin_writer_mosi (writes bins)
+ -- bin_reader_mosi (requests to read bins to increment bin count)
-- histogram_rd_mosi (requests to read the bins on the user side)
-- histogram_wr_mosi (on user side, auto clears RAM every sync)
-- . Output: histogram_rd_miso (carries the bins the user wants to read)
- -- bin_arbiter_miso (carries then bins the bin_reader wants to read)
+ -- bin_reader_miso (carries then bins the bin_reader wants to read)
-- . Note: the ram_pointer is carried (with different latencies) as MSbit in:
- -- . bin_arbiter_wr_mosi.address
- -- . bin_arbiter_rd_mosi.address
+ -- . bin_writer_mosi.address
+ -- . bin_reader_mosi.address
-------------------------------------------------------------------------------
- bin_arbiter_wr_ram_pointer <= bin_arbiter_wr_mosi.address(c_ram_adr_w);
- bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_mosi.address(c_ram_adr_w);
+ bin_writer_ram_pointer <= bin_writer_mosi.address(c_ram_adr_w);
+ bin_reader_ram_pointer <= bin_reader_mosi.address(c_ram_adr_w);
-- Store the previous RAM pointer of the read bus
p_prv_ram_pointer : PROCESS(dp_clk, dp_rst) IS
BEGIN
IF dp_rst = '1' THEN
- prv_bin_arbiter_rd_ram_pointer <= '0';
+ prv_bin_reader_ram_pointer <= '0';
ELSIF RISING_EDGE(dp_clk) THEN
- prv_bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_ram_pointer;
+ prv_bin_reader_ram_pointer <= bin_reader_ram_pointer;
END IF;
END PROCESS;
- -- Let bin_arbiter write RAM 0 while user reads RAM 1 and vice versa
- common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='0' ELSE histogram_wr_mosi;
- common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='0' ELSE histogram_rd_mosi;
- common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='1' ELSE histogram_wr_mosi;
- common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='1' ELSE histogram_rd_mosi;
+ -- Let bin_writter write RAM 0 while user reads RAM 1 and vice versa
+ common_ram_r_w_wr_mosi_arr(0) <= bin_writer_mosi WHEN bin_writer_ram_pointer='0' ELSE histogram_wr_mosi;
+ common_ram_r_w_rd_mosi_arr(0) <= bin_reader_mosi WHEN bin_reader_ram_pointer='0' ELSE histogram_rd_mosi;
+ common_ram_r_w_wr_mosi_arr(1) <= bin_writer_mosi WHEN bin_writer_ram_pointer='1' ELSE histogram_wr_mosi;
+ common_ram_r_w_rd_mosi_arr(1) <= bin_reader_mosi WHEN bin_reader_ram_pointer='1' ELSE histogram_rd_mosi;
- -- Let bin_arbiter read RAM 0 while user reads RAM 1 and vice versa
- -- . We always want the MISO bus to switch 1 cycle later than the MOSI (such that the MM operation can finish); hence using prv_bin_arbiter_rd_ram_pointer.
- bin_arbiter_rd_miso <= common_ram_r_w_rd_miso_arr(0) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
- histogram_rd_miso <= common_ram_r_w_rd_miso_arr(1) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
+ -- Let bin_reader read RAM 0 while user reads RAM 1 and vice versa
+ -- . We always want the MISO bus to switch 1 cycle later than the MOSI (such that the MM operation can finish); hence using prv_bin_reader_ram_pointer.
+ bin_reader_miso <= common_ram_r_w_rd_miso_arr(0) WHEN prv_bin_reader_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
+ histogram_rd_miso <= common_ram_r_w_rd_miso_arr(1) WHEN prv_bin_reader_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
gen_common_ram_r_w : FOR i IN 0 TO c_nof_ram_pages-1 GENERATE
u_common_ram_r_w : ENTITY common_lib.common_ram_r_w