diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index dc978140eaaafe0b299a2849864c5465a1fba09a..e399eb4af6e50ea5285c126ec1831da8a175ead9 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -9,6 +9,9 @@ synth_files =
src/vhdl/ddrctrl_input_pack.vhd
src/vhdl/ddrctrl_input_repack.vhd
src/vhdl/ddrctrl_input.vhd
+ src/vhdl/ddrctrl_output_unpack.vhd
+ src/vhdl/ddrctrl_output_repack.vhd
+ src/vhdl/ddrctrl_output.vhd
src/vhdl/ddrctrl_controller.vhd
src/vhdl/ddrctrl.vhd
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 8c751dcb3925ac03f4ed0bdf0110c3a66c36865d..f9d7419f6564895b29f0487983d5c53845c136cb 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -59,9 +59,9 @@ ENTITY ddrctrl IS
mm_clk : IN STD_LOGIC := '0';
mm_rst : IN STD_LOGIC := '0';
in_sosi_arr : IN t_dp_sosi_arr; -- input data
- wr_not_rd : IN STD_LOGIC := '0';
stop_in : IN STD_LOGIC := '0';
+ out_sosi_arr : OUT t_dp_sosi_arr;
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
@@ -85,6 +85,7 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr );
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_rd_fifo_uw_w : NATURAL := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
-- signals for connecting the components
SIGNAL ctrl_clk : STD_LOGIC;
@@ -93,13 +94,23 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL out_adr : NATURAL := 0;
SIGNAL dvr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
+ SIGNAL dvr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stop : STD_LOGIC;
-
+ SIGNAL rd_fifo_usedw: STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
+ SIGNAL rd_ready : STD_LOGIC;
+ SIGNAL inp_ds : NATURAL;
+ SIGNAL inp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL inp_bsn_adr : NATURAL;
+ SIGNAL outp_ds : NATURAL;
+ SIGNAL outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
BEGIN
+ rd_siso.ready <= rd_ready;
+ rd_siso.xon <= '1';
-- input to io_ddr
u_ddrctrl_input : ENTITY work.ddrctrl_input
@@ -116,7 +127,10 @@ BEGIN
in_stop => stop,
out_of => out_of,
out_sosi => out_sosi,
- out_adr => out_adr
+ out_adr => out_adr,
+ out_bsn_ds => inp_ds,
+ out_bsn => inp_bsn,
+ out_bsn_adr => inp_bsn_adr
);
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
@@ -160,7 +174,7 @@ BEGIN
dvr_clk => clk,
dvr_rst => rst,
- dvr_miso => open,
+ dvr_miso => dvr_miso,
dvr_mosi => dvr_mosi,
-- Write FIFO clock domain
@@ -175,8 +189,8 @@ BEGIN
rd_clk => clk,
rd_rst => rst,
- rd_fifo_usedw => open,
- rd_sosi => open,
+ rd_fifo_usedw => rd_fifo_usedw,
+ rd_sosi => rd_sosi,
rd_siso => rd_siso,
term_ctrl_out => term_ctrl_out,
@@ -193,26 +207,64 @@ BEGIN
phy4_ou => phy4_ou
);
+ -- reading ddr memory
+ u_ddrctrl_output : ENTITY work.ddrctrl_output
+ GENERIC MAP(
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => g_sim_model,
+ g_in_data_w => c_io_ddr_data_w,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ PORT MAP(
+ clk => clk,
+ rst => rst,
+
+ in_sosi => rd_sosi,
+ in_ds => outp_ds,
+ in_bsn => outp_bsn,
+
+ out_sosi_arr => out_sosi_arr,
+ out_ready => rd_ready
+ );
+
-- controller of ddrctrl
u_ddrctrl_controller : ENTITY work.ddrctrl_controller
GENERIC MAP(
g_tech_ddr => g_tech_ddr,
- g_stop_percentage => g_stop_percentage
+ g_stop_percentage => g_stop_percentage,
+ g_nof_streams => g_nof_streams,
+ g_out_data_w => g_data_w,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_rd_fifo_uw_w => c_rd_fifo_uw_w
)
PORT MAP(
- clk => clk,
- rst => rst,
-
- inp_of => out_of,
- inp_sosi => out_sosi,
- inp_adr => out_adr,
+ clk => clk,
+ rst => rst,
+
+ -- ddrctrl_input
+ inp_of => out_of,
+ inp_sosi => out_sosi,
+ inp_adr => out_adr,
+ inp_ds => inp_ds,
+ inp_bsn => inp_bsn,
+ inp_bsn_adr => inp_bsn_adr,
+
+ -- io_ddr
+ dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ wr_sosi => wr_sosi,
+ rd_fifo_usedw => rd_fifo_usedw,
- dvr_mosi => dvr_mosi,
- wr_sosi => wr_sosi,
- rd_siso => rd_siso,
+ -- ddrctrl_output
+ outp_ds => outp_ds,
+ outp_bsn => outp_bsn,
- stop_in => stop_in,
- stop_out => stop
+ -- ddrctrl_controller
+ stop_in => stop_in,
+ stop_out => stop
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 67a471ccf8bf7afed700c5788704fad3a61cfcc7..106dbaf1f8fdc877eae1ce30799c56c734cfb901 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -39,7 +39,13 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddrctrl_controller IS
GENERIC (
g_tech_ddr : t_c_tech_ddr;
- g_stop_percentage : NATURAL := 50
+ g_stop_percentage : NATURAL := 50;
+ g_nof_streams : NATURAL;
+ g_out_data_w : NATURAL;
+ g_wr_data_w : NATURAL;
+ g_rd_fifo_depth : NATURAL;
+ g_rd_data_w : NATURAL;
+ g_rd_fifo_uw_w : NATURAL
);
PORT (
clk : IN STD_LOGIC;
@@ -49,13 +55,21 @@ ENTITY ddrctrl_controller IS
inp_of : IN NATURAL;
inp_sosi : IN t_dp_sosi;
inp_adr : IN NATURAL;
+ inp_ds : IN NATURAL;
+ inp_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ inp_bsn_adr : IN NATURAL;
-- io_ddr
dvr_mosi : OUT t_mem_ctlr_mosi;
+ dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi;
- rd_siso : OUT t_dp_siso;
+ rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
- -- ddrctrl
+ -- ddrctrl_output
+ outp_ds : OUT NATURAL;
+ outp_bsn : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- ddrctrl_controller
stop_in : IN STD_LOGIC;
stop_out : OUT STD_LOGIC
);
@@ -70,25 +84,35 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_pof_ma : NATURAL := (c_max_adr*(100-g_stop_percentage))/100;
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
+ -- constant for reading
+ CONSTANT c_rd_data_w : NATURAL := g_nof_streams*g_out_data_w; -- 168
+ CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
+ CONSTANT c_max_read_cnt : NATURAL := (c_max_adr+1)/c_burstsize; -- 256
+
-- type for statemachine
- TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, READING, STOP_READING, IDLE);
+ TYPE t_state IS (RESET, WRITING, SET_STOP, STOP_WRITING, START_READING, READING, STOP_READING, IDLE);
-- record for readability
TYPE t_reg IS RECORD
-- state of program
state : t_state;
- -- signals
+ -- stopping signals
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stopped : STD_LOGIC;
+ -- reading signals
+ outp_ds : NATURAL;
+ outp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ read_cnt : NATURAL;
+ rd_burst_en : STD_LOGIC;
+
-- output
dvr_mosi : t_mem_ctlr_mosi;
wr_sosi : t_dp_sosi;
- rd_siso : t_dp_siso;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, TO_UVEC(c_max_adr, c_adr_w), '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init, c_dp_siso_rst);
+ CONSTANT c_t_reg_init : t_reg := (RESET, TO_UVEC(c_max_adr, c_adr_w), '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-- signals for readability
@@ -100,23 +124,24 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr, dvr_miso, rd_fifo_usedw)
VARIABLE v : t_reg := c_t_reg_init;
BEGIN
v := q_reg;
- CASE q_reg.state IS
-
+ CASE q_reg.state IS
WHEN RESET =>
v := c_t_reg_init;
WHEN WRITING =>
- IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- if adr mod c_burstsize = 0
+ -- if adr mod c_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
v.dvr_mosi.burstbegin := '1';
IF inp_adr = 0 THEN
v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
@@ -132,7 +157,6 @@ BEGIN
v.wr_sosi := inp_sosi;
-
WHEN SET_STOP =>
--setting a stop address dependend on the g_stop_percentage
IF inp_adr+c_pof_ma >= c_max_adr THEN
@@ -143,7 +167,9 @@ BEGIN
v.stop_adr(c_bitshift_adr-1 DOWNTO 0) := c_zeros;
-- still a write cyle
- IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- adr mod 64 = 0
+ -- if adr mod c_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
v.dvr_mosi.burstbegin := '1';
IF inp_adr = 0 THEN
v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
@@ -159,41 +185,102 @@ BEGIN
v.wr_sosi := inp_sosi;
-
WHEN STOP_WRITING =>
- v.stopped := '1';
- v.wr_sosi.valid := '0';
- v.dvr_mosi.flush := '1';
+ v.dvr_mosi.burstbegin := '0';
+ -- wait until the write burst is finished
+ IF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
+ v.stopped := '1';
+ v.wr_sosi.valid := '0';
+ v.dvr_mosi.flush := '1';
+ v.state := START_READING;
+ ELSE
+ v.state := STOP_WRITING;
+ END IF;
+
+
+ WHEN START_READING =>
+ v.rd_burst_en := '1';
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.outp_ds := inp_ds;
+
+ FOR I IN 0 TO inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)) LOOP -- takes a while WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
+ IF v.outp_ds-c_rest <= 0 THEN
+ v.outp_ds := v.outp_ds+c_rd_data_w-c_rest;
+ ELSE
+ v.outp_ds := v.outp_ds-c_rest;
+ END IF;
+ END LOOP;
+
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
+ v.state := READING;
+
+
+ WHEN READING =>
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ IF TO_UINT(rd_fifo_usedw) <= 10 AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' AND dvr_miso.done = '1' THEN
+ IF TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt >= c_max_adr THEN
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC((TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt)-c_max_adr-1, c_adr_w);
+ ELSE
+ v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.stop_adr(c_adr_w-1 DOWNTO 0))+c_burstsize*q_reg.read_cnt, c_adr_w);
+ END IF;
+ v.dvr_mosi.burstbegin := '1';
+ v.read_cnt := v.read_cnt+1;
+ v.rd_burst_en := '0';
+ ELSE
+ v.dvr_mosi.burstbegin := '0';
+ END IF;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ IF TO_UINT(rd_fifo_usedw) = 11 THEN
+ v.rd_burst_en := '1';
+ END IF;
+
+ IF q_reg.read_cnt >= c_max_read_cnt THEN
+ v.state := IDLE;
+ ELSE
+ v.state := READING;
+ END IF;
+
+
WHEN IDLE =>
-
+ -- the statemachine goes to Idle when its finished or when its waiting on other components.
WHEN OTHERS =>
v := c_t_reg_init;
-
END CASE;
+
+ IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
+ IF stop_in = '1' THEN
+ v.state := SET_STOP;
+ ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSIF v.stopped = '1' THEN
+ v.state := IDLE;
+ ELSE
+ v.state := WRITING;
+ END IF;
+ END IF;
+
+
IF rst = '1' THEN
v.state := RESET;
- ELSIF stop_in = '1' THEN
- v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
- v.state := STOP_WRITING;
- ELSIF v.stopped = '1' THEN
- v.state := IDLE;
- ELSE
- v.state := WRITING;
END IF;
+
d_reg <= v;
+
END PROCESS;
-- fill outputs
dvr_mosi <= q_reg.dvr_mosi;
wr_sosi <= q_reg.wr_sosi;
- rd_siso <= q_reg.rd_siso;
stop_out <= q_reg.stopped;
+ outp_bsn <= q_reg.outp_bsn;
+ outp_ds <= q_reg.outp_ds;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index 88b7e492bf4950c0fbef9e5bad964b4373e9475d..e08d57fcd78e6dfd07a82ec125985d621c877a20 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -53,7 +53,7 @@ ENTITY ddrctrl_input IS
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr; -- input data
- in_stop : IN STD_LOGIC;
+ in_stop : IN STD_LOGIC;
out_of : OUT NATURAL; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi; -- output data
out_adr : OUT NATURAL;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b93fb05eb0e3fdc4bdae44a7b8c69534a147509f
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: when there is output this component will turn it back into a
+-- sosi arr.
+--
+-- Description:
+-- The data from the ddr memory gets resized into its original size and gets
+-- back its bsn.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY ddrctrl_output IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr; -- type of memory
+ g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
+ g_in_data_w : NATURAL := 576;
+ g_nof_streams : NATURAL := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
+ );
+ PORT (
+ clk : IN STD_LOGIC := '0';
+ rst : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi := c_dp_sosi_init; -- input data
+ in_ds : IN NATURAL; -- amount of internal overflow this output
+ in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); -- bsn corresponding to the data at in_data[in_of]
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- output data
+ out_ready : OUT STD_LOGIC
+ );
+END ddrctrl_output;
+
+
+ARCHITECTURE str OF ddrctrl_output IS
+
+ -- constant for readability
+ CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data width for ddrctrl_repack 168
+
+ -- signals for connecting the components
+ SIGNAL sosi : t_dp_sosi := c_dp_sosi_init;
+
+BEGIN
+
+ -- makes one data vector out of all the data from the t_dp_sosi_arr
+ u_ddrctrl_output_unpack : ENTITY work.ddrctrl_output_unpack
+ GENERIC MAP(
+ g_tech_ddr => g_tech_ddr,
+ g_in_data_w => g_in_data_w,
+ g_out_data_w => c_out_data_w
+ )
+ PORT MAP(
+ clk => clk,
+ rst => rst,
+ in_sosi => in_sosi, -- input data
+ in_ds => in_ds,
+ in_bsn => in_bsn,
+ out_sosi => sosi, -- output data
+ out_ready => out_ready
+ );
+
+ -- resizes the input data vector so that the output data vector can be stored into the ddr memory
+ u_ddrctrl_output_repack : ENTITY work.ddrctrl_output_repack
+ GENERIC MAP(
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ PORT MAP(
+ in_sosi => sosi,
+ out_sosi_arr => out_sosi_arr
+ );
+
+END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9c8555f3ea8561de24a5de65de0aeaf88bd57c69
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -0,0 +1,58 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Spread out the input sosi over a sosi array.
+--
+-- Description:
+-- The input sosi gets split up and spread out over the sosi array.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- The output vector must be larger than the input vector.
+
+LIBRARY IEEE, dp_lib, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY ddrctrl_output_repack IS
+ GENERIC (
+ g_nof_streams : POSITIVE := 12;
+ g_data_w : NATURAL := 14
+ );
+ PORT (
+ in_sosi : IN t_dp_sosi := c_dp_sosi_init;
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init)
+ );
+END ddrctrl_output_repack;
+
+ARCHITECTURE rtl OF ddrctrl_output_repack IS
+
+BEGIN
+
+ -- putting the data from the stream into different streams.
+ gen_repack_data : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ out_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= in_sosi.data(g_data_w*(I+1)-1 DOWNTO g_data_w*I);
+ out_sosi_arr(I).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ out_sosi_arr(I).valid <= in_sosi.valid;
+ END GENERATE;
+
+END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fb711ef3da9abacde5ab36cbff84d63468988e8f
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -0,0 +1,260 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: resize the data into a single sosi with a width of g_out_data_w.
+--
+-- Description:
+-- The data gets collected into a vector(c_v) and from this vector the output
+-- data gets read. When the reading passes the halfway point of c_v new data
+-- is requested and the whole vector shifts g_in_data_w amount of bits to fit
+-- the new data at the end.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- The output vector must be larger than the input vector.
+
+LIBRARY IEEE, dp_lib, tech_ddr_lib, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY ddrctrl_output_unpack IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr;
+ g_in_data_w : NATURAL;
+ g_out_data_w : NATURAL
+ );
+ PORT (
+ clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi := c_dp_sosi_init;
+ in_ds : IN NATURAL;
+ in_bsn : IN STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init;
+ out_ready : OUT STD_LOGIC := '0'
+ );
+END ddrctrl_output_unpack;
+
+
+ARCHITECTURE rtl OF ddrctrl_output_unpack IS
+
+ -- type for statemachine
+ TYPE t_state IS ( READING, FIRST_READ, SECOND_READ, OVER_HALF, RESET, IDLE, OFF);
+
+ -- record for readability
+ TYPE t_reg IS RECORD
+ state : t_state;
+ a_of : NATURAL;
+ op_data_cnt : NATURAL;
+ delay_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
+ dd_fresh : STD_LOGIC;
+ c_v : STD_LOGIC_VECTOR(g_in_data_w*2-1 DOWNTO 0);
+ sr_done : STD_LOGIC;
+ out_sosi : t_dp_sosi;
+ out_ready : STD_LOGIC;
+ END RECORD;
+
+ CONSTANT c_t_reg_init : t_reg := (RESET, 0, 0, (OTHERS => '0'), '0', (OTHERS => '0'), '0', c_dp_sosi_init, '0');
+
+
+ -- signals for readability
+ SIGNAL d_reg : t_reg := c_t_reg_init;
+ SIGNAL q_reg : t_reg := c_t_reg_init;
+
+BEGIN
+
+ q_reg <= d_reg WHEN rising_edge(clk);
+
+ -- put the input data into c_v and fill the output vector from c_v
+ p_state : PROCESS(q_reg, rst, in_sosi, in_ds, in_bsn)
+
+ VARIABLE v : t_reg;
+
+ BEGIN
+
+ v := q_reg;
+
+ CASE q_reg.state IS
+ WHEN READING =>
+ -- generating output from the data already present in c_v
+ v.out_ready := '0';
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.op_data_cnt := q_reg.op_data_cnt+1;
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ v.state := OVER_HALF;
+ ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
+ v.state := IDLE;
+ ELSE
+ v.state := READING;
+ END IF;
+
+
+
+ WHEN OVER_HALF =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
+ v.out_ready := '1';
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := q_reg.c_v((g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-1 DOWNTO (g_out_data_w*q_reg.op_data_cnt)+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w);
+ v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.a_of := (g_out_data_w*(q_reg.op_data_cnt+1))+q_reg.a_of-g_in_data_w;
+ v.op_data_cnt := 0;
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ v.state := OVER_HALF;
+ ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
+ v.state := IDLE;
+ ELSE
+ v.state := READING;
+ END IF;
+
+
+
+ WHEN FIRST_READ =>
+ -- fills the first half of c_v and generates a output from it.
+ v.out_ready := '0';
+ v.c_v(g_in_data_w-1 DOWNTO 0) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.a_of := in_ds+2-((12-5)*14); -- will be fixed after in_ds is fixed in ddrctrl_controller.
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w+v.a_of-1 DOWNTO v.a_of);
+ v.out_sosi.valid := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF v.dd_fresh = '1' THEN
+ v.state := SECOND_READ;
+ ELSE
+ v.state := IDLE;
+ END IF;
+
+ WHEN SECOND_READ =>
+ -- fills the second half of c_v and generates a output from it.
+ v.out_ready := '0';
+ v.c_v(g_in_data_w*2-1 DOWNTO g_in_data_w) := q_reg.delay_data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '0';
+ v.out_sosi.data(g_out_data_w-1 DOWNTO 0) := v.c_v(g_out_data_w*2+q_reg.a_of-1 DOWNTO g_out_data_w+q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.op_data_cnt := 2;
+ v.sr_done := '1';
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
+ v.state := OVER_HALF;
+ ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
+ v.state := IDLE;
+ ELSE
+ v.state := READING;
+ END IF;
+
+
+ WHEN RESET =>
+ v := c_t_reg_init;
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+ v.state := OFF;
+
+
+ WHEN IDLE =>
+ -- the statemachine goes to Idle when its finished or when its waiting on other components.
+ v.out_ready := '1';
+ v.out_sosi.valid := '0';
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
+ v.state := OVER_HALF;
+ ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN
+ v.state := SECOND_READ;
+ ELSE
+ v.state := IDLE;
+ END IF;
+
+
+
+ WHEN OFF =>
+ -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
+ v.out_ready := '1';
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+
+ IF in_sosi.valid = '1' THEN
+ v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
+ v.dd_fresh := '1';
+ END IF;
+
+
+ IF in_sosi.valid = '1' THEN
+ v.state := FIRST_READ;
+ ELSE
+ v.state := OFF;
+ END IF;
+
+
+
+ END CASE;
+
+ IF rst = '1' THEN
+ v.state := RESET;
+ END IF;
+ d_reg <= v;
+ END PROCESS;
+
+ -- fill outputs
+ out_sosi <= q_reg.out_sosi;
+ out_ready <= q_reg.out_ready;
+
+
+END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index f6f7b8fb92b150df8038e553c9210d64143b2f83..212ecd8d2fa292824ee09750ac7fe0478ae6ea38 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -50,31 +50,41 @@ END tb_ddrctrl;
ARCHITECTURE tb OF tb_ddrctrl IS
- -- constants for testbench
- CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
- CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
- CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
- CONSTANT c_mm_clk_freq : NATURAL := 100; -- mm clock frequency in MHz
- CONSTANT c_mm_clk_period : TIME := (10**6 / c_mm_clk_freq) * 1 ps; -- mm clock period, 10 ns
- CONSTANT c_sim_length : NATURAL := (g_sim_length*576)/168; -- amount of input words that get put into the DUT
+ CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
-- Select DDR3 or DDR4 dependent on the technology and sim model
CONSTANT c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
CONSTANT c_sim_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_sim_model, c_sim_ddr, c_mem_ddr);
-
-- constants for readability
+ CONSTANT c_ctrl_data_w : NATURAL := func_tech_ddr_ctlr_data_w( c_tech_ddr ); -- 576
CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
+ -- constants for testbench
+ CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
+ CONSTANT c_clk_period : TIME := (10**6/c_clk_freq)*1 ps; -- clock priod, 5 ns
+ CONSTANT c_mm_clk_freq : NATURAL := 100; -- mm clock frequency in MHz
+ CONSTANT c_mm_clk_period : TIME := (10**6/c_mm_clk_freq)*1 ps; -- mm clock period, 10 ns
+ CONSTANT c_sim_length : NATURAL := (g_sim_length*c_ctrl_data_w)/c_in_data_w; -- amount of input words that get put into the DUT
+
+ -- constant for checking output data
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( c_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
+ CONSTANT c_output_stop_adr : NATURAL := (c_max_adr+1)-((((c_max_adr+1)/64)*g_stop_percentage/100)*64);
+ CONSTANT c_output_ds : NATURAL := 144;
+
+
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*c_sim_length-1 DOWNTO 0);
VARIABLE conv : STD_LOGIC_VECTOR(32-1 DOWNTO 0); -- removes a warning
BEGIN
- FOR I IN 0 TO c_sim_length*g_nof_streams-1 LOOP
+ FOR I IN 0 TO c_sim_length-1 LOOP
conv := TO_UVEC(I, 32);
- temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := conv(g_data_w-1 DOWNTO 0);
+ FOR J IN 0 TO g_nof_streams-1 LOOP
+ temp(g_data_w*((I*g_nof_streams)+J+1)-1 DOWNTO g_data_w*((I*g_nof_streams)+j)) := conv(g_data_w-1 DOWNTO 0);
+ END LOOP;
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
@@ -93,9 +103,9 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
- SIGNAL wr_not_rd : STD_LOGIC;
SIGNAL stop_in : STD_LOGIC := '0';
SIGNAL bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
-- testbench signal
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
@@ -104,12 +114,16 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
+ -- signals for checking the output data
+ SIGNAL output_data_cnt : NATURAL := 0;
+
-- PHY
SIGNAL phy3_io : t_tech_ddr3_phy_io;
SIGNAL phy3_ou : t_tech_ddr3_phy_ou;
SIGNAL phy4_io : t_tech_ddr4_phy_io;
SIGNAL phy4_ou : t_tech_ddr4_phy_ou;
+
BEGIN
-- generating clock
@@ -132,7 +146,6 @@ BEGIN
rst <= '0';
mm_rst <= '0';
test_running <= '1';
- wr_not_rd <= '1';
WAIT FOR c_clk_period*1;
@@ -145,16 +158,15 @@ BEGIN
END LOOP;
in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
bsn <= INCR_UVEC(bsn, 1);
+ IF K = 1 AND J = 0 THEN
+ stop_in <= '1';
+ ELSE
+ stop_in <= '0';
+ END IF;
WAIT FOR c_clk_period*1;
END LOOP;
- IF k = 1 THEN
- stop_in <= '1';
- ELSE
- stop_in <= '0';
- END IF;
END LOOP;
test_running <= '0';
- wr_not_rd <= '0';
-- stopping the testbench
@@ -163,6 +175,21 @@ BEGIN
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
+ p_checking_output_data : PROCESS -- first do tickets L2SDP-708 and L2SDP-707 before finsishing this is worth time
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ IF out_sosi_arr(0).valid = '1' THEN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ IF c_output_stop_adr+output_data_cnt <= c_max_adr THEN
+ --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
+ ELSE
+ --ASSERT out_sosi_arr(I).data(c_in_data_w-1 DOWNTO 0) = c_total_vector(g_data_w*(I+1)+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w-1 DOWNTO g_data_w*I+(c_output_stop_adr+output_data_cnt-c_max_adr)*c_ctrl_data_w) REPORT "wrong output data at: " & NATURAL'image(c_output_stop_adr+output_data_cnt) SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ output_data_cnt <= output_data_cnt+1;
+ END IF;
+ WAIT FOR c_clk_period*1;
+ END PROCESS;
@@ -182,8 +209,8 @@ BEGIN
mm_clk => mm_clk,
mm_rst => mm_rst,
in_sosi_arr => in_sosi_arr,
- wr_not_rd => wr_not_rd,
stop_in => stop_in,
+ out_sosi_arr => out_sosi_arr,
--PHY
phy3_io => phy3_io,