From 78cc0fa35ad5f955b1eddbcfd84b5a5dcb9aa7ab Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 28 Nov 2022 14:33:08 +0100
Subject: [PATCH] Rename eth_tester ports to match upe_gear peripheral names.
---
.../qsys_unb2c_test_nios2_gen2_0.ip | 4 +-
...unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip} | 28 +-
...unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip} | 28 +-
...unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip} | 28 +-
...unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip} | 28 +-
...p => qsys_unb2c_test_reg_diag_bg_eth_0.ip} | 28 +-
...p => qsys_unb2c_test_reg_diag_bg_eth_1.ip} | 28 +-
...test_reg_eth1g_II_strobe_total_count_rx.ip | 1535 -----------------
...test_reg_eth1g_II_strobe_total_count_tx.ip | 1535 -----------------
...p => qsys_unb2c_test_reg_hdr_dat_eth_0.ip} | 28 +-
...p => qsys_unb2c_test_reg_hdr_dat_eth_1.ip} | 28 +-
...c_test_reg_strobe_total_count_rx_eth_0.ip} | 28 +-
...2c_test_reg_strobe_total_count_rx_eth_1.ip | 1535 +++++++++++++++++
...c_test_reg_strobe_total_count_tx_eth_0.ip} | 28 +-
...2c_test_reg_strobe_total_count_tx_eth_1.ip | 1535 +++++++++++++++++
.../src/vhdl/qsys_unb2c_test_pkg.vhd | 872 +++++-----
doc/erko_howto_tools.txt | 2 +
17 files changed, 3650 insertions(+), 3648 deletions(-)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip => qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip => qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip => qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip => qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip => qsys_unb2c_test_reg_diag_bg_eth_0.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip => qsys_unb2c_test_reg_diag_bg_eth_1.ip} (98%)
delete mode 100644 boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
delete mode 100644 boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip => qsys_unb2c_test_reg_hdr_dat_eth_0.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip => qsys_unb2c_test_reg_hdr_dat_eth_1.ip} (98%)
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip => qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip} (98%)
create mode 100644 boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
rename boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/{qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip => qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip} (98%)
create mode 100644 boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
index b46dd29e27..1cd44510b7 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /><slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /><slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /><slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /><slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /><slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /><slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /><slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /><slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /><slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /><slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /><slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3584,7 +3584,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_rx.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_rx.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs2_eth_coe_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bsn_monitor_v2_tx.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_strobe_total_count_tx.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_hdr_dat.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='avs2_eth_coe_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_rx.mem' start='0x1C900' end='0x1C980' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_strobe_total_count_tx.mem' start='0x1C980' end='0x1CA00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_hdr_dat.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /&gt;&lt;slave name='reg_eth1g_I_bg_ctrl.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bg_ctrl.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_rx.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /&gt;&lt;slave name='reg_eth1g_II_bsn_monitor_v2_tx.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_eth_0.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_rx_eth_0.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='avs_eth_1.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_1.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx_eth_0.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back1.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_tx_eth_0.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat_eth_0.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_eth10g_qsfp_ring.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x8000' end='0xC000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0xC000' end='0xE000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0xE000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_10GbE.mem' start='0x18000' end='0x1A000' datawidth='32' /&gt;&lt;slave name='avs_eth_1.mms_ram' start='0x1A000' end='0x1B000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x1B000' end='0x1C000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x1C000' end='0x1C800' datawidth='32' /&gt;&lt;slave name='reg_eth10g_back0.mem' start='0x1C800' end='0x1C900' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_rx_eth_1.mem' start='0x1C900' end='0x1C980' datawidth='32' /&gt;&lt;slave name='reg_strobe_total_count_tx_eth_1.mem' start='0x1C980' end='0x1CA00' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat_eth_1.mem' start='0x1CA00' end='0x1CA80' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_eth_0.mem' start='0x1CA80' end='0x1CB00' datawidth='32' /&gt;&lt;slave name='reg_heater.mem' start='0x1CB00' end='0x1CB80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x1CB80' end='0x1CC00' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x1CC00' end='0x1CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_10gbe.mem' start='0x1CC80' end='0x1CD00' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x1CD00' end='0x1CD40' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_10gbe.mem' start='0x1CD40' end='0x1CD80' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1CD80' end='0x1CDC0' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_eth_1.mem' start='0x1CDC0' end='0x1CDE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_eth_1.mem' start='0x1CDE0' end='0x1CE00' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx_eth_1.mem' start='0x1CE00' end='0x1CE20' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x1CE20' end='0x1CE40' datawidth='32' /&gt;&lt;slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x1CE40' end='0x1CE60' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_10gbe.mem' start='0x1CE60' end='0x1CE80' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x1CE80' end='0x1CEA0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x1CEA0' end='0x1CEC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1CEC0' end='0x1CEE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x1CEE0' end='0x1CEF0' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x1CEF0' end='0x1CF00' datawidth='32' /&gt;&lt;slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x1CF00' end='0x1CF10' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1CF10' end='0x1CF20' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1CF20' end='0x1CF28' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1CF28' end='0x1CF30' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1CF30' end='0x1CF38' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x1CF38' end='0x1CF40' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x1CF40' end='0x1CF48' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x1CF48' end='0x1CF50' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /&gt;&lt;slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' datawidth='32' /&gt;&lt;slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
index 04e5061ee2..a95f4dfded 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
index d2c116b0bd..c41940a264 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
index 969b7f6029..15913842ff 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
index e5c242e722..b309529a6d 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx
+ element qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
index 8b5349883e..dee194964b 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_bg_ctrl</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_bg_ctrl
+ element qsys_unb2c_test_reg_diag_bg_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
index dba9399a1b..4145abee24 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_bg_ctrl</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_diag_bg_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_bg_ctrl
+ element qsys_unb2c_test_reg_diag_bg_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_bg_ctrl.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_diag_bg_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
deleted file mode 100644
index 60e87b3764..0000000000
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+++ /dev/null
@@ -1,1535 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>128</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>5</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>125000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U3F45E2SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>7</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
deleted file mode 100644
index 0e21ab78fc..0000000000
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+++ /dev/null
@@ -1,1535 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>128</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>4</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>5</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>125000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U3F45E2SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>2</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>128</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>7</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>125000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
index 0e9f2b1f5b..971f53f6c7 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_hdr_dat</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_hdr_dat
+ element qsys_unb2c_test_reg_hdr_dat_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
index d352a73115..8ecb89c83d 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_II_hdr_dat</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_hdr_dat_eth_1</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_II_hdr_dat
+ element qsys_unb2c_test_reg_hdr_dat_eth_1
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_II_hdr_dat.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_hdr_dat_eth_1.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
index d2b0b772d7..6673af2cc9 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx
+ element qsys_unb2c_test_reg_strobe_total_count_rx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
new file mode 100644
index 0000000000..2f553a7b5a
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_rx_eth_1</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_strobe_total_count_rx_eth_1
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
similarity index 98%
rename from boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
rename to boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
index 1cc106178b..736faa5cf0 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
- <ipxact:name>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:name>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx</ipxact:library>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx
+ element qsys_unb2c_test_reg_strobe_total_count_tx_eth_0
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
new file mode 100644
index 0000000000..516f092e78
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:library>
+ <ipxact:name>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_unb2c_test_reg_strobe_total_count_tx_eth_1</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>125000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_unb2c_test_reg_strobe_total_count_tx_eth_1
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index 4751e53edb..5c579ef596 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -26,442 +26,442 @@ PACKAGE qsys_unb2c_test_pkg IS
component qsys_unb2c_test is
port (
- avs2_eth_coe_1_reset_export : out std_logic; -- export
- avs2_eth_coe_1_clk_export : out std_logic; -- export
- avs2_eth_coe_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_tse_write_export : out std_logic; -- export
- avs2_eth_coe_1_tse_read_export : out std_logic; -- export
- avs2_eth_coe_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs2_eth_coe_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs2_eth_coe_1_reg_write_export : out std_logic; -- export
- avs2_eth_coe_1_reg_read_export : out std_logic; -- export
- avs2_eth_coe_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs2_eth_coe_1_ram_write_export : out std_logic; -- export
- avs2_eth_coe_1_ram_read_export : out std_logic; -- export
- avs2_eth_coe_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs2_eth_coe_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs2_eth_coe_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bg_ctrl_reset_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_clk_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bg_ctrl_write_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bg_ctrl_read_export : out std_logic; -- export
- reg_eth1g_ii_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_address_export : out std_logic_vector(2 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_eth1g_ii_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_hdr_dat_reset_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_clk_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_hdr_dat_write_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_hdr_dat_read_export : out std_logic; -- export
- reg_eth1g_ii_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_strobe_total_count_rx_reset_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_clk_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_rx_write_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_rx_read_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_ii_strobe_total_count_tx_reset_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_clk_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_tx_write_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_ii_strobe_total_count_tx_read_export : out std_logic; -- export
- reg_eth1g_ii_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bg_ctrl_reset_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_clk_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bg_ctrl_write_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bg_ctrl_read_export : out std_logic; -- export
- reg_eth1g_i_bg_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_address_export : out std_logic_vector(4 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_eth1g_i_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_hdr_dat_reset_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_clk_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_hdr_dat_write_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_hdr_dat_read_export : out std_logic; -- export
- reg_eth1g_i_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_strobe_total_count_rx_reset_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_clk_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_strobe_total_count_rx_write_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_strobe_total_count_rx_read_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth1g_i_strobe_total_count_tx_reset_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_clk_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth1g_i_strobe_total_count_tx_write_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth1g_i_strobe_total_count_tx_read_export : out std_logic; -- export
- reg_eth1g_i_strobe_total_count_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_eth_0_write_export : out std_logic; -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_0_read_export : out std_logic; -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_eth_1_write_export : out std_logic; -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_1_read_export : out std_logic; -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_unb2c_test;
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index c71e6e5067..65beba3761 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -115,6 +115,8 @@ during tb simulation load --> fixed by "sudo chmod a+w -R modelsim_altera_libs/1
. remove components
. add components from Uniboard library (double click avs_common_mm or use green +)
use qsys_unb2c_test_ prefix in component name ip file, but rename component without prefix
+ . use periperal names that match the upe_gear default name + instance scheme
+ double click export name to change it, none for default
. System/assign base addresses
System/assign interrupt numbers
if needed do: Sync system infos button
--
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