From 780e0e835d610a7700fca320d41e6ade87965539 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 21 Oct 2016 07:54:53 +0000
Subject: [PATCH] -Added eth_statistics to tb_arts_unb1_sc1.

---
 .../tb/vhdl/tb_arts_unb1_sc1.vhd              | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd b/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
index ed890f8556..831f75679d 100644
--- a/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/tb/vhdl/tb_arts_unb1_sc1.vhd
@@ -31,7 +31,7 @@
 --   . The X input data is different from the Y input data so we can verify that
 --     the two polarization paths are kept separate.
 
-LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, apertif_unb1_fn_bf_emu_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, apertif_unb1_fn_bf_emu_lib, eth_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
@@ -91,6 +91,10 @@ ARCHITECTURE tb OF tb_arts_unb1_sc1 IS
   SIGNAL bn_in_mesh_serial_3arr  : t_unb1_board_mesh_sl_3arr;
   SIGNAL fn_in_mesh_serial_3arr  : t_unb1_board_mesh_sl_3arr;
   SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
+
+  SIGNAL eth_statistics_serial_in_arr : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
+  SIGNAL eth_statistics_pkt_cnt       : NATURAL;
+  SIGNAL eth_statistics_pkt_len       : NATURAL;
  
 BEGIN
 
@@ -165,6 +169,7 @@ BEGIN
         -- 1GbE Control Interface
         ETH_clk     => eth_clk,
         ETH_SGIN    => '0',
+        ETH_SGOUT   => eth_statistics_serial_in_arr(i),
         
         -- Transceiver clocks
         SA_CLK      => sa_clk,
@@ -244,4 +249,16 @@ BEGIN
     );
   END GENERATE;
 
+  ------------------------------------------------------------------------------
+  -- Verify proper DUT output using Ethernet packet statistics
+  ------------------------------------------------------------------------------
+  u_eth_statistics : ENTITY eth_lib.eth_statistics
+  PORT MAP (  
+    eth_clk       => eth_clk,
+    eth_serial_in => eth_statistics_serial_in_arr(0),
+
+    pkt_cnt       => eth_statistics_pkt_cnt,
+    pkt_len       => eth_statistics_pkt_len
+  );
+
 END tb;
-- 
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