From 77934c0899928dcffe7ad2c7708463844a8c80aa Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Thu, 31 Mar 2022 17:33:08 +0200
Subject: [PATCH] only a test bench is needed for ddrctrl_controller.
---
.../lofar2/libraries/ddrctrl/hdllib.cfg | 1 -
.../libraries/ddrctrl/src/vhdl/ddrctrl.vhd | 9 +-
.../ddrctrl/src/vhdl/ddrctrl_controller.vhd | 100 ++++++++----------
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 34 ++++--
4 files changed, 77 insertions(+), 67 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index 6800878092..53fe5f5958 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -11,7 +11,6 @@ synth_files =
src/vhdl/ddrctrl_input.vhd
src/vhdl/ddrctrl_controller.vhd
src/vhdl/ddrctrl.vhd
- src/vhdl/ddrctrl_pkg.vhd
test_bench_files =
tb/vhdl/tb_ddrctrl_input_address_counter.vhd
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 507909186e..a803641e0b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -32,7 +32,7 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
-- The maximum value of the address is determend by g_tech_ddr.
-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib, lofar2_ddrctrl_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_pkg.ALL;
@@ -42,7 +42,6 @@ USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE io_ddr_lib.ALL;
-USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
ENTITY ddrctrl IS
@@ -52,8 +51,8 @@ ENTITY ddrctrl IS
g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
- g_stop_pos : t_c_stop_pos
- );
+ g_stop_percentage : NATURAL := 50
+ );
PORT (
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
@@ -196,7 +195,7 @@ BEGIN
u_ddrctrl_controller : ENTITY work.ddrctrl_controller
GENERIC MAP(
g_tech_ddr => g_tech_ddr,
- g_stop_pos => g_stop_pos
+ g_stop_percentage => g_stop_percentage
)
PORT MAP(
clk => clk,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 7d596e9ade..09de03e44b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -27,37 +27,36 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
--
-LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib, lofar2_ddrctrl_lib;
+LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
ENTITY ddrctrl_controller IS
GENERIC (
- g_tech_ddr : t_c_tech_ddr;
- g_stop_pos : t_c_stop_pos
+ g_tech_ddr : t_c_tech_ddr;
+ g_stop_percentage : NATURAL := 50
);
PORT (
- clk : IN STD_LOGIC;
- rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
-- ddrctrl_input
- out_of : IN NATURAL;
- out_sosi : IN t_dp_sosi;
- out_adr : IN NATURAL;
+ out_of : IN NATURAL;
+ out_sosi : IN t_dp_sosi;
+ out_adr : IN NATURAL;
-- io_ddr
- dvr_mosi : OUT t_mem_ctlr_mosi;
- wr_sosi : OUT t_dp_sosi;
- rd_siso : OUT t_dp_siso;
+ dvr_mosi : OUT t_mem_ctlr_mosi;
+ wr_sosi : OUT t_dp_sosi;
+ rd_siso : OUT t_dp_siso;
-- ddrctrl
- stop_in : IN STD_LOGIC
+ stop_in : IN STD_LOGIC
);
END ddrctrl_controller;
@@ -67,6 +66,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_bitshift_adr : NATURAL := ceil_log2(c_burstsize);
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
+ CONSTANT c_pof_ma : NATURAL := (c_max_adr*(100-g_stop_percentage))/100;
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
-- type for statemachine
@@ -75,24 +75,24 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
-- record for readability
TYPE t_reg IS RECORD
-- state of program
- state : t_state;
+ state : t_state;
-- signals
- stop_adr : NATURAL;
- stopped : STD_LOGIC;
+ stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
+ stopped : STD_LOGIC;
-- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
- rd_siso : t_dp_siso;
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
+ rd_siso : t_dp_siso;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init, c_dp_siso_rst);
+ CONSTANT c_t_reg_init : t_reg := (RESET, TO_UVEC(c_max_adr, c_adr_w), '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init, c_dp_siso_rst);
-- signals for readability
- SIGNAL d_reg : t_reg := c_t_reg_init;
- SIGNAL q_reg : t_reg := c_t_reg_init;
+ SIGNAL d_reg : t_reg := c_t_reg_init;
+ SIGNAL q_reg : t_reg := c_t_reg_init;
BEGIN
@@ -133,53 +133,39 @@ BEGIN
WHEN SET_STOP =>
- --setting a stop address dependend on the g_stop_pos
- IF g_stop_pos=START THEN
- v.stop_adr := 0;
- END IF;
-
- IF g_stop_pos=HALFWAY THEN
- IF (out_adr + (c_max_adr / 2) >= c_max_adr) THEN
- v.stop_adr := out_adr - (c_max_adr / 2);
- ELSE
- v.stop_adr := out_adr + (c_max_adr / 2);
- END IF;
- IF (stop_in = '1' AND out_adr = v.stop_adr) THEN
- --stop_out <= '1';
- v.dvr_mosi.address := TO_UVEC(out_adr, dvr_mosi.address'length);
- ELSE
- --stop_out <= '0';
- END IF;
- END IF;
-
- IF g_stop_pos=IMMIDIATE THEN
- v.stop_adr := c_max_adr;
+ --setting a stop address dependend on the g_stop_percentage
+ IF out_adr+c_pof_ma >= c_max_adr THEN
+ v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(out_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
+ ELSE
+ v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(out_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
END IF;
-
+ v.stop_adr(c_bitshift_adr-1 DOWNTO 0) := c_zeros;
-- still a write cyle
IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- adr mod 64 = 0
- v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstbegin := '1';
IF out_adr = 0 THEN
- v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
+ v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
ELSE
- v.dvr_mosi.address := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
+ v.dvr_mosi.address := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
END IF;
ELSE
- v.dvr_mosi.burstbegin := '0';
+ v.dvr_mosi.burstbegin := '0';
END IF;
- v.dvr_mosi.burstsize := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
- v.wr_sosi := out_sosi;
+ v.dvr_mosi.burstsize := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+ v.wr_sosi := out_sosi;
WHEN STOP_WRITING =>
- v.stopped := '0';
- v.wr_sosi.valid := '0';
- -- enable flush
+ v.stopped := '1';
+ v.wr_sosi.valid := '0';
+ v.dvr_mosi.flush := '1';
+ WHEN IDLE =>
+
WHEN OTHERS =>
@@ -193,6 +179,10 @@ BEGIN
v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
+ ELSIF v.stop_adr = TO_UVEC(out_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
+ v.state := STOP_WRITING;
+ ELSIF v.stopped = '1' THEN
+ v.state := IDLE;
ELSE
v.state := WRITING;
END IF;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index f16bee3854..df1980ae0a 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -22,7 +22,7 @@
-- Usage:
-- > run -a
-LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib, lofar2_ddrctrl_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
@@ -32,7 +32,6 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-USE lofar2_ddrctrl_lib.ddrctrl_pkg.ALL;
ENTITY tb_ddrctrl IS
@@ -45,7 +44,7 @@ ENTITY tb_ddrctrl IS
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
- g_stop_pos : t_c_stop_pos := HALFWAY
+ g_stop_percentage : NATURAL := 80 -- percentage there needs to be already written in the ddr memory when a stop gets triggered
);
END tb_ddrctrl;
@@ -91,6 +90,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
SIGNAL wr_not_rd : STD_LOGIC;
+ SIGNAL stop_in : STD_LOGIC := '0';
-- testbench signal
@@ -131,9 +131,29 @@ BEGIN
-- filling the input data vectors with the corresponding numbers
- make_data : FOR J IN 0 TO c_sim_length-1 LOOP
+ make_data_0 : FOR J IN 0 TO c_sim_length-1 LOOP
in_data_cnt <= in_data_cnt+1;
- fill_in_sosi_arr_rest : FOR I IN 0 TO g_nof_streams-1 LOOP
+ fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ END LOOP;
+ WAIT FOR c_clk_period*1;
+ END LOOP;
+
+ -- sending a stop signal
+ stop_in <= '1';
+
+ -- filling the input data vectors with the corresponding numbers
+ make_data_1 : FOR J IN 0 TO c_sim_length-1 LOOP
+ in_data_cnt <= in_data_cnt+1;
+ fill_in_sosi_arr_1 : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ END LOOP;
+ WAIT FOR c_clk_period*1;
+ stop_in <= '0';
+ END LOOP;
+ make_data_2 : FOR J IN 0 TO c_sim_length-1 LOOP
+ in_data_cnt <= in_data_cnt+1;
+ fill_in_sosi_arr_2 : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
END LOOP;
WAIT FOR c_clk_period*1;
@@ -141,6 +161,7 @@ BEGIN
test_running <= '0';
wr_not_rd <= '0';
+
-- stopping the testbench
WAIT FOR c_clk_period*4;
tb_end <= '1';
@@ -158,7 +179,7 @@ BEGIN
g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w,
- g_stop_pos => g_stop_pos
+ g_stop_percentage => g_stop_percentage
)
PORT MAP (
clk => clk,
@@ -167,6 +188,7 @@ BEGIN
mm_rst => mm_rst,
in_sosi_arr => in_sosi_arr,
wr_not_rd => wr_not_rd,
+ stop_in => stop_in,
--PHY
phy3_io => phy3_io,
--
GitLab