diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d8370f60f7ee79584431d22d9aa7e5f0be46dbcb
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
@@ -0,0 +1,80 @@
+hdl_lib_name = lofar2_unb2b_adc_6ch_200MHz
+hdl_library_clause_name = lofar2_unb2b_adc_6ch_200MHz_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_adc 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+                     
+ synth_files =
+    lofar2_unb2b_adc_6ch_200MHz.vhd
+
+test_bench_files = 
+    tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+
+regression_test_vhdl =
+    tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus .
+
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    lofar2_unb2b_adc_200MHz.sdc
+
+quartus_tcl_files =
+    ../../quartus/lofar2_unb2b_adc_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+
+quartus_ip_files =
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_200MHz.sdc b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_200MHz.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..465b38505311433fb219ac64c0d589af84c86db1
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_200MHz.sdc
@@ -0,0 +1,103 @@
+###############################################################################
+#
+# Copyright (C) 2018
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Constrain the input I/O path
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+# Constrain the output I/O path
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+
+
+# False path the PPS to DDIO:
+#set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
+
+
+#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
+
+#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
+
+
+
+set_time_format -unit ns -decimal_places 3
+
+create_clock -period 125Mhz [get_ports {ETH_CLK}]
+create_clock -period 200Mhz [get_ports {CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
+create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+#create_clock -period 100MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group {CLK}
+set_clock_groups -asynchronous -group {BCK_REF_CLK}
+set_clock_groups -asynchronous -group {CLK_USR}
+set_clock_groups -asynchronous -group {CLKUSR}
+set_clock_groups -asynchronous -group {SA_CLK}
+set_clock_groups -asynchronous -group {SB_CLK}
+# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
+
+# IOPLL outputs (which have global names defined in the IP qsys settings)
+set_clock_groups -asynchronous -group [get_clocks pll_clk20]
+set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
+set_clock_groups -asynchronous -group [get_clocks pll_clk125]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+
+
+# FPLL outputs
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
+
+
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
+
+#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
+
+#set_clock_groups -asynchronous \
+#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
+#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+
+
+
+# false paths added for the jesd test design
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
+set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
+set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+
+# Constraint on the SYSREF input pin
+#    Adjust this to account for any board trace difference between SYSREF and REFCLK
+# See page 150: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
+set_input_delay -clock BCK_REF_CLK 0 [get_ports JESD204B_SYSREF]
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..39c9b8843f11675c5f30618d7ef5cf8d75694c67
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -0,0 +1,165 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : J Hargreaves
+-- Purpose:  
+--   Wrapper for full adc input test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 12 ADC streams
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_adc_6ch_200MHz IS
+  GENERIC (
+    g_design_name      : STRING  := "lofar2_unb2b_adc_6ch_200MHz";
+    g_design_note      : STRING  := "Lofar2 adc with all streams";
+    g_jesd_freq        : STRING  := "200MHz";
+    g_sim              : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr       : NATURAL := 0;
+    g_sim_node_nr      : NATURAL := 0;
+    g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_revision_id      : STRING := ""   -- revision ID     -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    SENS_SC      : INOUT STD_LOGIC;
+    SENS_SD      : INOUT STD_LOGIC;
+  
+    PMBUS_SC     : INOUT STD_LOGIC;
+    PMBUS_SD     : INOUT STD_LOGIC;
+    PMBUS_ALERT  : IN    STD_LOGIC := '0';
+
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC;
+    ETH_SGIN     : IN    STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+    ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+    -- LEDs
+    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+     -- back transceivers (note only 6 are used in unb2b)
+    BCK_RX       : IN    STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1  downto c_unb2b_board_nof_tr_jesd204b);
+    BCK_REF_CLK  : IN    STD_LOGIC; -- Use as JESD204B_REFCLK
+ 
+    -- jesd204b syncronization signals (2 syncs)
+    JESD204B_SYSREF : IN    STD_LOGIC;
+    JESD204B_SYNC_N : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+  );
+END lofar2_unb2b_adc_6ch_200MHz;
+ 
+ARCHITECTURE str OF lofar2_unb2b_adc_6ch_200MHz IS
+
+  SIGNAL JESD204B_SERIAL_DATA       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL JESD204B_REFCLK            : STD_LOGIC;
+
+
+BEGIN
+
+  -- Mapping between JESD signal names and UNB2B pin/schematic names
+  JESD204B_REFCLK <=  BCK_REF_CLK;
+  JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+  JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+  JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+  JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+  JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+  JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+  JESD204B_SERIAL_DATA(6) <= '0';
+  JESD204B_SERIAL_DATA(7) <= '0';
+  JESD204B_SERIAL_DATA(8) <= '0';
+  JESD204B_SERIAL_DATA(9) <= '0';
+  JESD204B_SERIAL_DATA(10) <= '0';
+  JESD204B_SERIAL_DATA(11) <= '0';
+  JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+  u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
+  GENERIC MAP (
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_jesd_freq   => g_jesd_freq,
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time,
+    g_revision_id => g_revision_id
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => CLK,
+    PPS          => PPS,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => VERSION,
+    ID           => ID,
+    TESTIO       => TESTIO,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => SENS_SC,
+    SENS_SD      => SENS_SD,
+
+    PMBUS_SC     => PMBUS_SC,
+    PMBUS_SD     => PMBUS_SD,
+    PMBUS_ALERT  => PMBUS_ALERT,
+
+    -- 1GbE Control Interface
+    ETH_clk      => ETH_clk,
+    ETH_SGIN     => ETH_SGIN,
+    ETH_SGOUT    => ETH_SGOUT,
+
+    -- LEDs
+    QSFP_LED     => QSFP_LED,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA   => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK        => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF        => JESD204B_SYSREF,
+    JESD204B_SYNC_N        => jesd204b_sync_n_arr
+  );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0b2b380ba4c4edf1adedb8a02a0b93c884263c66
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -0,0 +1,166 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc_6ch_200MHz can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_6ch_200MHz IS
+END tb_lofar2_unb2b_adc_6ch_200MHz;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_6ch_200MHz IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL bck_rx              : STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1  downto c_unb2b_board_nof_tr_jesd204b);
+  SIGNAL bck_ref_clk         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc_6ch_200MHz : ENTITY work.lofar2_unb2b_adc_6ch_200MHz
+  GENERIC MAP (
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    BCK_RX       => bck_rx,
+    BCK_REF_CLK  => bck_ref_clk,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index b0e20abd2d6ed7ea752c3b7005a0714c7cf964d8..f1346d8a5213e5d4ff8ab8c89ccf612201d4946c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -33,7 +33,7 @@ quartus_qsf_files =
 
 # use lofar2_unb2b_adc.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
 quartus_sdc_files =
-    ../../quartus/lofar2_unb2b_adc.sdc
+    lofar2_unb2b_adc_200MHz.sdc
     #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
 
 quartus_tcl_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 502673a5db50407e0a11492f2eec4b039d9b1e99..6289c73f28f7bd582e4b3493277575dd6341fa29 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -97,8 +97,8 @@ BEGIN
 
   -- Mapping between JESD signal names and UNB2B pin/schematic names
   JESD204B_REFCLK <=  BCK_REF_CLK;
-  JESD204B_SERIAL_DATA(0) <= BCK_RX(43); --2);
-  JESD204B_SERIAL_DATA(1) <= BCK_RX(42); --3);
+  JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+  JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
   JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
   JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
   JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
@@ -110,7 +110,6 @@ BEGIN
   JESD204B_SERIAL_DATA(10) <= '0';
   JESD204B_SERIAL_DATA(11) <= '0';
   JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
-  --                              ^-- 2
 
 
   u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 892cb0c8b058a7b1ef83ad961e8e21f48193e699..8b76cf8f1a47c6fc516518773767c93bef3d3ef7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -42,6 +42,7 @@ ENTITY lofar2_unb2b_adc IS
   GENERIC (
     g_design_name      : STRING  := "lofar2_unb2b_adc";
     g_design_note      : STRING  := "UNUSED";
+    g_jesd_freq        : STRING  := "200MHz";
     g_technology       : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data     : NATURAL := 1024;
     g_sim              : BOOLEAN := FALSE; --Overridden by TB
@@ -104,14 +105,12 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
   CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
-  --CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
 
-  -- see also ~/git/hdl/libraries/base/util/src/vhdl$ vi util_heater_pkg.vhd
-  CONSTANT c_mm_jesd_ctrl_reg  : t_c_mem := (latency  => 1,
-                                   adr_w    => 1,
-                                   dat_w    => c_word_w,
-                                   nof_dat  => 1,
-                                   init_sl  => '0');
+  CONSTANT c_mm_jesd_ctrl_reg       : t_c_mem := (latency  => 1,
+                                                  adr_w    => 1,
+                                                  dat_w    => c_word_w,
+                                                  nof_dat  => 1,
+                                                  init_sl  => '0');
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
@@ -239,11 +238,11 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL alt_sosi_arr               : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);         
 
 
-  SIGNAL jesd_ctrl_mosi                : t_mem_mosi := c_mem_mosi_rst;
-  SIGNAL jesd_ctrl_miso                : t_mem_miso := c_mem_miso_rst;
+  SIGNAL jesd_ctrl_mosi             : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL jesd_ctrl_miso             : t_mem_miso := c_mem_miso_rst;
 
-  SIGNAL mm_jesd_ctrl_reg : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-  SIGNAL jesd_disable     : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
+  SIGNAL mm_jesd_ctrl_reg           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL jesd_disable               : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
 
 BEGIN
 
@@ -499,6 +498,7 @@ BEGIN
   GENERIC MAP(
     g_technology                => g_technology,
     g_nof_streams               => c_nof_streams,
+    g_jesd_freq                 => g_jesd_freq,
     g_sim                       => g_sim                
   )
   PORT MAP(
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index fc8463eea473048d1e0e849e4cf13cc592863185..f9de5b5d8be745b5a2348e4113b6f97eb8b5501b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -53,6 +53,7 @@ PACKAGE BODY lofar2_unb2b_adc_pkg IS
   BEGIN
     IF    g_design_name = "lofar2_unb2b_adc_one_node"    THEN RETURN c_one_node;
     ELSIF g_design_name = "lofar2_unb2b_adc_full"        THEN RETURN c_full;
+    ELSIF g_design_name = "lofar2_unb2b_adc_6ch_200MHz"  THEN RETURN c_full;
     ELSE  RETURN c_one_node;
     END IF;
   END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 0923e5cf2359125d265a1854992ab4ab14026e53..4b8ab7405d5547b03f612f2fe4e8e2934724f46a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -41,6 +41,7 @@ USE work.lofar2_unb2b_adc_pkg.ALL;
 ENTITY node_adc_input_and_timing IS
   GENERIC (
     g_technology              : NATURAL := c_tech_arria10_e1sg;
+    g_jesd_freq               : STRING  := "200MHz";
     g_buf_nof_data            : NATURAL := 131072; --8192; --1024;
     g_nof_streams             : NATURAL := 12;
     g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
@@ -121,7 +122,6 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
   CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
-  --CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
 
   CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
   CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
@@ -177,7 +177,8 @@ BEGIN
   GENERIC MAP(
     g_sim                => g_sim,                
     g_nof_streams        => c_nof_streams_jesd204b,
-    g_nof_sync_n         => g_nof_sync_n        
+    g_nof_sync_n         => g_nof_sync_n,
+    g_jesd_freq          => g_jesd_freq
   )
   PORT MAP(
     jesd204b_refclk      => JESD204B_REFCLK,   
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index f65bebd26358236e542192a4438a76f0cd0401a0..35a6630c98968019bd2e993aaf47081bd9c60288 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -18,16 +18,16 @@ modelsim_compile_ip_files =
 
 [quartus_project_file]
 quartus_qip_files =
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip
-    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
     $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
     $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
     $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
-    ip_arria10_e1sg_jesd204b_rx.ip
-    ip_arria10_e1sg_jesd204b_rx_core_pll.ip
+    ip_arria10_e1sg_jesd204b_rx_200MHz.ip
+    ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip
     ip_arria10_e1sg_jesd204b_rx_reset_seq.ip
     ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip
     ip_arria10_e1sg_jesd204b_tx.ip
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index a43a3f183526ba6435fd7b7bcf33edec5319d36c..56885c08586d97b1f7f4dff55ed3c1bc6a9a0a0a 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -28,7 +28,6 @@
 --   The sync_n signals are gated together to form g_nof_sync_n outputs
 --  
 
---LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
 LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
@@ -42,7 +41,8 @@ ENTITY ip_arria10_e1sg_jesd204b IS
     g_sim                 : BOOLEAN := FALSE;
     g_nof_streams         : NATURAL := 1;
     g_nof_sync_n          : NATURAL := 1;
-    g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_direction           : STRING  := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_jesd_freq           : STRING  := "200MHz"
   );
   PORT (
     -- JESD204B external signals
@@ -135,7 +135,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   -- Component declarations for the IP blocks
 
 
-    component ip_arria10_e1sg_jesd204b_rx is
+    component ip_arria10_e1sg_jesd204b_rx_200MHz is
     port (
       alldev_lane_aligned        : in  std_logic                     := 'X';             -- export
       csr_cf                     : out std_logic_vector(4 downto 0);                     -- export
@@ -184,9 +184,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       somf                       : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0);                     -- export
       sysref                     : in  std_logic                     := 'X'              -- export
     );
-  end component ip_arria10_e1sg_jesd204b_rx;
+  end component ip_arria10_e1sg_jesd204b_rx_200MHz;
 
-  component ip_arria10_e1sg_jesd204b_rx_core_pll is
+  component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz is
     port (
       locked   : out std_logic;        -- export
       outclk_0 : out std_logic;        -- clk
@@ -194,7 +194,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       refclk   : in  std_logic := 'X'; -- clk
       rst      : in  std_logic := 'X'  -- reset
     );
-  end component ip_arria10_e1sg_jesd204b_rx_core_pll;
+  end component ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz;
 
   component ip_arria10_e1sg_jesd204b_rx_reset_seq is
     port (
@@ -259,56 +259,58 @@ BEGIN
       -- The JESD204 IP (rx only)
       -----------------------------------------------------------------------------
 
-    u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx
-      PORT MAP 
-      (
-        alldev_lane_aligned        => dev_lane_aligned_arr(i),
-        csr_cf                     => OPEN,
-        csr_cs                     => OPEN,
-        csr_f                      => OPEN, 
-        csr_hd                     => OPEN,
-        csr_k                      => OPEN,
-        csr_l                      => OPEN, 
-        csr_lane_powerdown         => rx_csr_lane_powerdown_arr(i downto i), 
-        csr_m                      => OPEN, 
-        csr_n                      => OPEN, 
-        csr_np                     => OPEN, 
-        csr_rx_testmode            => OPEN, 
-        csr_s                      => OPEN, 
-        dev_lane_aligned           => dev_lane_aligned_arr(i),           
-        dev_sync_n                 => jesd204b_sync_n_internal_arr(i),
-        jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
-        jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
-        jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
-        jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
-        jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
-        jesd204_rx_avs_write              => jesd204b_mosi_arr(i).wr,
-        jesd204_rx_avs_writedata          => jesd204b_mosi_arr(i).wrdata(31 downto 0),
-        jesd204_rx_avs_clk                => jesd204b_avs_clk, --mm_clk,
-        jesd204_rx_avs_rst_n              => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
-        jesd204_rx_dlb_data               => (others => '0'), -- debug/loopback testing
-        jesd204_rx_dlb_data_valid  => (others => '0'), -- debug/loopback testing
-        jesd204_rx_dlb_disperr     => (others => '0'), -- debug/loopback testing
-        jesd204_rx_dlb_errdetect   => (others => '0'), -- debug/loopback testing
-        jesd204_rx_dlb_kchar_data  => (others => '0'), -- debug/loopback testing
-        jesd204_rx_frame_error     => '0',             -- jesd204_rx_frame_error.export
-        jesd204_rx_int             => OPEN,            -- Connected to status IO in example design 
-        jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*c_jesd204b_rx_data_w+c_jesd204b_rx_data_w-1 DOWNTO i*c_jesd204b_rx_data_w),
-        jesd204_rx_link_valid             => jesd204b_rx_link_valid_arr(i),
-        jesd204_rx_link_ready             => '1',
-        pll_ref_clk                => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) 
-        rx_analogreset             => rx_analogreset_arr(I DOWNTO I),
-        rx_cal_busy                => rx_cal_busy_arr(I DOWNTO I),
-        rx_digitalreset            => rx_digitalreset_arr(I DOWNTO I),
-        rx_islockedtodata          => rx_islockedtodata_arr(I DOWNTO I),
-        rx_serial_data             => serial_rx_arr(i downto i),
-        rxlink_clk                 => rxlink_clk,             -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
-        rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
-        rxphy_clk                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
-        sof                        => OPEN,
-        somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
-        sysref                     => jesd204b_sysref_2
-      );
+    gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+      u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
+        PORT MAP 
+        (
+          alldev_lane_aligned        => dev_lane_aligned_arr(i),
+          csr_cf                     => OPEN,
+          csr_cs                     => OPEN,
+          csr_f                      => OPEN, 
+          csr_hd                     => OPEN,
+          csr_k                      => OPEN,
+          csr_l                      => OPEN, 
+          csr_lane_powerdown         => rx_csr_lane_powerdown_arr(i downto i), 
+          csr_m                      => OPEN, 
+          csr_n                      => OPEN, 
+          csr_np                     => OPEN, 
+          csr_rx_testmode            => OPEN, 
+          csr_s                      => OPEN, 
+          dev_lane_aligned           => dev_lane_aligned_arr(i),           
+          dev_sync_n                 => jesd204b_sync_n_internal_arr(i),
+          jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
+          jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
+          jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
+          jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
+          jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
+          jesd204_rx_avs_write              => jesd204b_mosi_arr(i).wr,
+          jesd204_rx_avs_writedata          => jesd204b_mosi_arr(i).wrdata(31 downto 0),
+          jesd204_rx_avs_clk                => jesd204b_avs_clk, --mm_clk,
+          jesd204_rx_avs_rst_n              => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
+          jesd204_rx_dlb_data               => (others => '0'), -- debug/loopback testing
+          jesd204_rx_dlb_data_valid  => (others => '0'), -- debug/loopback testing
+          jesd204_rx_dlb_disperr     => (others => '0'), -- debug/loopback testing
+          jesd204_rx_dlb_errdetect   => (others => '0'), -- debug/loopback testing
+          jesd204_rx_dlb_kchar_data  => (others => '0'), -- debug/loopback testing
+          jesd204_rx_frame_error     => '0',             -- jesd204_rx_frame_error.export
+          jesd204_rx_int             => OPEN,            -- Connected to status IO in example design 
+          jesd204_rx_link_data              => jesd204b_rx_link_data_arr(i*c_jesd204b_rx_data_w+c_jesd204b_rx_data_w-1 DOWNTO i*c_jesd204b_rx_data_w),
+          jesd204_rx_link_valid             => jesd204b_rx_link_valid_arr(i),
+          jesd204_rx_link_ready             => '1',
+          pll_ref_clk                => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63) 
+          rx_analogreset             => rx_analogreset_arr(I DOWNTO I),
+          rx_cal_busy                => rx_cal_busy_arr(I DOWNTO I),
+          rx_digitalreset            => rx_digitalreset_arr(I DOWNTO I),
+          rx_islockedtodata          => rx_islockedtodata_arr(I DOWNTO I),
+          rx_serial_data             => serial_rx_arr(i downto i),
+          rxlink_clk                 => rxlink_clk,             -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
+          rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
+          rxphy_clk                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+          sof                        => OPEN,
+          somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
+          sysref                     => jesd204b_sysref_2
+        );
+      END GENERATE;
 
       -----------------------------------------------------------------------------
       -- Reset sequencer for each channel
@@ -420,39 +422,18 @@ BEGIN
       END IF;
     END PROCESS;
 
-    -- old:
-    --p_rx_sysref : PROCESS (rxframe_clk, core_pll_locked)
-    --BEGIN
-    --  IF core_pll_locked = '0' THEN
-    --    jesd204b_sysref_frameclk_1 <= '0';
-    --    jesd204b_sysref_frameclk_2 <= '0';
-    --    rx_sysref <= '0';
-    --  ELSE
-    --    IF rising_edge(rxframe_clk) THEN
-    --      jesd204b_sysref_frameclk_1 <= jesd204b_sysref;
-    --      jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
-    --      IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
-    --        rx_sysref <= '1';
-    --      ELSE
-    --        rx_sysref <= '0';
-    --      END IF;
-    --    END IF;
-    --  END IF;
-    --END PROCESS;
-
-
-
-
   
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
-    u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll
-    PORT MAP (
-      locked                      => core_pll_locked,
-      outclk_0                    => rxlink_clk,
-      outclk_1                    => rxframe_clk,
-      refclk                      => jesd204b_refclk,
-      rst                         => pll_reset_arr(0)
-    );
+    gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+      u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz : ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz
+      PORT MAP (
+        locked                      => core_pll_locked,
+        outclk_0                    => rxlink_clk,
+        outclk_1                    => rxframe_clk,
+        refclk                      => jesd204b_refclk,
+        rst                         => pll_reset_arr(0)
+      );
+    END GENERATE;
 
     p_pll_locked_reg : PROCESS (mm_rst_internal, mm_clk)
     BEGIN
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.ip b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.ip
similarity index 99%
rename from libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.ip
rename to libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.ip
index 2c690f6819c8f2ce0a47d072c5cdb67107408daf..02bb23216d2903b6d91eb451973df594b7f0f8fd 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.ip
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.ip
@@ -2834,7 +2834,7 @@
         <ipxact:parameter parameterId="REFCLK_FREQ" type="real">
           <ipxact:name>REFCLK_FREQ</ipxact:name>
           <ipxact:displayName>PLL/CDR Reference Clock Frequency</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_analog_voltage" type="string">
           <ipxact:name>gui_analog_voltage</ipxact:name>
@@ -3074,7 +3074,7 @@
         <ipxact:parameter parameterId="d_refclk_freq" type="real">
           <ipxact:name>d_refclk_freq</ipxact:name>
           <ipxact:displayName>PLL/CDR Reference Clock Frequency</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="JESDV" type="int">
           <ipxact:name>JESDV</ipxact:name>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.qsys b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.qsys
similarity index 99%
rename from libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.qsys
rename to libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.qsys
index 22e511f4094b29da3cc5f459294b1d06d6d7bc59..c4ed31506907439a2e3c34051e354636b59c4eca 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx.qsys
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_200MHz.qsys
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<system name="ip_arria10_e1sg_jesd204b_rx">
+<system name="ip_arria10_e1sg_jesd204b_rx_200MHz">
  <component
    name="$${FILENAME}"
    displayName="$${FILENAME}"
@@ -1942,13 +1942,13 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>alldev_lane_aligned</name>
-            <type>conduit</type>
+            <name>rxlink_clk</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>alldev_lane_aligned</name>
-                    <role>export</role>
+                    <name>rxlink_clk</name>
+                    <role>clk</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
@@ -1956,371 +1956,470 @@
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_cf</name>
-            <type>conduit</type>
+            <name>rxlink_rst_n</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_cf</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>5</width>
+                    <name>rxlink_rst_n_reset_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>rxlink_clk</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_cs</name>
-            <type>conduit</type>
+            <name>jesd204_rx_avs_clk</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_cs</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>2</width>
+                    <name>jesd204_rx_avs_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_f</name>
-            <type>conduit</type>
+            <name>jesd204_rx_avs_rst_n</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_f</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>8</width>
+                    <name>jesd204_rx_avs_rst_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_hd</name>
-            <type>conduit</type>
+            <name>jesd204_rx_avs</name>
+            <type>avalon</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_hd</name>
-                    <role>export</role>
+                    <name>jesd204_rx_avs_chipselect</name>
+                    <role>chipselect</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_avs_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>8</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_avs_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_avs_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_avs_waitrequest</name>
+                    <role>waitrequest</role>
                     <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
+                <port>
+                    <name>jesd204_rx_avs_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_avs_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
             </ports>
             <assignments>
                 <assignmentValueMap>
                     <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>1024</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
                     <entry>
                         <key>associatedClock</key>
+                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
+                        <value>jesd204_rx_avs_rst_n</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
                         <value>false</value>
                     </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>csr_k</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csr_k</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>5</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
                     <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
                     </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
                         <value>false</value>
                     </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>csr_l</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csr_l</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>5</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
                     <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <key>isBigEndian</key>
+                        <value>false</value>
                     </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>isFlash</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
+                        <key>isNonVolatileStorage</key>
                         <value>false</value>
                     </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>csr_lane_powerdown</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csr_lane_powerdown</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
                     <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
                     </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
                     </entry>
                     <entry>
                         <key>prSafe</key>
                         <value>false</value>
                     </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>csr_m</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>csr_m</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>8</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
                     <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <key>printableDevice</key>
+                        <value>false</value>
                     </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>readLatency</key>
+                        <value>1</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>readWaitStates</key>
+                        <value>1</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
                         <value>false</value>
                     </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_n</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
+            <name>jesd204_rx_link</name>
+            <type>avalon_streaming</type>
+            <isStart>true</isStart>
             <ports>
                 <port>
-                    <name>csr_n</name>
-                    <role>export</role>
+                    <name>jesd204_rx_link_data</name>
+                    <role>data</role>
                     <direction>Output</direction>
-                    <width>5</width>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
+                <port>
+                    <name>jesd204_rx_link_valid</name>
+                    <role>valid</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>jesd204_rx_link_ready</name>
+                    <role>ready</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>rxlink_clk</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
+                        <value>rxlink_rst_n</value>
+                    </entry>
+                    <entry>
+                        <key>beatsPerCycle</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>dataBitsPerSymbol</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>emptyWithinPacket</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>errorDescriptor</key>
+                    </entry>
+                    <entry>
+                        <key>firstSymbolInHighOrderBits</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>highOrderSymbolAtMSB</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maxChannel</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>packetDescription</key>
+                        <value></value>
                     </entry>
                     <entry>
                         <key>prSafe</key>
                         <value>false</value>
                     </entry>
+                    <entry>
+                        <key>readyAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readyLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>symbolsPerBeat</key>
+                        <value>1</value>
+                    </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>csr_np</name>
+            <name>sof</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_np</name>
+                    <name>sof</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>5</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2349,12 +2448,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>csr_rx_testmode</name>
+            <name>somf</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_rx_testmode</name>
+                    <name>somf</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>4</width>
@@ -2386,24 +2485,24 @@
             </parameters>
         </interface>
         <interface>
-            <name>csr_s</name>
+            <name>alldev_lane_aligned</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csr_s</name>
+                    <name>alldev_lane_aligned</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>5</width>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <value>input</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2497,328 +2596,245 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_avs</name>
-            <type>avalon</type>
+            <name>sysref</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_avs_chipselect</name>
-                    <role>chipselect</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_avs_address</name>
-                    <role>address</role>
-                    <direction>Input</direction>
-                    <width>8</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_avs_read</name>
-                    <role>read</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_avs_readdata</name>
-                    <role>readdata</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_avs_waitrequest</name>
-                    <role>waitrequest</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_avs_write</name>
-                    <role>write</role>
+                    <name>sysref</name>
+                    <role>export</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
-                <port>
-                    <name>jesd204_rx_avs_writedata</name>
-                    <role>writedata</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
             </ports>
             <assignments>
                 <assignmentValueMap>
                     <entry>
-                        <key>embeddedsw.configuration.isFlash</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>0</value>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>input</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
-                    <entry>
-                        <key>addressAlignment</key>
-                        <value>DYNAMIC</value>
-                    </entry>
-                    <entry>
-                        <key>addressGroup</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>addressSpan</key>
-                        <value>1024</value>
-                    </entry>
-                    <entry>
-                        <key>addressUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>alwaysBurstMaxBurst</key>
-                        <value>false</value>
-                    </entry>
                     <entry>
                         <key>associatedClock</key>
-                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
-                        <value>jesd204_rx_avs_rst_n</value>
-                    </entry>
-                    <entry>
-                        <key>bitsPerSymbol</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>bridgedAddressOffset</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>bridgesToMaster</key>
-                    </entry>
-                    <entry>
-                        <key>burstOnBurstBoundariesOnly</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>burstcountUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>constantBurstBehavior</key>
-                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>explicitAddressSpan</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>holdTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>interleaveBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isFlash</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isMemoryDevice</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isNonVolatileStorage</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>linewrapBursts</key>
+                        <key>prSafe</key>
                         <value>false</value>
                     </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>jesd204_rx_int</name>
+            <type>interrupt</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>jesd204_rx_int</name>
+                    <role>irq</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
                     <entry>
-                        <key>maximumPendingReadTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingWriteTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>minimumReadLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumResponseLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumUninterruptedRunLength</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>associatedAddressablePoint</key>
+                        <value>jesd204_0.jesd204_rx_avs</value>
                     </entry>
                     <entry>
-                        <key>printableDevice</key>
-                        <value>false</value>
+                        <key>associatedClock</key>
+                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
-                        <key>readLatency</key>
-                        <value>1</value>
+                        <key>associatedReset</key>
+                        <value>jesd204_rx_avs_rst_n</value>
                     </entry>
                     <entry>
-                        <key>readWaitStates</key>
-                        <value>1</value>
+                        <key>bridgedReceiverOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>readWaitTime</key>
-                        <value>1</value>
+                        <key>bridgesToReceiver</key>
                     </entry>
                     <entry>
-                        <key>registerIncomingSignals</key>
-                        <value>false</value>
+                        <key>irqScheme</key>
+                        <value>NONE</value>
                     </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>csr_rx_testmode</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csr_rx_testmode</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
                     <entry>
-                        <key>registerOutgoingSignals</key>
-                        <value>false</value>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
                     </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
                     <entry>
-                        <key>setupTime</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>timingUnits</key>
-                        <value>Cycles</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>transparentBridge</key>
+                        <key>prSafe</key>
                         <value>false</value>
                     </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>csr_f</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csr_f</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>8</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
                     <entry>
-                        <key>waitrequestAllowance</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>wellBehavedWaitrequest</key>
-                        <value>false</value>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
                     </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
                     <entry>
-                        <key>writeLatency</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>writeWaitStates</key>
-                        <value>0</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>writeWaitTime</key>
-                        <value>0</value>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_avs_clk</name>
-            <type>clock</type>
+            <name>csr_k</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_avs_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>csr_k</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_avs_rst_n</name>
-            <type>reset</type>
+            <name>csr_l</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_avs_rst_n</name>
-                    <role>reset_n</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>csr_l</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_dlb_data</name>
+            <name>csr_m</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_dlb_data</name>
+                    <name>csr_m</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
+                    <direction>Output</direction>
+                    <width>8</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2827,7 +2843,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2847,15 +2863,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_dlb_data_valid</name>
+            <name>csr_n</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_dlb_data_valid</name>
+                    <name>csr_n</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2864,7 +2880,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2884,15 +2900,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_dlb_disperr</name>
+            <name>csr_s</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_dlb_disperr</name>
+                    <name>csr_s</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>4</width>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2901,7 +2917,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2921,15 +2937,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_dlb_errdetect</name>
+            <name>csr_cf</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_dlb_errdetect</name>
+                    <name>csr_cf</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>4</width>
+                    <direction>Output</direction>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2938,7 +2954,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2958,15 +2974,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_dlb_kchar_data</name>
+            <name>csr_cs</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_dlb_kchar_data</name>
+                    <name>csr_cs</name>
                     <role>export</role>
-                    <direction>Input</direction>
-                    <width>4</width>
+                    <direction>Output</direction>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -2975,7 +2991,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -2995,14 +3011,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_frame_error</name>
+            <name>csr_hd</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_frame_error</name>
+                    <name>csr_hd</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -3012,7 +3028,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
+                        <value>output</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -3032,151 +3048,87 @@
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_int</name>
-            <type>interrupt</type>
+            <name>csr_np</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_int</name>
-                    <role>irq</role>
+                    <name>csr_np</name>
+                    <role>export</role>
                     <direction>Output</direction>
-                    <width>1</width>
+                    <width>5</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
-                    <entry>
-                        <key>associatedAddressablePoint</key>
-                        <value>jesd204_0.jesd204_rx_avs</value>
-                    </entry>
                     <entry>
                         <key>associatedClock</key>
-                        <value>jesd204_rx_avs_clk</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
-                        <value>jesd204_rx_avs_rst_n</value>
-                    </entry>
-                    <entry>
-                        <key>bridgedReceiverOffset</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>bridgesToReceiver</key>
                     </entry>
                     <entry>
-                        <key>irqScheme</key>
-                        <value>NONE</value>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>jesd204_rx_link</name>
-            <type>avalon_streaming</type>
-            <isStart>true</isStart>
+            <name>csr_lane_powerdown</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>jesd204_rx_link_data</name>
-                    <role>data</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_link_valid</name>
-                    <role>valid</role>
+                    <name>csr_lane_powerdown</name>
+                    <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>jesd204_rx_link_ready</name>
-                    <role>ready</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>rxlink_clk</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
-                        <value>rxlink_rst_n</value>
-                    </entry>
-                    <entry>
-                        <key>beatsPerCycle</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>dataBitsPerSymbol</key>
-                        <value>32</value>
-                    </entry>
-                    <entry>
-                        <key>emptyWithinPacket</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>errorDescriptor</key>
-                    </entry>
-                    <entry>
-                        <key>firstSymbolInHighOrderBits</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>highOrderSymbolAtMSB</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>maxChannel</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>packetDescription</key>
-                        <value></value>
                     </entry>
                     <entry>
                         <key>prSafe</key>
                         <value>false</value>
                     </entry>
-                    <entry>
-                        <key>readyAllowance</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>readyLatency</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>symbolsPerBeat</key>
-                        <value>1</value>
-                    </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>pll_ref_clk</name>
-            <type>clock</type>
+            <name>jesd204_rx_frame_error</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>pll_ref_clk</name>
-                    <role>clk</role>
+                    <name>jesd204_rx_frame_error</name>
+                    <role>export</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
@@ -3184,34 +3136,38 @@
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>input</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>rx_analogreset</name>
+            <name>jesd204_rx_dlb_data</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rx_analogreset</name>
-                    <role>rx_analogreset</role>
+                    <name>jesd204_rx_dlb_data</name>
+                    <role>export</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3240,14 +3196,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>rx_cal_busy</name>
+            <name>jesd204_rx_dlb_data_valid</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rx_cal_busy</name>
-                    <role>rx_cal_busy</role>
-                    <direction>Output</direction>
+                    <name>jesd204_rx_dlb_data_valid</name>
+                    <role>export</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -3257,7 +3213,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <value>input</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -3277,15 +3233,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>rx_digitalreset</name>
+            <name>jesd204_rx_dlb_kchar_data</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rx_digitalreset</name>
-                    <role>rx_digitalreset</role>
+                    <name>jesd204_rx_dlb_kchar_data</name>
+                    <role>export</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3314,15 +3270,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>rx_islockedtodata</name>
+            <name>jesd204_rx_dlb_errdetect</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rx_islockedtodata</name>
-                    <role>rx_is_lockedtodata</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <name>jesd204_rx_dlb_errdetect</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3331,7 +3287,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <value>input</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -3351,15 +3307,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>rx_serial_data</name>
+            <name>jesd204_rx_dlb_disperr</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rx_serial_data</name>
-                    <role>rx_serial_data</role>
+                    <name>jesd204_rx_dlb_disperr</name>
+                    <role>export</role>
                     <direction>Input</direction>
-                    <width>1</width>
+                    <width>4</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3388,12 +3344,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>rxlink_clk</name>
+            <name>pll_ref_clk</name>
             <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rxlink_clk</name>
+                    <name>pll_ref_clk</name>
                     <role>clk</role>
                     <direction>Input</direction>
                     <width>1</width>
@@ -3421,43 +3377,50 @@
             </parameters>
         </interface>
         <interface>
-            <name>rxlink_rst_n</name>
-            <type>reset</type>
+            <name>rxphy_clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rxlink_rst_n_reset_n</name>
-                    <role>reset_n</role>
-                    <direction>Input</direction>
+                    <name>rxphy_clk</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap/>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>output</value>
+                    </entry>
+                </assignmentValueMap>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>rxlink_clk</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>rxphy_clk</name>
+            <name>rx_islockedtodata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>rxphy_clk</name>
-                    <role>export</role>
+                    <name>rx_islockedtodata</name>
+                    <role>rx_is_lockedtodata</role>
                     <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
@@ -3488,15 +3451,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>sof</name>
+            <name>rx_cal_busy</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>sof</name>
-                    <role>export</role>
+                    <name>rx_cal_busy</name>
+                    <role>rx_cal_busy</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3525,15 +3488,15 @@
             </parameters>
         </interface>
         <interface>
-            <name>somf</name>
+            <name>rx_analogreset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>somf</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>4</width>
+                    <name>rx_analogreset</name>
+                    <role>rx_analogreset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -3542,7 +3505,7 @@
                 <assignmentValueMap>
                     <entry>
                         <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
+                        <value>input</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -3562,17 +3525,54 @@
             </parameters>
         </interface>
         <interface>
-            <name>sysref</name>
+            <name>rx_digitalreset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>sysref</name>
-                    <role>export</role>
+                    <name>rx_digitalreset</name>
+                    <role>rx_digitalreset</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>ui.blockdiagram.direction</key>
+                        <value>input</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>rx_serial_data</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>rx_serial_data</name>
+                    <role>rx_serial_data</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -3601,30 +3601,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>ip_arria10_e1sg_jesd204b_rx</hdlLibraryName>
+    <hdlLibraryName>ip_arria10_e1sg_jesd204b_rx_200MHz</hdlLibraryName>
     <fileSets>
         <fileSet>
             <fileSetName>ip_arria10_e1sg_jesd204b_rx</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx</fileSetFixedName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_200MHz</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
             <fileSetName>ip_arria10_e1sg_jesd204b_rx</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx</fileSetFixedName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_200MHz</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
             <fileSetName>ip_arria10_e1sg_jesd204b_rx</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx</fileSetFixedName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_200MHz</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip_arria10_e1sg_jesd204b_rx.ip</parameter>
+  <parameter name="logicalView">ip_arria10_e1sg_jesd204b_rx_200MHz.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo
deleted file mode 100644
index d4ee2071a4b3a49f0e2fc76198d6de5fe84d8058..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo
+++ /dev/null
@@ -1,183 +0,0 @@
-`timescale 1ns/10ps
-module  ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama(
-
-	// interface 'reset'
-	input wire rst,
-
-	// interface 'refclk'
-	input wire refclk,
-
-	// interface 'locked'
-	output wire locked,
-
-	// interface 'outclk0'
-	output wire outclk_0,
-
-	// interface 'outclk1'
-	output wire outclk_1
-);
-
-    wire [6:0] unused_wires;
-
-	altera_iopll #(
-		.c_cnt_bypass_en0("false"),
-		.c_cnt_bypass_en1("false"),
-		.c_cnt_bypass_en2("true"),
-		.c_cnt_bypass_en3("true"),
-		.c_cnt_bypass_en4("true"),
-		.c_cnt_bypass_en5("true"),
-		.c_cnt_bypass_en6("true"),
-		.c_cnt_bypass_en7("true"),
-		.c_cnt_bypass_en8("true"),
-		.c_cnt_hi_div0(4),
-		.c_cnt_hi_div1(2),
-		.c_cnt_hi_div2(256),
-		.c_cnt_hi_div3(256),
-		.c_cnt_hi_div4(256),
-		.c_cnt_hi_div5(256),
-		.c_cnt_hi_div6(256),
-		.c_cnt_hi_div7(256),
-		.c_cnt_hi_div8(256),
-		.c_cnt_in_src0("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src1("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src2("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src3("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src4("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src5("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src6("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src7("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src8("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_lo_div0(4),
-		.c_cnt_lo_div1(2),
-		.c_cnt_lo_div2(256),
-		.c_cnt_lo_div3(256),
-		.c_cnt_lo_div4(256),
-		.c_cnt_lo_div5(256),
-		.c_cnt_lo_div6(256),
-		.c_cnt_lo_div7(256),
-		.c_cnt_lo_div8(256),
-		.c_cnt_odd_div_duty_en0("false"),
-		.c_cnt_odd_div_duty_en1("false"),
-		.c_cnt_odd_div_duty_en2("false"),
-		.c_cnt_odd_div_duty_en3("false"),
-		.c_cnt_odd_div_duty_en4("false"),
-		.c_cnt_odd_div_duty_en5("false"),
-		.c_cnt_odd_div_duty_en6("false"),
-		.c_cnt_odd_div_duty_en7("false"),
-		.c_cnt_odd_div_duty_en8("false"),
-		.c_cnt_ph_mux_prst0(0),
-		.c_cnt_ph_mux_prst1(0),
-		.c_cnt_ph_mux_prst2(0),
-		.c_cnt_ph_mux_prst3(0),
-		.c_cnt_ph_mux_prst4(0),
-		.c_cnt_ph_mux_prst5(0),
-		.c_cnt_ph_mux_prst6(0),
-		.c_cnt_ph_mux_prst7(0),
-		.c_cnt_ph_mux_prst8(0),
-		.c_cnt_prst0(1),
-		.c_cnt_prst1(1),
-		.c_cnt_prst2(1),
-		.c_cnt_prst3(1),
-		.c_cnt_prst4(1),
-		.c_cnt_prst5(1),
-		.c_cnt_prst6(1),
-		.c_cnt_prst7(1),
-		.c_cnt_prst8(1),
-		.clock_name_0("link_clk"),
-		.clock_name_1("frame_clk"),
-		.clock_name_2(""),
-		.clock_name_3(""),
-		.clock_name_4(""),
-		.clock_name_5(""),
-		.clock_name_6(""),
-		.clock_name_7(""),
-		.clock_name_8(""),
-		.clock_name_global_0("false"),
-		.clock_name_global_1("false"),
-		.clock_name_global_2("false"),
-		.clock_name_global_3("false"),
-		.clock_name_global_4("false"),
-		.clock_name_global_5("false"),
-		.clock_name_global_6("false"),
-		.clock_name_global_7("false"),
-		.clock_name_global_8("false"),
-		.duty_cycle0(50),
-		.duty_cycle1(50),
-		.duty_cycle2(50),
-		.duty_cycle3(50),
-		.duty_cycle4(50),
-		.duty_cycle5(50),
-		.duty_cycle6(50),
-		.duty_cycle7(50),
-		.duty_cycle8(50),
-		.m_cnt_bypass_en("false"),
-		.m_cnt_hi_div(2),
-		.m_cnt_lo_div(2),
-		.m_cnt_odd_div_duty_en("false"),
-		.n_cnt_bypass_en("true"),
-		.n_cnt_hi_div(256),
-		.n_cnt_lo_div(256),
-		.n_cnt_odd_div_duty_en("false"),
-		.number_of_clocks(2),
-		.operation_mode("source_synchronous"),
-		.output_clock_frequency0("100.000000 MHz"),
-		.output_clock_frequency1("200.000000 MHz"),
-		.output_clock_frequency2("0 ps"),
-		.output_clock_frequency3("0 ps"),
-		.output_clock_frequency4("0 ps"),
-		.output_clock_frequency5("0 ps"),
-		.output_clock_frequency6("0 ps"),
-		.output_clock_frequency7("0 ps"),
-		.output_clock_frequency8("0 ps"),
-		.phase_shift0("0 ps"),
-		.phase_shift1("0 ps"),
-		.phase_shift2("0 ps"),
-		.phase_shift3("0 ps"),
-		.phase_shift4("0 ps"),
-		.phase_shift5("0 ps"),
-		.phase_shift6("0 ps"),
-		.phase_shift7("0 ps"),
-		.phase_shift8("0 ps"),
-		.pll_bw_sel("Low"),
-		.pll_bwctrl("pll_bw_res_setting2"),
-		.pll_cp_current("pll_cp_setting10"),
-		.pll_extclk_0_cnt_src("pll_extclk_cnt_src_vss"),
-		.pll_extclk_1_cnt_src("pll_extclk_cnt_src_vss"),
-		.pll_fbclk_mux_1("pll_fbclk_mux_1_glb"),
-		.pll_fbclk_mux_2("pll_fbclk_mux_2_fb_1"),
-		.pll_m_cnt_in_src("c_m_cnt_in_src_ph_mux_clk"),
-		.pll_output_clk_frequency("800.0 MHz"),
-		.pll_slf_rst("false"),
-		.pll_subtype("General"),
-		.pll_type("Arria 10"),
-		.prot_mode("BASIC"),
-		.reference_clock_frequency("200.0 MHz")
-	) altera_iopll_i (
-		.refclk1	(1'b0),
-		.rst	(rst),
-		.fbclk	(1'b0),
-		.fboutclk	( ),
-		.zdbfbclk	( ),
-		.locked	(locked),
-		.loaden	( ),
-		.phase_done	( ),
-		.reconfig_to_pll	(64'b0),
-		.refclk	(refclk),
-		.scanclk	(1'b0),
-		.phout	( ),
-		.num_phase_shifts	(3'b0),
-		.cntsel	(5'b0),
-		.clkbad	( ),
-		.extclk_out	( ),
-		.lvds_clk	( ),
-		.outclk	({outclk_1, outclk_0}),
-		.phase_en	(1'b0),
-		.extswitch	(1'b0),
-		.cascade_out	( ),
-		.activeclk	( ),
-		.adjpllin	(1'b0),
-		.updn	(1'b0),
-		.reconfig_from_pll	( )
-	);
-endmodule
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/synth/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.v b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/synth/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.v
deleted file mode 100644
index d4ee2071a4b3a49f0e2fc76198d6de5fe84d8058..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/altera_iopll_180/synth/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.v
+++ /dev/null
@@ -1,183 +0,0 @@
-`timescale 1ns/10ps
-module  ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama(
-
-	// interface 'reset'
-	input wire rst,
-
-	// interface 'refclk'
-	input wire refclk,
-
-	// interface 'locked'
-	output wire locked,
-
-	// interface 'outclk0'
-	output wire outclk_0,
-
-	// interface 'outclk1'
-	output wire outclk_1
-);
-
-    wire [6:0] unused_wires;
-
-	altera_iopll #(
-		.c_cnt_bypass_en0("false"),
-		.c_cnt_bypass_en1("false"),
-		.c_cnt_bypass_en2("true"),
-		.c_cnt_bypass_en3("true"),
-		.c_cnt_bypass_en4("true"),
-		.c_cnt_bypass_en5("true"),
-		.c_cnt_bypass_en6("true"),
-		.c_cnt_bypass_en7("true"),
-		.c_cnt_bypass_en8("true"),
-		.c_cnt_hi_div0(4),
-		.c_cnt_hi_div1(2),
-		.c_cnt_hi_div2(256),
-		.c_cnt_hi_div3(256),
-		.c_cnt_hi_div4(256),
-		.c_cnt_hi_div5(256),
-		.c_cnt_hi_div6(256),
-		.c_cnt_hi_div7(256),
-		.c_cnt_hi_div8(256),
-		.c_cnt_in_src0("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src1("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src2("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src3("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src4("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src5("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src6("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src7("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_in_src8("c_m_cnt_in_src_ph_mux_clk"),
-		.c_cnt_lo_div0(4),
-		.c_cnt_lo_div1(2),
-		.c_cnt_lo_div2(256),
-		.c_cnt_lo_div3(256),
-		.c_cnt_lo_div4(256),
-		.c_cnt_lo_div5(256),
-		.c_cnt_lo_div6(256),
-		.c_cnt_lo_div7(256),
-		.c_cnt_lo_div8(256),
-		.c_cnt_odd_div_duty_en0("false"),
-		.c_cnt_odd_div_duty_en1("false"),
-		.c_cnt_odd_div_duty_en2("false"),
-		.c_cnt_odd_div_duty_en3("false"),
-		.c_cnt_odd_div_duty_en4("false"),
-		.c_cnt_odd_div_duty_en5("false"),
-		.c_cnt_odd_div_duty_en6("false"),
-		.c_cnt_odd_div_duty_en7("false"),
-		.c_cnt_odd_div_duty_en8("false"),
-		.c_cnt_ph_mux_prst0(0),
-		.c_cnt_ph_mux_prst1(0),
-		.c_cnt_ph_mux_prst2(0),
-		.c_cnt_ph_mux_prst3(0),
-		.c_cnt_ph_mux_prst4(0),
-		.c_cnt_ph_mux_prst5(0),
-		.c_cnt_ph_mux_prst6(0),
-		.c_cnt_ph_mux_prst7(0),
-		.c_cnt_ph_mux_prst8(0),
-		.c_cnt_prst0(1),
-		.c_cnt_prst1(1),
-		.c_cnt_prst2(1),
-		.c_cnt_prst3(1),
-		.c_cnt_prst4(1),
-		.c_cnt_prst5(1),
-		.c_cnt_prst6(1),
-		.c_cnt_prst7(1),
-		.c_cnt_prst8(1),
-		.clock_name_0("link_clk"),
-		.clock_name_1("frame_clk"),
-		.clock_name_2(""),
-		.clock_name_3(""),
-		.clock_name_4(""),
-		.clock_name_5(""),
-		.clock_name_6(""),
-		.clock_name_7(""),
-		.clock_name_8(""),
-		.clock_name_global_0("false"),
-		.clock_name_global_1("false"),
-		.clock_name_global_2("false"),
-		.clock_name_global_3("false"),
-		.clock_name_global_4("false"),
-		.clock_name_global_5("false"),
-		.clock_name_global_6("false"),
-		.clock_name_global_7("false"),
-		.clock_name_global_8("false"),
-		.duty_cycle0(50),
-		.duty_cycle1(50),
-		.duty_cycle2(50),
-		.duty_cycle3(50),
-		.duty_cycle4(50),
-		.duty_cycle5(50),
-		.duty_cycle6(50),
-		.duty_cycle7(50),
-		.duty_cycle8(50),
-		.m_cnt_bypass_en("false"),
-		.m_cnt_hi_div(2),
-		.m_cnt_lo_div(2),
-		.m_cnt_odd_div_duty_en("false"),
-		.n_cnt_bypass_en("true"),
-		.n_cnt_hi_div(256),
-		.n_cnt_lo_div(256),
-		.n_cnt_odd_div_duty_en("false"),
-		.number_of_clocks(2),
-		.operation_mode("source_synchronous"),
-		.output_clock_frequency0("100.000000 MHz"),
-		.output_clock_frequency1("200.000000 MHz"),
-		.output_clock_frequency2("0 ps"),
-		.output_clock_frequency3("0 ps"),
-		.output_clock_frequency4("0 ps"),
-		.output_clock_frequency5("0 ps"),
-		.output_clock_frequency6("0 ps"),
-		.output_clock_frequency7("0 ps"),
-		.output_clock_frequency8("0 ps"),
-		.phase_shift0("0 ps"),
-		.phase_shift1("0 ps"),
-		.phase_shift2("0 ps"),
-		.phase_shift3("0 ps"),
-		.phase_shift4("0 ps"),
-		.phase_shift5("0 ps"),
-		.phase_shift6("0 ps"),
-		.phase_shift7("0 ps"),
-		.phase_shift8("0 ps"),
-		.pll_bw_sel("Low"),
-		.pll_bwctrl("pll_bw_res_setting2"),
-		.pll_cp_current("pll_cp_setting10"),
-		.pll_extclk_0_cnt_src("pll_extclk_cnt_src_vss"),
-		.pll_extclk_1_cnt_src("pll_extclk_cnt_src_vss"),
-		.pll_fbclk_mux_1("pll_fbclk_mux_1_glb"),
-		.pll_fbclk_mux_2("pll_fbclk_mux_2_fb_1"),
-		.pll_m_cnt_in_src("c_m_cnt_in_src_ph_mux_clk"),
-		.pll_output_clk_frequency("800.0 MHz"),
-		.pll_slf_rst("false"),
-		.pll_subtype("General"),
-		.pll_type("Arria 10"),
-		.prot_mode("BASIC"),
-		.reference_clock_frequency("200.0 MHz")
-	) altera_iopll_i (
-		.refclk1	(1'b0),
-		.rst	(rst),
-		.fbclk	(1'b0),
-		.fboutclk	( ),
-		.zdbfbclk	( ),
-		.locked	(locked),
-		.loaden	( ),
-		.phase_done	( ),
-		.reconfig_to_pll	(64'b0),
-		.refclk	(refclk),
-		.scanclk	(1'b0),
-		.phout	( ),
-		.num_phase_shifts	(3'b0),
-		.cntsel	(5'b0),
-		.clkbad	( ),
-		.extclk_out	( ),
-		.lvds_clk	( ),
-		.outclk	({outclk_1, outclk_0}),
-		.phase_en	(1'b0),
-		.extswitch	(1'b0),
-		.cascade_out	( ),
-		.activeclk	( ),
-		.adjpllin	(1'b0),
-		.updn	(1'b0),
-		.reconfig_from_pll	( )
-	);
-endmodule
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.bsf b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.bsf
deleted file mode 100644
index 5fc6b21ef7816c9dac42988998576dad245883be..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.bsf
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2019  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and any partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details, at
-https://fpgasoftware.intel.com/eula.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 248 184)
-	(text "ip_arria10_e1sg_jesd204b_rx_core_pll" (rect 13 -1 166 11)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 20 180)(font "Arial" ))
-	(port
-		(pt 0 72)
-		(input)
-		(text "refclk_clk" (rect 0 0 38 12)(font "Arial" (font_size 8)))
-		(text "refclk_clk" (rect 4 61 64 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 64 72)(line_width 1))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "reset_reset" (rect 0 0 46 12)(font "Arial" (font_size 8)))
-		(text "reset_reset" (rect 4 101 70 112)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 64 112)(line_width 1))
-	)
-	(port
-		(pt 248 72)
-		(output)
-		(text "locked_export" (rect 0 0 55 12)(font "Arial" (font_size 8)))
-		(text "locked_export" (rect 137 61 215 72)(font "Arial" (font_size 8)))
-	)
-	(port
-		(pt 248 112)
-		(output)
-		(text "outclk0_clk" (rect 0 0 43 12)(font "Arial" (font_size 8)))
-		(text "outclk0_clk" (rect 152 101 218 112)(font "Arial" (font_size 8)))
-	)
-	(port
-		(pt 248 152)
-		(output)
-		(text "outclk1_clk" (rect 0 0 42 12)(font "Arial" (font_size 8)))
-		(text "outclk1_clk" (rect 154 141 220 152)(font "Arial" (font_size 8)))
-	)
-	(drawing
-		(text "locked" (rect 129 43 294 99)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "export" (rect 98 67 232 144)(font "Arial" (color 0 0 0)))
-		(text "outclk0" (rect 129 83 300 179)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 113 107 244 224)(font "Arial" (color 0 0 0)))
-		(text "outclk1" (rect 129 123 300 259)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 113 147 244 304)(font "Arial" (color 0 0 0)))
-		(text "refclk" (rect 32 43 100 99)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 69 67 156 144)(font "Arial" (color 0 0 0)))
-		(text "reset" (rect 35 83 100 179)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "reset" (rect 69 107 168 224)(font "Arial" (color 0 0 0)))
-		(text " ip_arria10_e1sg_jesd204b_rx_core_pll " (rect 39 168 306 346)(font "Arial" ))
-		(line (pt 64 32)(pt 128 32)(line_width 1))
-		(line (pt 128 32)(pt 128 168)(line_width 1))
-		(line (pt 64 168)(pt 128 168)(line_width 1))
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-		(line (pt 127 132)(pt 127 156)(line_width 1))
-		(line (pt 126 132)(pt 126 156)(line_width 1))
-		(line (pt 65 52)(pt 65 76)(line_width 1))
-		(line (pt 66 52)(pt 66 76)(line_width 1))
-		(line (pt 65 92)(pt 65 116)(line_width 1))
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-		(line (pt 0 0)(pt 251 0)(line_width 1))
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-		(line (pt 0 0)(pt 0 184)(line_width 1))
-	)
-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.cmp b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.cmp
deleted file mode 100644
index 258b7db6b3afb0ea752a97e069429ebee516791c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.cmp
+++ /dev/null
@@ -1,10 +0,0 @@
-	component ip_arria10_e1sg_jesd204b_rx_core_pll is
-		port (
-			locked_export : out std_logic;        -- export
-			outclk0_clk   : out std_logic;        -- clk
-			outclk1_clk   : out std_logic;        -- clk
-			refclk_clk    : in  std_logic := 'X'; -- clk
-			reset_reset   : in  std_logic := 'X'  -- reset
-		);
-	end component ip_arria10_e1sg_jesd204b_rx_core_pll;
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.csv b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.csv
deleted file mode 100644
index 756e36aa5c07832e51129903b064d8ffa8346538..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.csv
+++ /dev/null
@@ -1,18 +0,0 @@
-# system info ip_arria10_e1sg_jesd204b_rx_core_pll on 2019.11.25.08:21:57
-system_info:
-name,value
-DEVICE,10AX115U2F45E1SG
-DEVICE_FAMILY,Arria 10
-GENERATION_ID,0
-#
-#
-# Files generated for ip_arria10_e1sg_jesd204b_rx_core_pll on 2019.11.25.08:21:57
-files:
-filepath,kind,attributes,module,is_top
-sim/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,ip_arria10_e1sg_jesd204b_rx_core_pll,true
-altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo,VERILOG,,ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama,false
-#
-# Map from instance-path to kind of module
-instances:
-instancePath,module
-ip_arria10_e1sg_jesd204b_rx_core_pll.core_pll,ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.html b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.html
deleted file mode 100644
index 9ba5e20e4bf01c8280342095d9817c687eca200c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.html
+++ /dev/null
@@ -1,129 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
-  <title>datasheet for ip_arria10_e1sg_jesd204b_rx_core_pll</title>
-  <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
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-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
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- </head>
- <body>
-  <table class="topTitle">
-   <tr>
-    <td class="l">ip_arria10_e1sg_jesd204b_rx_core_pll</td>
-    <td class="r">
-     <br/>
-     <br/>
-    </td>
-   </tr>
-  </table>
-  <table class="blueBar">
-   <tr>
-    <td class="l">2020.11.26.17:23:40</td>
-    <td class="r">Datasheet</td>
-   </tr>
-  </table>
-  <div style="width:100% ;  height:10px"> </div>
-  <div class="label">Overview</div>
-  <div class="greydiv">
-   <div style="display:inline-block ; text-align:left">
-    <table class="connectionboxes">
-     <tr style="height:6px">
-      <td></td>
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-   </div><span style="display:inline-block ; width:28px"> </span>
-   <div style="display:inline-block ; text-align:left"><span>
-     <br/></span>
-   </div>
-  </div>
-  <div style="width:100% ;  height:10px"> </div>
-  <div class="label">Memory Map</div>
-  <table class="mmap">
-   <tr>
-    <td class="empty" rowspan="2"></td>
-   </tr>
-  </table>
-  <a name="module_iopll_0"> </a>
-  <div>
-   <hr/>
-   <h2>iopll_0</h2>altera_iopll v19.3.0
-   <br/>
-   <br/>
-   <br/>
-   <table class="flowbox">
-    <tr>
-     <td class="parametersbox">
-      <h2>Parameters</h2>
-      <table>
-       <tr>
-        <td class="parametername">generateLegacySim</td>
-        <td class="parametervalue">false</td>
-       </tr>
-      </table>
-     </td>
-    </tr>
-   </table>&#160;&#160;
-   <table class="flowbox">
-    <tr>
-     <td class="parametersbox">
-      <h2>Software Assignments</h2>(none)</td>
-    </tr>
-   </table>
-  </div>
-  <table class="blueBar">
-   <tr>
-    <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.00 seconds</td>
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diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.ppf b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.ppf
deleted file mode 100644
index daace63bb8f7d0dc09a835032718bb969ab2c4f2..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.ppf
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<pinplan
- variation_name="core_pll"
- megafunction_name="ALTERA_IOPLL"
- intended_family="Arria 10"
- specifies="all_ports">
- <global>
-  <pin name="rst" direction="input" scope="external" />
-  <pin name="refclk" direction="input" scope="external" />
-  <pin name="locked" direction="output" scope="external" />
-  <pin name="outclk_0" direction="output" scope="external" />
-  <pin name="outclk_1" direction="output" scope="external" />
- </global>
-</pinplan>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsimc b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsimc
deleted file mode 100644
index 390ae976fd9c1f845800283ea0099268089c11c6..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsimc
+++ /dev/null
@@ -1,2877 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
-  <instanceKey xsi:type="xs:string">ip_arria10_e1sg_jesd204b_rx_core_pll</instanceKey>
-  <instanceData xsi:type="data">
-    <parameters></parameters>
-    <interconnectAssignments>
-      <interconnectAssignment>
-        <name>$system.qsys_mm.clockCrossingAdapter</name>
-        <value>HANDSHAKE</value>
-      </interconnectAssignment>
-      <interconnectAssignment>
-        <name>$system.qsys_mm.maxAdditionalLatency</name>
-        <value>0</value>
-      </interconnectAssignment>
-    </interconnectAssignments>
-    <className>ip_arria10_e1sg_jesd204b_rx_core_pll</className>
-    <version>1.0</version>
-    <name>ip_arria10_e1sg_jesd204b_rx_core_pll</name>
-    <uniqueName>ip_arria10_e1sg_jesd204b_rx_core_pll</uniqueName>
-    <nonce>0</nonce>
-    <incidentConnections></incidentConnections>
-  </instanceData>
-  <children>
-    <node>
-      <instanceKey xsi:type="xs:string">core_pll</instanceKey>
-      <instanceData xsi:type="data">
-        <parameters>
-          <parameter>
-            <name>c_cnt_bypass_en0</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en1</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en10</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en11</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en12</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en13</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en14</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en15</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en16</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en17</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en2</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en3</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en4</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en5</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en6</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en7</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en8</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_bypass_en9</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div0</name>
-            <value>4</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div1</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div10</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div11</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div12</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div13</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div14</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div15</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div16</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div17</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div2</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div3</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div4</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div5</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div6</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div7</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div8</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_hi_div9</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src0</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src1</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src10</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src11</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src12</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src13</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src14</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src15</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src16</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src17</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src2</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src3</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src4</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src5</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src6</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src7</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src8</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_in_src9</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div0</name>
-            <value>4</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div1</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div10</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div11</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div12</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div13</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div14</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div15</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div16</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div17</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div2</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div3</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div4</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div5</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div6</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div7</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div8</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_lo_div9</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en0</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en1</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en10</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en11</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en12</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en13</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en14</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en15</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en16</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en17</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en2</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en3</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en4</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en5</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en6</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en7</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en8</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_odd_div_duty_en9</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst0</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst1</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst10</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst11</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst12</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst13</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst14</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst15</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst16</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst17</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst2</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst3</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst4</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst5</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst6</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst7</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst8</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_ph_mux_prst9</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst0</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst1</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst10</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst11</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst12</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst13</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst14</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst15</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst16</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst17</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst2</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst3</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst4</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst5</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst6</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst7</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst8</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>c_cnt_prst9</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>cal_code_hex_file</name>
-            <value>iossm.hex</value>
-          </parameter>
-          <parameter>
-            <name>cal_converge</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>cal_error</name>
-            <value>cal_clean</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_0</name>
-            <value>link_clk</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_1</name>
-            <value>frame_clk</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_2</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_3</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_4</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_5</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_6</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_7</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_8</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_0</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_1</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_2</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_3</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_4</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_5</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_6</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_7</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_name_global_8</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>clock_to_compensate</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor0</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor1</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor2</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor3</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor4</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor5</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor6</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor7</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>divide_factor8</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>dprio_interface_sel</name>
-            <value>3</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle0</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle1</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle10</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle11</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle12</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle13</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle14</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle15</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle16</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle17</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle2</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle3</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle4</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle5</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle6</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle7</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle8</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>duty_cycle9</name>
-            <value>50</value>
-          </parameter>
-          <parameter>
-            <name>eff_m_cnt</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>fractional_vco_multiplier</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_active_clk</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle0</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle1</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle10</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle11</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle12</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle13</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle14</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle15</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle16</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle17</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle2</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle3</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle4</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle5</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle6</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle7</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle8</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle9</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range0</name>
-            <value>45.83,46.43,46.88,50.0,53.12,53.57</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range1</name>
-            <value>41.67,42.86,43.75,50.0,56.25,57.14</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range10</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range11</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range12</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range13</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range14</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range15</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range16</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range17</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range2</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range3</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range4</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range5</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range6</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range7</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range8</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_duty_cycle_range9</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency0</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency1</name>
-            <value>200.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency10</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency11</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency12</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency13</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency14</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency15</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency16</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency17</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency2</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency3</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency4</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency5</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency6</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency7</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency8</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency9</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range0</name>
-            <value>99.595142,99.607843,99.649123,100.0,100.350877,100.392157</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range1</name>
-            <value>183.333333,185.714286,187.5,200.0,214.285714,216.666667</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range10</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range11</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range12</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range13</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range14</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range15</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range16</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range17</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range2</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range3</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range4</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range5</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range6</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range7</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range8</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_output_clock_frequency_range9</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift0</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift1</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg0</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg1</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range0</name>
-            <value>0.0,2.8,3.2,3.8,4.5,5.6</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range1</name>
-            <value>0.0,5.6,6.4,7.5,9.0,11.2</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_deg_range9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range0</name>
-            <value>0.0,78.1,89.3,104.2,125.0,156.2</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range1</name>
-            <value>0.0,78.1,89.3,104.2,125.0,156.2</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_actual_phase_shift_range9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src0</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src1</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src2</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src3</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src4</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src5</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src6</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src7</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_c_cnt_in_src8</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_cal_code_hex_file</name>
-            <value>iossm.hex</value>
-          </parameter>
-          <parameter>
-            <name>gui_cal_converge</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cal_error</name>
-            <value>cal_clean</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter0</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter1</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter10</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter11</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter12</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter13</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter14</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter15</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter16</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter17</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter2</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter3</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter4</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter5</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter6</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter7</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter8</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_counter9</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_cascade_outclk_index</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>gui_clk_bad</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_global</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string0</name>
-            <value>link_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string1</name>
-            <value>frame_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string10</name>
-            <value>outclk10</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string11</name>
-            <value>outclk11</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string12</name>
-            <value>outclk12</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string13</name>
-            <value>outclk13</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string14</name>
-            <value>outclk14</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string15</name>
-            <value>outclk15</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string16</name>
-            <value>outclk16</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string17</name>
-            <value>outclk17</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string2</name>
-            <value>outclk2</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string3</name>
-            <value>outclk3</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string4</name>
-            <value>outclk4</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string5</name>
-            <value>outclk5</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string6</name>
-            <value>outclk6</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string7</name>
-            <value>outclk7</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string8</name>
-            <value>outclk8</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_name_string9</name>
-            <value>outclk9</value>
-          </parameter>
-          <parameter>
-            <name>gui_clock_to_compensate</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>gui_debug_mode</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_device_component</name>
-            <value>10AX115U2F45E1SG</value>
-          </parameter>
-          <parameter>
-            <name>gui_device_family</name>
-            <value>Arria 10</value>
-          </parameter>
-          <parameter>
-            <name>gui_device_speed_grade</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c0</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c1</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c10</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c11</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c12</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c13</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c14</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c15</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c16</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c17</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c2</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c3</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c4</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c5</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c6</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c7</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c8</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_c9</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_divide_factor_n</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_dps_cntr</name>
-            <value>C0</value>
-          </parameter>
-          <parameter>
-            <name>gui_dps_dir</name>
-            <value>Positive</value>
-          </parameter>
-          <parameter>
-            <name>gui_dps_num</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_dsm_out_sel</name>
-            <value>1st_order</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle0</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle1</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle10</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle11</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle12</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle13</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle14</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle15</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle16</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle17</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle2</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle3</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle4</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle5</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle6</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle7</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle8</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_duty_cycle9</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_adv_params</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_dps_ports</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_extclkout_ports</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_lvds_ports</name>
-            <value>Disabled</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_phout_ports</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_en_reconf</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_enable_cascade_in</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_enable_cascade_out</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_enable_mif_dps</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_enable_output_counter_cascading</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_enable_permit_cal</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_existing_mif_file_path</name>
-            <value>~/pll.mif</value>
-          </parameter>
-          <parameter>
-            <name>gui_extclkout_0_source</name>
-            <value>C0</value>
-          </parameter>
-          <parameter>
-            <name>gui_extclkout_1_source</name>
-            <value>C0</value>
-          </parameter>
-          <parameter>
-            <name>gui_feedback_clock</name>
-            <value>Global Clock</value>
-          </parameter>
-          <parameter>
-            <name>gui_fix_vco_frequency</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_fixed_vco_frequency</name>
-            <value>600.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_frac_multiply_factor</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_fractional_cout</name>
-            <value>32</value>
-          </parameter>
-          <parameter>
-            <name>gui_include_iossm</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_lock_setting</name>
-            <value>Low Lock Time</value>
-          </parameter>
-          <parameter>
-            <name>gui_mif_config_name</name>
-            <value>unnamed</value>
-          </parameter>
-          <parameter>
-            <name>gui_mif_gen_options</name>
-            <value>Generate New MIF File</value>
-          </parameter>
-          <parameter>
-            <name>gui_multiply_factor</name>
-            <value>6</value>
-          </parameter>
-          <parameter>
-            <name>gui_new_mif_file_path</name>
-            <value>~/pll.mif</value>
-          </parameter>
-          <parameter>
-            <name>gui_number_of_clocks</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>gui_operation_mode</name>
-            <value>source synchronous</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency0</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency1</name>
-            <value>200.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency10</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency11</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency12</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency13</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency14</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency15</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency16</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency17</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency2</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency3</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency4</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency5</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency6</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency7</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency8</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_output_clock_frequency9</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_parameter_table_hex_file</name>
-            <value>seq_params_sim.hex</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift0</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift1</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg0</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg1</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phase_shift_deg9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_phout_division</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_auto_reset</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_bandwidth_preset</name>
-            <value>Low</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_cal_done</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_cascading_mode</name>
-            <value>adjpllin</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_freqcal_en</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_freqcal_req_flag</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_m_cnt_in_src</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_mode</name>
-            <value>Integer-N PLL</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_tclk_mux_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_tclk_sel</name>
-            <value>pll_tclk_m_src</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_type</name>
-            <value>S10_Simple</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_vco_freq_band_0</name>
-            <value>pll_freq_clk0_disabled</value>
-          </parameter>
-          <parameter>
-            <name>gui_pll_vco_freq_band_1</name>
-            <value>pll_freq_clk1_disabled</value>
-          </parameter>
-          <parameter>
-            <name>gui_prot_mode</name>
-            <value>UNUSED</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units0</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units1</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units10</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units11</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units12</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units13</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units14</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units15</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units16</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units17</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units2</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units3</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units4</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units5</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units6</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units7</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units8</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_ps_units9</name>
-            <value>ps</value>
-          </parameter>
-          <parameter>
-            <name>gui_refclk1_frequency</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_refclk_might_change</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_refclk_switch</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_reference_clock_frequency</name>
-            <value>200.0</value>
-          </parameter>
-          <parameter>
-            <name>gui_skip_sdc_generation</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_switchover_delay</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>gui_switchover_mode</name>
-            <value>Automatic Switchover</value>
-          </parameter>
-          <parameter>
-            <name>gui_use_NDFB_modes</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_use_coreclk</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_use_locked</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>gui_use_logical</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>gui_usr_device_speed_grade</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>gui_vco_frequency</name>
-            <value>600.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp0</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp1</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp10</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp11</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp12</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp13</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp14</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp15</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp16</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp17</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp2</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp3</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp4</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp5</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp6</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp7</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp8</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_duty_cycle_fp9</name>
-            <value>50.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp0</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp1</name>
-            <value>200.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp10</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp11</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp12</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp13</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp14</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp15</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp16</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp17</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp2</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp3</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp4</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp5</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp6</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp7</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp8</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_output_clock_frequency_fp9</name>
-            <value>100.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp0</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp1</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp10</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp11</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp12</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp13</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp14</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp15</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp16</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp17</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp2</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp3</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp4</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp5</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp6</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp7</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp8</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_phase_shift_fp9</name>
-            <value>0.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_actual_vco_frequency_fp</name>
-            <value>600.0</value>
-          </parameter>
-          <parameter>
-            <name>hp_number_of_family_allowable_clocks</name>
-            <value>9</value>
-          </parameter>
-          <parameter>
-            <name>hp_parameter_update_message</name>
-            <value>{altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_family }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_component }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_speed_grade }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_dps_cntr}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_extclkout_source}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_cascade_outclk_index}} {altera_iopll::util::pll_send_message DEBUG { -- in update gui_clock_to_compensate}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_pll_bandwidth_preset}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_vco_frequency}} {altera_iopll::util::pll_send_message DEBUG { -- Updating all outclk values in order, starting with freq 0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_family }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_component }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_speed_grade }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_dps_cntr}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_extclkout_source}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_cascade_outclk_index}} {altera_iopll::util::pll_send_message DEBUG { -- in update gui_clock_to_compensate}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_pll_bandwidth_preset}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_vco_frequency}} {altera_iopll::util::pll_send_message DEBUG { -- Updating all outclk values in order, starting with freq 0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_family }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_component }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_speed_grade }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_dps_cntr}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_extclkout_source}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_cascade_outclk_index}} {altera_iopll::util::pll_send_message DEBUG { -- in update gui_clock_to_compensate}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_pll_bandwidth_preset}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_vco_frequency}} {altera_iopll::util::pll_send_message DEBUG { -- Updating all outclk values in order, starting with freq 0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle8}}</value>
-          </parameter>
-          <parameter>
-            <name>hp_previous_num_clocks</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>hp_qsys_scripting_mode</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>include_iossm</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>iossm_nios_sim_clk_period_ps</name>
-            <value>1333</value>
-          </parameter>
-          <parameter>
-            <name>lock_mode</name>
-            <value>low_lock_time</value>
-          </parameter>
-          <parameter>
-            <name>m_cnt_bypass_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>m_cnt_hi_div</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>m_cnt_lo_div</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>m_cnt_odd_div_duty_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>mifTable_names</name>
-            <value>The MIF file specified does not yet exist</value>
-          </parameter>
-          <parameter>
-            <name>mifTable_values</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>mimic_fbclk_type</name>
-            <value>gclk</value>
-          </parameter>
-          <parameter>
-            <name>multiply_factor</name>
-            <value>4</value>
-          </parameter>
-          <parameter>
-            <name>n_cnt_bypass_en</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>n_cnt_hi_div</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>n_cnt_lo_div</name>
-            <value>256</value>
-          </parameter>
-          <parameter>
-            <name>n_cnt_odd_div_duty_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>number_of_clocks</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>number_of_outclks</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>operation_mode</name>
-            <value>source_synchronous</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency0</name>
-            <value>100.000000 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency1</name>
-            <value>200.000000 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency10</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency11</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency12</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency13</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency14</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency15</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency16</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency17</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency2</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency3</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency4</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency5</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency6</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency7</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency8</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>output_clock_frequency9</name>
-            <value>0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>parameterTable_names</name>
-            <value>M-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control</value>
-          </parameter>
-          <parameter>
-            <name>parameterTable_values</name>
-            <value>4,1,800.0 MHz,8,4,1,1,1,1,1,1,1,false,2,2,false,false,256,256,false,true,4,2,256,256,256,256,256,256,256,4,2,256,256,256,256,256,256,256,false,false,false,false,false,false,false,false,false,false,false,true,true,true,true,true,true,true,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting10,pll_bw_res_setting2</value>
-          </parameter>
-          <parameter>
-            <name>parameter_table_hex_file</name>
-            <value>seq_params_sim.hex</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift0</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift1</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift10</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift11</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift12</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift13</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift14</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift15</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift16</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift17</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift2</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift3</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift4</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift5</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift6</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift7</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift8</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>phase_shift9</name>
-            <value>0 ps</value>
-          </parameter>
-          <parameter>
-            <name>pll_auto_clk_sw_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_bw_sel</name>
-            <value>Low</value>
-          </parameter>
-          <parameter>
-            <name>pll_bwctrl</name>
-            <value>pll_bw_res_setting2</value>
-          </parameter>
-          <parameter>
-            <name>pll_cal_done</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_clk_loss_sw_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_clk_sw_dly</name>
-            <value>0</value>
-          </parameter>
-          <parameter>
-            <name>pll_clkin_0_src</name>
-            <value>clk_0</value>
-          </parameter>
-          <parameter>
-            <name>pll_clkin_1_src</name>
-            <value>clk_0</value>
-          </parameter>
-          <parameter>
-            <name>pll_cp_current</name>
-            <value>pll_cp_setting10</value>
-          </parameter>
-          <parameter>
-            <name>pll_defer_cal_user_mode</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>pll_dsm_out_sel</name>
-            <value>1st_order</value>
-          </parameter>
-          <parameter>
-            <name>pll_extclk_0_cnt_src</name>
-            <value>pll_extclk_cnt_src_vss</value>
-          </parameter>
-          <parameter>
-            <name>pll_extclk_1_cnt_src</name>
-            <value>pll_extclk_cnt_src_vss</value>
-          </parameter>
-          <parameter>
-            <name>pll_fbclk_mux_1</name>
-            <value>pll_fbclk_mux_1_glb</value>
-          </parameter>
-          <parameter>
-            <name>pll_fbclk_mux_2</name>
-            <value>pll_fbclk_mux_2_fb_1</value>
-          </parameter>
-          <parameter>
-            <name>pll_fractional_cout</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>pll_fractional_division</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>pll_freqcal_en</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>pll_freqcal_req_flag</name>
-            <value>true</value>
-          </parameter>
-          <parameter>
-            <name>pll_lock_fltr_cfg</name>
-            <value>100</value>
-          </parameter>
-          <parameter>
-            <name>pll_m_cnt</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>pll_m_cnt_basic</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>pll_m_cnt_in_src</name>
-            <value>c_m_cnt_in_src_ph_mux_clk</value>
-          </parameter>
-          <parameter>
-            <name>pll_manu_clk_sw_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_output_clk_frequency</name>
-            <value>800.0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>pll_ripplecap_ctrl</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>pll_slf_rst</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_subtype</name>
-            <value>General</value>
-          </parameter>
-          <parameter>
-            <name>pll_tclk_mux_en</name>
-            <value>false</value>
-          </parameter>
-          <parameter>
-            <name>pll_tclk_sel</name>
-            <value>pll_tclk_m_src</value>
-          </parameter>
-          <parameter>
-            <name>pll_type</name>
-            <value>Arria 10</value>
-          </parameter>
-          <parameter>
-            <name>pll_unlock_fltr_cfg</name>
-            <value>2</value>
-          </parameter>
-          <parameter>
-            <name>pll_vco_div</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>pll_vco_freq_band_0</name>
-            <value>pll_freq_clk0_disabled</value>
-          </parameter>
-          <parameter>
-            <name>pll_vco_freq_band_1</name>
-            <value>pll_freq_clk1_disabled</value>
-          </parameter>
-          <parameter>
-            <name>pll_vcoph_div</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>prot_mode</name>
-            <value>BASIC</value>
-          </parameter>
-          <parameter>
-            <name>refclk1_frequency</name>
-            <value>100.0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>reference_clock_frequency</name>
-            <value>200.0 MHz</value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_component</name>
-            <value>10AX115U2F45E1SG</value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_family</name>
-            <value>Arria 10</value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_speed_grade</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>system_part_trait_speed_grade</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>use_core_refclk</name>
-            <value>false</value>
-          </parameter>
-        </parameters>
-        <interconnectAssignments></interconnectAssignments>
-        <className>altera_iopll</className>
-        <version>18.0</version>
-        <name>core_pll</name>
-        <uniqueName>ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama</uniqueName>
-        <nonce>0</nonce>
-        <incidentConnections></incidentConnections>
-        <path>ip_arria10_e1sg_jesd204b_rx_core_pll.core_pll</path>
-      </instanceData>
-      <children></children>
-    </node>
-  </children>
-</node>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsynthc b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsynthc
deleted file mode 100644
index e1097d9539d494f2e25861550baff5061ed91f75..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qgsynthc
+++ /dev/null
@@ -1,584 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
-  <instanceKey xsi:type="xs:string">ip_arria10_e1sg_jesd204b_rx_core_pll</instanceKey>
-  <instanceData xsi:type="data">
-    <parameters></parameters>
-    <interconnectAssignments></interconnectAssignments>
-    <className>ip_arria10_e1sg_jesd204b_rx_core_pll</className>
-    <version>1.0</version>
-    <name>ip_arria10_e1sg_jesd204b_rx_core_pll</name>
-    <uniqueName>ip_arria10_e1sg_jesd204b_rx_core_pll</uniqueName>
-    <nonce>0</nonce>
-    <incidentConnections></incidentConnections>
-  </instanceData>
-  <children>
-    <node>
-      <instanceKey xsi:type="xs:string">iopll_0</instanceKey>
-      <instanceData xsi:type="data">
-        <parameters>
-          <parameter>
-            <name>componentDefinition</name>
-            <value>&lt;componentDefinition&gt;
-    &lt;boundary&gt;
-        &lt;interfaces&gt;
-            &lt;interface&gt;
-                &lt;name&gt;locked&lt;/name&gt;
-                &lt;type&gt;conduit&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;locked&lt;/name&gt;
-                        &lt;role&gt;export&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedReset&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;prSafe&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;outclk0&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;true&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;outclk_0&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRateKnown&lt;/key&gt;
-                            &lt;value&gt;true&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;outclk1&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;true&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;outclk_1&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRateKnown&lt;/key&gt;
-                            &lt;value&gt;true&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;refclk&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;refclk&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Input&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;input&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;reset&lt;/name&gt;
-                &lt;type&gt;reset&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;rst&lt;/name&gt;
-                        &lt;role&gt;reset&lt;/role&gt;
-                        &lt;direction&gt;Input&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;input&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;synchronousEdges&lt;/key&gt;
-                            &lt;value&gt;NONE&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-        &lt;/interfaces&gt;
-    &lt;/boundary&gt;
-    &lt;originalModuleInfo&gt;
-        &lt;className&gt;altera_iopll&lt;/className&gt;
-        &lt;version&gt;19.3.0&lt;/version&gt;
-        &lt;displayName&gt;IOPLL Intel FPGA IP&lt;/displayName&gt;
-    &lt;/originalModuleInfo&gt;
-    &lt;systemInfoParameterDescriptors&gt;
-        &lt;descriptors&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_component&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_family&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE_FAMILY&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_speed_grade&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE_SPEEDGRADE&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_part_trait_speed_grade&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfoArgs&gt;DEVICE_SPEEDGRADE&lt;/systemInfoArgs&gt;
-                &lt;systemInfotype&gt;PART_TRAIT&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-        &lt;/descriptors&gt;
-    &lt;/systemInfoParameterDescriptors&gt;
-    &lt;systemInfos&gt;
-        &lt;connPtSystemInfos&gt;
-            &lt;entry&gt;
-                &lt;key&gt;outclk0&lt;/key&gt;
-                &lt;value&gt;
-                    &lt;connectionPointName&gt;outclk0&lt;/connectionPointName&gt;
-                    &lt;suppliedSystemInfos&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/suppliedSystemInfos&gt;
-                    &lt;consumedSystemInfos/&gt;
-                &lt;/value&gt;
-            &lt;/entry&gt;
-            &lt;entry&gt;
-                &lt;key&gt;outclk1&lt;/key&gt;
-                &lt;value&gt;
-                    &lt;connectionPointName&gt;outclk1&lt;/connectionPointName&gt;
-                    &lt;suppliedSystemInfos&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/suppliedSystemInfos&gt;
-                    &lt;consumedSystemInfos/&gt;
-                &lt;/value&gt;
-            &lt;/entry&gt;
-        &lt;/connPtSystemInfos&gt;
-    &lt;/systemInfos&gt;
-&lt;/componentDefinition&gt;</value>
-          </parameter>
-          <parameter>
-            <name>defaultBoundary</name>
-            <value>&lt;boundaryDefinition&gt;
-    &lt;interfaces&gt;
-        &lt;interface&gt;
-            &lt;name&gt;locked&lt;/name&gt;
-            &lt;type&gt;conduit&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;locked&lt;/name&gt;
-                    &lt;role&gt;export&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedReset&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;prSafe&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;outclk0&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;true&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;outclk_0&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRateKnown&lt;/key&gt;
-                        &lt;value&gt;true&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;outclk1&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;true&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;outclk_1&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRateKnown&lt;/key&gt;
-                        &lt;value&gt;true&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;refclk&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;refclk&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;input&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;reset&lt;/name&gt;
-            &lt;type&gt;reset&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;rst&lt;/name&gt;
-                    &lt;role&gt;reset&lt;/role&gt;
-                    &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;input&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;synchronousEdges&lt;/key&gt;
-                        &lt;value&gt;NONE&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-    &lt;/interfaces&gt;
-&lt;/boundaryDefinition&gt;</value>
-          </parameter>
-          <parameter>
-            <name>generationInfoDefinition</name>
-            <value>&lt;generationInfoDefinition&gt;
-    &lt;hdlLibraryName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/hdlLibraryName&gt;
-    &lt;fileSets&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-    &lt;/fileSets&gt;
-&lt;/generationInfoDefinition&gt;</value>
-          </parameter>
-          <parameter>
-            <name>hlsFile</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>logicalView</name>
-            <value>ip_arria10_e1sg_jesd204b_rx_core_pll.ip</value>
-          </parameter>
-          <parameter>
-            <name>moduleAssignmentDefinition</name>
-            <value>&lt;assignmentDefinition&gt;
-    &lt;assignmentValueMap&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.compatible&lt;/key&gt;
-            &lt;value&gt;altr,pll&lt;/value&gt;
-        &lt;/entry&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.group&lt;/key&gt;
-            &lt;value&gt;clock&lt;/value&gt;
-        &lt;/entry&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.vendor&lt;/key&gt;
-            &lt;value&gt;altr&lt;/value&gt;
-        &lt;/entry&gt;
-    &lt;/assignmentValueMap&gt;
-&lt;/assignmentDefinition&gt;</value>
-          </parameter>
-          <parameter>
-            <name>svInterfaceDefinition</name>
-            <value></value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_component</name>
-            <value>10AX115U2F45E1SG</value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_family</name>
-            <value>Arria 10</value>
-          </parameter>
-          <parameter>
-            <name>system_info_device_speed_grade</name>
-            <value>1</value>
-          </parameter>
-          <parameter>
-            <name>system_part_trait_speed_grade</name>
-            <value>1</value>
-          </parameter>
-        </parameters>
-        <interconnectAssignments></interconnectAssignments>
-        <className>altera_generic_component</className>
-        <version>1.0</version>
-        <name>iopll_0</name>
-        <uniqueName>ip_arria10_e1sg_jesd204b_rx_core_pll</uniqueName>
-        <fixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fixedName>
-        <nonce>0</nonce>
-        <incidentConnections></incidentConnections>
-        <path>ip_arria10_e1sg_jesd204b_rx_core_pll.iopll_0</path>
-      </instanceData>
-      <children></children>
-    </node>
-  </children>
-</node>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
deleted file mode 100644
index 63dd17af4990f987336a812cc3b2071a352b4106..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
+++ /dev/null
@@ -1,49 +0,0 @@
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_TOOL_VERSION "19.4"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "ip_arria10_e1sg_jesd204b_rx_core_pll.sopcinfo"]
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name SLD_INFO "QSYS_NAME ip_arria10_e1sg_jesd204b_rx_core_pll HAS_SOPCINFO 1 GENERATION_ID 0"
-set_global_assignment -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name MISC_FILE [file join $::quartus(qip_path) "ip_arria10_e1sg_jesd204b_rx_core_pll.cmp"]
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_TARGETED_PART_TRAIT "DEVICE_SPEEDGRADE::1"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_QSYS_MODE "SYSTEM"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name MISC_FILE [file join $::quartus(qip_path) "../ip_arria10_e1sg_jesd204b_rx_core_pll.qsys"]
-
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_NAME "aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxs"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_DISPLAY_NAME "R2VuZXJpYyBDb21wb25lbnQ="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_DESCRIPTION "QSBkeW5hbWljIGNvbXBvbmVudCB3aGVyZSB5b3UgY2FuIGFkZCwgbW9kaWZ5IG9yIHJlbW92ZSBpbnRlcmZhY2VzIGFuZCBwb3J0cyBvbiB0aGUgZmx5"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "Y29tcG9uZW50RGVmaW5pdGlvbg==::<componentDefinition>
    <boundary>
        <interfaces>
            <interface>
                <name>locked</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>locked</name>
                        <role>export</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>outclk0</name>
                <type>clock</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>outclk_0</name>
                        <role>clk</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedDirectClock</key>
                        </entry>
                        <entry>
                            <key>clockRate</key>
                            <value>100000000</value>
                        </entry>
                        <entry>
                            <key>clockRateKnown</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>outclk1</name>
                <type>clock</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>outclk_1</name>
                        <role>clk</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedDirectClock</key>
                        </entry>
                        <entry>
                            <key>clockRate</key>
                            <value>100000000</value>
                        </entry>
                        <entry>
                            <key>clockRateKnown</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>refclk</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>refclk</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>input</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>100000000</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>reset</name>
                <type>reset</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>rst</name>
                        <role>reset</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>input</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>NONE</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
        </interfaces>
    </boundary>
    <originalModuleInfo>
        <className>altera_iopll</className>
        <version>19.3.0</version>
        <displayName>IOPLL Intel FPGA IP</displayName>
    </originalModuleInfo>
    <systemInfoParameterDescriptors>
        <descriptors>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_component</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_family</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE_FAMILY</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_speed_grade</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_part_trait_speed_grade</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_SPEEDGRADE</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
        </descriptors>
    </systemInfoParameterDescriptors>
    <systemInfos>
        <connPtSystemInfos>
            <entry>
                <key>outclk0</key>
                <value>
                    <connectionPointName>outclk0</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>100000000</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
            <entry>
                <key>outclk1</key>
                <value>
                    <connectionPointName>outclk1</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>100000000</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
        </connPtSystemInfos>
    </systemInfos>
</componentDefinition>::Q29tcG9uZW50IGRlZmluaXRpb24="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "Z2VuZXJhdGlvbkluZm9EZWZpbml0aW9u::PGdlbmVyYXRpb25JbmZvRGVmaW5pdGlvbj4KICAgIDxoZGxMaWJyYXJ5TmFtZT5pcF9hcnJpYTEwX2Uxc2dfamVzZDIwNGJfcnhfY29yZV9wbGw8L2hkbExpYnJhcnlOYW1lPgogICAgPGZpbGVTZXRzPgogICAgICAgIDxmaWxlU2V0PgogICAgICAgICAgICA8ZmlsZVNldE5hbWU+aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxsPC9maWxlU2V0TmFtZT4KICAgICAgICAgICAgPGZpbGVTZXRGaXhlZE5hbWU+aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxsPC9maWxlU2V0Rml4ZWROYW1lPgogICAgICAgICAgICA8ZmlsZVNldEtpbmQ+UVVBUlRVU19TWU5USDwvZmlsZVNldEtpbmQ+CiAgICAgICAgICAgIDxmaWxlU2V0RmlsZXMvPgogICAgICAgIDwvZmlsZVNldD4KICAgICAgICA8ZmlsZVNldD4KICAgICAgICAgICAgPGZpbGVTZXROYW1lPmlwX2FycmlhMTBfZTFzZ19qZXNkMjA0Yl9yeF9jb3JlX3BsbDwvZmlsZVNldE5hbWU+CiAgICAgICAgICAgIDxmaWxlU2V0Rml4ZWROYW1lPmlwX2FycmlhMTBfZTFzZ19qZXNkMjA0Yl9yeF9jb3JlX3BsbDwvZmlsZVNldEZpeGVkTmFtZT4KICAgICAgICAgICAgPGZpbGVTZXRLaW5kPlNJTV9WRVJJTE9HPC9maWxlU2V0S2luZD4KICAgICAgICAgICAgPGZpbGVTZXRGaWxlcy8+CiAgICAgICAgPC9maWxlU2V0PgogICAgICAgIDxmaWxlU2V0PgogICAgICAgICAgICA8ZmlsZVNldE5hbWU+aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxsPC9maWxlU2V0TmFtZT4KICAgICAgICAgICAgPGZpbGVTZXRGaXhlZE5hbWU+aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxsPC9maWxlU2V0Rml4ZWROYW1lPgogICAgICAgICAgICA8ZmlsZVNldEtpbmQ+U0lNX1ZIREw8L2ZpbGVTZXRLaW5kPgogICAgICAgICAgICA8ZmlsZVNldEZpbGVzLz4KICAgICAgICA8L2ZpbGVTZXQ+CiAgICA8L2ZpbGVTZXRzPgo8L2dlbmVyYXRpb25JbmZvRGVmaW5pdGlvbj4=::R2VuZXJhdGlvbiBCZWhhdmlvcg=="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "bG9naWNhbFZpZXc=::aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxsLmlw::TG9naWNhbCB2aWV3"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "ZGVmYXVsdEJvdW5kYXJ5::<boundaryDefinition>
    <interfaces>
        <interface>
            <name>locked</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>locked</name>
                    <role>export</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>outclk0</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>outclk_0</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>100000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>outclk1</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>outclk_1</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>100000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>refclk</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>refclk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>input</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>100000000</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>reset</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>rst</name>
                    <role>reset</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>input</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>::RGVmYXVsdCBib3VuZGFyeQ=="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "bW9kdWxlQXNzaWdubWVudERlZmluaXRpb24=::PGFzc2lnbm1lbnREZWZpbml0aW9uPgogICAgPGFzc2lnbm1lbnRWYWx1ZU1hcD4KICAgICAgICA8ZW50cnk+CiAgICAgICAgICAgIDxrZXk+ZW1iZWRkZWRzdy5kdHMuY29tcGF0aWJsZTwva2V5PgogICAgICAgICAgICA8dmFsdWU+YWx0cixwbGw8L3ZhbHVlPgogICAgICAgIDwvZW50cnk+CiAgICAgICAgPGVudHJ5PgogICAgICAgICAgICA8a2V5PmVtYmVkZGVkc3cuZHRzLmdyb3VwPC9rZXk+CiAgICAgICAgICAgIDx2YWx1ZT5jbG9jazwvdmFsdWU+CiAgICAgICAgPC9lbnRyeT4KICAgICAgICA8ZW50cnk+CiAgICAgICAgICAgIDxrZXk+ZW1iZWRkZWRzdy5kdHMudmVuZG9yPC9rZXk+CiAgICAgICAgICAgIDx2YWx1ZT5hbHRyPC92YWx1ZT4KICAgICAgICA8L2VudHJ5PgogICAgPC9hc3NpZ25tZW50VmFsdWVNYXA+CjwvYXNzaWdubWVudERlZmluaXRpb24+::TW9kdWxlIEFzc2lnbm1lbnRz"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "c3lzdGVtX2luZm9fZGV2aWNlX2NvbXBvbmVudA==::MTBBWDExNVUyRjQ1RTFTRw==::c3lzdGVtX2luZm9fZGV2aWNlX2NvbXBvbmVudA=="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "c3lzdGVtX2luZm9fZGV2aWNlX2ZhbWlseQ==::QXJyaWEgMTA=::c3lzdGVtX2luZm9fZGV2aWNlX2ZhbWlseQ=="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "c3lzdGVtX2luZm9fZGV2aWNlX3NwZWVkX2dyYWRl::MQ==::c3lzdGVtX2luZm9fZGV2aWNlX3NwZWVkX2dyYWRl"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "c3lzdGVtX3BhcnRfdHJhaXRfc3BlZWRfZ3JhZGU=::MQ==::c3lzdGVtX3BhcnRfdHJhaXRfc3BlZWRfZ3JhZGU="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_GROUP "R2VuZXJpYyBDb21wb25lbnQ="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_NAME "aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxs"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_DISPLAY_NAME "aXBfYXJyaWExMF9lMXNnX2plc2QyMDRiX3J4X2NvcmVfcGxs"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19SRUZDTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_PARAMETER "QVVUT19SRUZDTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-set_global_assignment -entity "ip_arria10_e1sg_jesd204b_rx_core_pll" -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name IP_COMPONENT_GROUP "U3lzdGVt"
-
-
-set_global_assignment -library "ip_arria10_e1sg_jesd204b_rx_core_pll" -name VHDL_FILE [file join $::quartus(qip_path) "synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"]
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.sopcinfo b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.sopcinfo
deleted file mode 100644
index 4816c71b98e4b4e3162637fa32178ed331dddaba..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.sopcinfo
+++ /dev/null
@@ -1,1119 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="ip_arria10_e1sg_jesd204b_rx_core_pll"
- kind="ip_arria10_e1sg_jesd204b_rx_core_pll"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 19.4 64 (Future versions may contain additional information.) -->
- <!-- 2020.11.26.17:23:40 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
-  <type>java.lang.Integer</type>
-  <value>0</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
-  <type>java.lang.String</type>
-  <value></value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
-  <type>java.lang.String</type>
-  <value>ARRIA10</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
-  <type>java.lang.String</type>
-  <value>10AX115U2F45E1SG</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
-  <type>java.lang.String</type>
-  <value>1</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_REFCLK_CLOCK_RATE">
-  <type>java.lang.Long</type>
-  <value>-1</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>CLOCK_RATE</sysinfo_type>
-  <sysinfo_arg>refclk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_REFCLK_CLOCK_DOMAIN">
-  <type>java.lang.Integer</type>
-  <value>-1</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
-  <sysinfo_arg>refclk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_REFCLK_RESET_DOMAIN">
-  <type>java.lang.Integer</type>
-  <value>-1</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
-  <sysinfo_arg>refclk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
-  <type>java.lang.String</type>
-  <value>Arria 10</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>false</visible>
-  <valid>true</valid>
-  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
-  <type>boolean</type>
-  <value>false</value>
-  <derived>false</derived>
-  <enabled>true</enabled>
-  <visible>true</visible>
-  <valid>true</valid>
- </parameter>
- <module
-   name="iopll_0"
-   kind="altera_iopll"
-   version="19.3.0"
-   entity="ip_arria10_e1sg_jesd204b_rx_core_pll"
-   library="ip_arria10_e1sg_jesd204b_rx_core_pll"
-   path="iopll_0"
-   hpath="iopll_0">
-  <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
-  <assignment>
-   <name>embeddedsw.dts.compatible</name>
-   <value>altr,pll</value>
-  </assignment>
-  <assignment>
-   <name>embeddedsw.dts.group</name>
-   <value>clock</value>
-  </assignment>
-  <assignment>
-   <name>embeddedsw.dts.vendor</name>
-   <value>altr</value>
-  </assignment>
-  <parameter name="componentDefinition">
-   <type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
-   <value><![CDATA[<componentDefinition>
-    <boundary>
-        <interfaces>
-            <interface>
-                <name>locked</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>locked</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>ui.blockdiagram.direction</key>
-                            <value>output</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>outclk0</name>
-                <type>clock</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>outclk_0</name>
-                        <role>clk</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>ui.blockdiagram.direction</key>
-                            <value>output</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedDirectClock</key>
-                        </entry>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>clockRateKnown</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>outclk1</name>
-                <type>clock</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>outclk_1</name>
-                        <role>clk</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>ui.blockdiagram.direction</key>
-                            <value>output</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedDirectClock</key>
-                        </entry>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>clockRateKnown</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>refclk</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>refclk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>ui.blockdiagram.direction</key>
-                            <value>input</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>rst</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>ui.blockdiagram.direction</key>
-                            <value>input</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>NONE</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-        </interfaces>
-    </boundary>
-    <originalModuleInfo>
-        <className>altera_iopll</className>
-        <version>19.3.0</version>
-        <displayName>IOPLL Intel FPGA IP</displayName>
-    </originalModuleInfo>
-    <systemInfoParameterDescriptors>
-        <descriptors>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>system_info_device_component</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>system_info_device_family</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_FAMILY</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>system_info_device_speed_grade</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>system_part_trait_speed_grade</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>DEVICE_SPEEDGRADE</systemInfoArgs>
-                <systemInfotype>PART_TRAIT</systemInfotype>
-            </descriptor>
-        </descriptors>
-    </systemInfoParameterDescriptors>
-    <systemInfos>
-        <connPtSystemInfos>
-            <entry>
-                <key>outclk0</key>
-                <value>
-                    <connectionPointName>outclk0</connectionPointName>
-                    <suppliedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </suppliedSystemInfos>
-                    <consumedSystemInfos/>
-                </value>
-            </entry>
-            <entry>
-                <key>outclk1</key>
-                <value>
-                    <connectionPointName>outclk1</connectionPointName>
-                    <suppliedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </suppliedSystemInfos>
-                    <consumedSystemInfos/>
-                </value>
-            </entry>
-        </connPtSystemInfos>
-    </systemInfos>
-</componentDefinition>]]></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="generationInfoDefinition">
-   <type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
-   <value><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>ip_arria10_e1sg_jesd204b_rx_core_pll</hdlLibraryName>
-    <fileSets>
-        <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
-            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
-            <fileSetKind>SIM_VERILOG</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
-            <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="hlsFile">
-   <type>java.lang.String</type>
-   <value></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="logicalView">
-   <type>java.lang.String</type>
-   <value>ip_arria10_e1sg_jesd204b_rx_core_pll.ip</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="defaultBoundary">
-   <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
-   <value><![CDATA[<boundaryDefinition>
-    <interfaces>
-        <interface>
-            <name>locked</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>locked</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>outclk0</name>
-            <type>clock</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>outclk_0</name>
-                    <role>clk</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedDirectClock</key>
-                    </entry>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>clockRateKnown</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>outclk1</name>
-            <type>clock</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>outclk_1</name>
-                    <role>clk</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>output</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedDirectClock</key>
-                    </entry>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>clockRateKnown</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>refclk</name>
-            <type>clock</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>refclk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>reset</name>
-            <type>reset</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>rst</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>ui.blockdiagram.direction</key>
-                        <value>input</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>NONE</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-    </interfaces>
-</boundaryDefinition>]]></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="moduleAssignmentDefinition">
-   <type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
-   <value><![CDATA[<assignmentDefinition>
-    <assignmentValueMap>
-        <entry>
-            <key>embeddedsw.dts.compatible</key>
-            <value>altr,pll</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.group</key>
-            <value>clock</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.vendor</key>
-            <value>altr</value>
-        </entry>
-    </assignmentValueMap>
-</assignmentDefinition>]]></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="svInterfaceDefinition">
-   <type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
-   <value></value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-  </parameter>
-  <parameter name="system_info_device_component">
-   <type>java.lang.String</type>
-   <value>10AX115U2F45E1SG</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE</sysinfo_type>
-  </parameter>
-  <parameter name="system_info_device_family">
-   <type>java.lang.String</type>
-   <value>ARRIA10</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
-  </parameter>
-  <parameter name="system_info_device_speed_grade">
-   <type>java.lang.String</type>
-   <value>1</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
-  </parameter>
-  <parameter name="system_part_trait_speed_grade">
-   <type>java.lang.String</type>
-   <value>1</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>PART_TRAIT</sysinfo_type>
-   <sysinfo_arg>DEVICE_SPEEDGRADE</sysinfo_arg>
-  </parameter>
-  <parameter name="AUTO_DEVICE_FAMILY">
-   <type>java.lang.String</type>
-   <value>ARRIA10</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
-  </parameter>
-  <parameter name="AUTO_DEVICE">
-   <type>java.lang.String</type>
-   <value>10AX115U2F45E1SG</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE</sysinfo_type>
-  </parameter>
-  <parameter name="deviceFamily">
-   <type>java.lang.String</type>
-   <value>Arria 10</value>
-   <derived>true</derived>
-   <enabled>true</enabled>
-   <visible>false</visible>
-   <valid>true</valid>
-   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
-  </parameter>
-  <parameter name="generateLegacySim">
-   <type>boolean</type>
-   <value>false</value>
-   <derived>false</derived>
-   <enabled>true</enabled>
-   <visible>true</visible>
-   <valid>true</valid>
-  </parameter>
-  <interface name="locked" kind="conduit_end" version="19.4">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>output</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="associatedReset">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="prSafe">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>conduit</type>
-   <isStart>false</isStart>
-   <port>
-    <name>locked</name>
-    <direction>Output</direction>
-    <width>1</width>
-    <role>export</role>
-   </port>
-  </interface>
-  <interface name="outclk0" kind="clock_source" version="19.4">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>output</value>
-   </assignment>
-   <parameter name="associatedDirectClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRate">
-    <type>long</type>
-    <value>100000000</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRateKnown">
-    <type>boolean</type>
-    <value>true</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="externallyDriven">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="ptfSchematicName">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>clock</type>
-   <isStart>true</isStart>
-   <port>
-    <name>outclk_0</name>
-    <direction>Output</direction>
-    <width>1</width>
-    <role>clk</role>
-   </port>
-  </interface>
-  <interface name="outclk1" kind="clock_source" version="19.4">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>output</value>
-   </assignment>
-   <parameter name="associatedDirectClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRate">
-    <type>long</type>
-    <value>100000000</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRateKnown">
-    <type>boolean</type>
-    <value>true</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="externallyDriven">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="ptfSchematicName">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>clock</type>
-   <isStart>true</isStart>
-   <port>
-    <name>outclk_1</name>
-    <direction>Output</direction>
-    <width>1</width>
-    <role>clk</role>
-   </port>
-  </interface>
-  <interface name="refclk" kind="clock_sink" version="19.4">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>input</value>
-   </assignment>
-   <parameter name="externallyDriven">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="ptfSchematicName">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRateKnown">
-    <type>java.lang.Boolean</type>
-    <value>true</value>
-    <derived>true</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="clockRate">
-    <type>java.lang.Long</type>
-    <value>100000000</value>
-    <derived>true</derived>
-    <enabled>true</enabled>
-    <visible>false</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>clock</type>
-   <isStart>false</isStart>
-   <port>
-    <name>refclk</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>clk</role>
-   </port>
-  </interface>
-  <interface name="reset" kind="reset_sink" version="19.4">
-   <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
-   <assignment>
-    <name>ui.blockdiagram.direction</name>
-    <value>input</value>
-   </assignment>
-   <parameter name="associatedClock">
-    <type>java.lang.String</type>
-    <value></value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="synchronousEdges">
-    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
-    <value>NONE</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="deviceFamily">
-    <type>java.lang.String</type>
-    <value>UNKNOWN</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <parameter name="generateLegacySim">
-    <type>boolean</type>
-    <value>false</value>
-    <derived>false</derived>
-    <enabled>true</enabled>
-    <visible>true</visible>
-    <valid>true</valid>
-   </parameter>
-   <type>reset</type>
-   <isStart>false</isStart>
-   <port>
-    <name>rst</name>
-    <direction>Input</direction>
-    <width>1</width>
-    <role>reset</role>
-   </port>
-  </interface>
- </module>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>altera_generic_component</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype></subtype>
-  <displayName>Generic Component</displayName>
-  <version>1.0</version>
- </plugin>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>conduit_end</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Conduit</displayName>
-  <version>19.4</version>
- </plugin>
- <plugin>
-  <instanceCount>2</instanceCount>
-  <name>clock_source</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Clock Output</displayName>
-  <version>19.4</version>
- </plugin>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>clock_sink</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Clock Input</displayName>
-  <version>19.4</version>
- </plugin>
- <plugin>
-  <instanceCount>1</instanceCount>
-  <name>reset_sink</name>
-  <type>com.altera.entityinterfaces.IElementClass</type>
-  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
-  <displayName>Reset Input</displayName>
-  <version>19.4</version>
- </plugin>
- <reportVersion>19.4 64</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.spd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.spd
deleted file mode 100644
index b608fcd2162b6a2f76eb2eebba9f4d25b77e36d0..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.spd
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<simPackage>
- <file
-   path="altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo"
-   type="VERILOG"
-   library="altera_iopll_180" />
- <file
-   path="sim/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"
-   type="VHDL"
-   library="ip_arria10_e1sg_jesd204b_rx_core_pll"
-   hasInlineConfiguration="true" />
- <topLevel
-   name="ip_arria10_e1sg_jesd204b_rx_core_pll.ip_arria10_e1sg_jesd204b_rx_core_pll" />
- <deviceFamily name="arria10" />
-</simPackage>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.xml b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.xml
deleted file mode 100644
index 4757f19d5e624e9880356180f7ceb6f00e8e4394..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.xml
+++ /dev/null
@@ -1,661 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2020.11.26.17:23:40"
- outputDirectory="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/">
- <perimeter>
-  <parameter
-     name="AUTO_GENERATION_ID"
-     type="Integer"
-     defaultValue="0"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_UNIQUE_ID"
-     type="String"
-     defaultValue=""
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_DEVICE_FAMILY"
-     type="String"
-     defaultValue="Arria 10"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_DEVICE"
-     type="String"
-     defaultValue="10AX115U2F45E1SG"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_DEVICE_SPEEDGRADE"
-     type="String"
-     defaultValue="1"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_REFCLK_CLOCK_RATE"
-     type="Long"
-     defaultValue="-1"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_REFCLK_CLOCK_DOMAIN"
-     type="Integer"
-     defaultValue="-1"
-     onHdl="0"
-     affectsHdl="1" />
-  <parameter
-     name="AUTO_REFCLK_RESET_DOMAIN"
-     type="Integer"
-     defaultValue="-1"
-     onHdl="0"
-     affectsHdl="1" />
-  <interface name="locked" kind="conduit" start="0">
-   <property name="associatedClock" value="" />
-   <property name="associatedReset" value="" />
-   <property name="prSafe" value="false" />
-   <port name="locked_export" direction="output" role="export" width="1" />
-  </interface>
-  <interface name="outclk0" kind="clock" start="1">
-   <property name="associatedDirectClock" value="" />
-   <property name="clockRate" value="100000000" />
-   <property name="clockRateKnown" value="true" />
-   <property name="externallyDriven" value="false" />
-   <property name="ptfSchematicName" value="" />
-   <port name="outclk0_clk" direction="output" role="clk" width="1" />
-  </interface>
-  <interface name="outclk1" kind="clock" start="1">
-   <property name="associatedDirectClock" value="" />
-   <property name="clockRate" value="100000000" />
-   <property name="clockRateKnown" value="true" />
-   <property name="externallyDriven" value="false" />
-   <property name="ptfSchematicName" value="" />
-   <port name="outclk1_clk" direction="output" role="clk" width="1" />
-  </interface>
-  <interface name="refclk" kind="clock" start="0">
-   <property name="clockRate" value="100000000" />
-   <property name="externallyDriven" value="false" />
-   <property name="ptfSchematicName" value="" />
-   <port name="refclk_clk" direction="input" role="clk" width="1" />
-  </interface>
-  <interface name="reset" kind="reset" start="0">
-   <property name="associatedClock" value="" />
-   <property name="synchronousEdges" value="NONE" />
-   <port name="reset_reset" direction="input" role="reset" width="1" />
-  </interface>
- </perimeter>
- <entity
-   kind="ip_arria10_e1sg_jesd204b_rx_core_pll"
-   version="1.0"
-   name="ip_arria10_e1sg_jesd204b_rx_core_pll">
-  <parameter name="AUTO_REFCLK_CLOCK_DOMAIN" value="-1" />
-  <parameter name="AUTO_GENERATION_ID" value="0" />
-  <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
-  <parameter name="AUTO_UNIQUE_ID" value="" />
-  <parameter name="AUTO_REFCLK_RESET_DOMAIN" value="-1" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
-  <generatedFiles>
-   <file
-       path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"
-       attributes="CONTAINS_INLINE_CONFIGURATION" />
-  </generatedFiles>
-  <childGeneratedFiles>
-   <file
-       path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"
-       attributes="CONTAINS_INLINE_CONFIGURATION" />
-  </childGeneratedFiles>
-  <sourceFiles>
-   <file
-       path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys" />
-  </sourceFiles>
-  <childSourceFiles/>
-  <messages>
-   <message level="Info" culprit="ip_arria10_e1sg_jesd204b_rx_core_pll">"Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"</message>
-   <message level="Info" culprit="ip_arria10_e1sg_jesd204b_rx_core_pll">"Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"</message>
-  </messages>
- </entity>
- <entity
-   kind="altera_generic_component"
-   version="1.0"
-   name="ip_arria10_e1sg_jesd204b_rx_core_pll">
-  <parameter name="hlsFile" value="" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
-  <parameter
-     name="defaultBoundary"
-     value="&lt;boundaryDefinition&gt;
-    &lt;interfaces&gt;
-        &lt;interface&gt;
-            &lt;name&gt;locked&lt;/name&gt;
-            &lt;type&gt;conduit&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;locked&lt;/name&gt;
-                    &lt;role&gt;export&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedReset&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;prSafe&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;outclk0&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;true&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;outclk_0&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRateKnown&lt;/key&gt;
-                        &lt;value&gt;true&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;outclk1&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;true&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;outclk_1&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;output&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRateKnown&lt;/key&gt;
-                        &lt;value&gt;true&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;refclk&lt;/name&gt;
-            &lt;type&gt;clock&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;refclk&lt;/name&gt;
-                    &lt;role&gt;clk&lt;/role&gt;
-                    &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;input&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;externallyDriven&lt;/key&gt;
-                        &lt;value&gt;false&lt;/value&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-        &lt;interface&gt;
-            &lt;name&gt;reset&lt;/name&gt;
-            &lt;type&gt;reset&lt;/type&gt;
-            &lt;isStart&gt;false&lt;/isStart&gt;
-            &lt;ports&gt;
-                &lt;port&gt;
-                    &lt;name&gt;rst&lt;/name&gt;
-                    &lt;role&gt;reset&lt;/role&gt;
-                    &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;1&lt;/width&gt;
-                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                &lt;/port&gt;
-            &lt;/ports&gt;
-            &lt;assignments&gt;
-                &lt;assignmentValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                        &lt;value&gt;input&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/assignmentValueMap&gt;
-            &lt;/assignments&gt;
-            &lt;parameters&gt;
-                &lt;parameterValueMap&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;associatedClock&lt;/key&gt;
-                    &lt;/entry&gt;
-                    &lt;entry&gt;
-                        &lt;key&gt;synchronousEdges&lt;/key&gt;
-                        &lt;value&gt;NONE&lt;/value&gt;
-                    &lt;/entry&gt;
-                &lt;/parameterValueMap&gt;
-            &lt;/parameters&gt;
-        &lt;/interface&gt;
-    &lt;/interfaces&gt;
-&lt;/boundaryDefinition&gt;" />
-  <parameter name="system_info_device_speed_grade" value="1" />
-  <parameter
-     name="componentDefinition"
-     value="&lt;componentDefinition&gt;
-    &lt;boundary&gt;
-        &lt;interfaces&gt;
-            &lt;interface&gt;
-                &lt;name&gt;locked&lt;/name&gt;
-                &lt;type&gt;conduit&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;locked&lt;/name&gt;
-                        &lt;role&gt;export&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedReset&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;prSafe&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;outclk0&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;true&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;outclk_0&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRateKnown&lt;/key&gt;
-                            &lt;value&gt;true&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;outclk1&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;true&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;outclk_1&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Output&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;output&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedDirectClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRateKnown&lt;/key&gt;
-                            &lt;value&gt;true&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;refclk&lt;/name&gt;
-                &lt;type&gt;clock&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;refclk&lt;/name&gt;
-                        &lt;role&gt;clk&lt;/role&gt;
-                        &lt;direction&gt;Input&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;input&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;clockRate&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;externallyDriven&lt;/key&gt;
-                            &lt;value&gt;false&lt;/value&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-            &lt;interface&gt;
-                &lt;name&gt;reset&lt;/name&gt;
-                &lt;type&gt;reset&lt;/type&gt;
-                &lt;isStart&gt;false&lt;/isStart&gt;
-                &lt;ports&gt;
-                    &lt;port&gt;
-                        &lt;name&gt;rst&lt;/name&gt;
-                        &lt;role&gt;reset&lt;/role&gt;
-                        &lt;direction&gt;Input&lt;/direction&gt;
-                        &lt;width&gt;1&lt;/width&gt;
-                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
-                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
-                    &lt;/port&gt;
-                &lt;/ports&gt;
-                &lt;assignments&gt;
-                    &lt;assignmentValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;ui.blockdiagram.direction&lt;/key&gt;
-                            &lt;value&gt;input&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/assignmentValueMap&gt;
-                &lt;/assignments&gt;
-                &lt;parameters&gt;
-                    &lt;parameterValueMap&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;associatedClock&lt;/key&gt;
-                        &lt;/entry&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;synchronousEdges&lt;/key&gt;
-                            &lt;value&gt;NONE&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/parameterValueMap&gt;
-                &lt;/parameters&gt;
-            &lt;/interface&gt;
-        &lt;/interfaces&gt;
-    &lt;/boundary&gt;
-    &lt;originalModuleInfo&gt;
-        &lt;className&gt;altera_iopll&lt;/className&gt;
-        &lt;version&gt;19.3.0&lt;/version&gt;
-        &lt;displayName&gt;IOPLL Intel FPGA IP&lt;/displayName&gt;
-    &lt;/originalModuleInfo&gt;
-    &lt;systemInfoParameterDescriptors&gt;
-        &lt;descriptors&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_component&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_family&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE_FAMILY&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_info_device_speed_grade&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfotype&gt;DEVICE_SPEEDGRADE&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-            &lt;descriptor&gt;
-                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
-                &lt;parameterName&gt;system_part_trait_speed_grade&lt;/parameterName&gt;
-                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
-                &lt;systemInfoArgs&gt;DEVICE_SPEEDGRADE&lt;/systemInfoArgs&gt;
-                &lt;systemInfotype&gt;PART_TRAIT&lt;/systemInfotype&gt;
-            &lt;/descriptor&gt;
-        &lt;/descriptors&gt;
-    &lt;/systemInfoParameterDescriptors&gt;
-    &lt;systemInfos&gt;
-        &lt;connPtSystemInfos&gt;
-            &lt;entry&gt;
-                &lt;key&gt;outclk0&lt;/key&gt;
-                &lt;value&gt;
-                    &lt;connectionPointName&gt;outclk0&lt;/connectionPointName&gt;
-                    &lt;suppliedSystemInfos&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/suppliedSystemInfos&gt;
-                    &lt;consumedSystemInfos/&gt;
-                &lt;/value&gt;
-            &lt;/entry&gt;
-            &lt;entry&gt;
-                &lt;key&gt;outclk1&lt;/key&gt;
-                &lt;value&gt;
-                    &lt;connectionPointName&gt;outclk1&lt;/connectionPointName&gt;
-                    &lt;suppliedSystemInfos&gt;
-                        &lt;entry&gt;
-                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                            &lt;value&gt;100000000&lt;/value&gt;
-                        &lt;/entry&gt;
-                    &lt;/suppliedSystemInfos&gt;
-                    &lt;consumedSystemInfos/&gt;
-                &lt;/value&gt;
-            &lt;/entry&gt;
-        &lt;/connPtSystemInfos&gt;
-    &lt;/systemInfos&gt;
-&lt;/componentDefinition&gt;" />
-  <parameter name="logicalView" value="ip_arria10_e1sg_jesd204b_rx_core_pll.ip" />
-  <parameter
-     name="moduleAssignmentDefinition"
-     value="&lt;assignmentDefinition&gt;
-    &lt;assignmentValueMap&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.compatible&lt;/key&gt;
-            &lt;value&gt;altr,pll&lt;/value&gt;
-        &lt;/entry&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.group&lt;/key&gt;
-            &lt;value&gt;clock&lt;/value&gt;
-        &lt;/entry&gt;
-        &lt;entry&gt;
-            &lt;key&gt;embeddedsw.dts.vendor&lt;/key&gt;
-            &lt;value&gt;altr&lt;/value&gt;
-        &lt;/entry&gt;
-    &lt;/assignmentValueMap&gt;
-&lt;/assignmentDefinition&gt;" />
-  <parameter name="svInterfaceDefinition" value="" />
-  <parameter name="system_part_trait_speed_grade" value="1" />
-  <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
-  <parameter name="system_info_device_component" value="10AX115U2F45E1SG" />
-  <parameter name="system_info_device_family" value="Arria 10" />
-  <parameter
-     name="generationInfoDefinition"
-     value="&lt;generationInfoDefinition&gt;
-    &lt;hdlLibraryName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/hdlLibraryName&gt;
-    &lt;fileSets&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-        &lt;fileSet&gt;
-            &lt;fileSetName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetName&gt;
-            &lt;fileSetFixedName&gt;ip_arria10_e1sg_jesd204b_rx_core_pll&lt;/fileSetFixedName&gt;
-            &lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
-            &lt;fileSetFiles/&gt;
-        &lt;/fileSet&gt;
-    &lt;/fileSets&gt;
-&lt;/generationInfoDefinition&gt;" />
-  <generatedFiles/>
-  <childGeneratedFiles/>
-  <sourceFiles/>
-  <childSourceFiles/>
-  <instantiator instantiator="ip_arria10_e1sg_jesd204b_rx_core_pll" as="iopll_0" />
-  <messages>
-   <message level="Info" culprit="ip_arria10_e1sg_jesd204b_rx_core_pll">"Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"</message>
-  </messages>
- </entity>
-</deploy>
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_bb.v b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_bb.v
deleted file mode 100644
index 1ee7dfa498e1fac20050b89400550e3fbd0a8912..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_bb.v
+++ /dev/null
@@ -1,9 +0,0 @@
-module ip_arria10_e1sg_jesd204b_rx_core_pll (
-		output wire  locked_export, //  locked.export
-		output wire  outclk0_clk,   // outclk0.clk
-		output wire  outclk1_clk,   // outclk1.clk
-		input  wire  refclk_clk,    //  refclk.clk
-		input  wire  reset_reset    //   reset.reset
-	);
-endmodule
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation.rpt b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation.rpt
deleted file mode 100644
index 841bbc8929fd252f5afff2fbbe8cc0bc86a94dbe..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation.rpt
+++ /dev/null
@@ -1,35 +0,0 @@
-Info: Generated by version: 19.4 build 64
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys --block-symbol-file --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll --family="Arria 10" --part=10AX115U2F45E1SG
-Progress: Loading jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys
-Progress: Reading input file
-Progress: Adding iopll_0 [altera_generic_component 1.0]
-Progress: Parameterizing module iopll_0
-Progress: Building connections
-Progress: Parameterizing connections
-Progress: Validating
-Progress: Done reading input file
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info: 
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys --synthesis=VHDL --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll --family="Arria 10" --part=10AX115U2F45E1SG
-Progress: Loading jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys
-Progress: Reading input file
-Progress: Adding iopll_0 [altera_generic_component 1.0]
-Progress: Parameterizing module iopll_0
-Progress: Building connections
-Progress: Parameterizing connections
-Progress: Validating
-Progress: Done reading input file
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Transforming system: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Naming system components in system: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Processing generation queue"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: Done "ip_arria10_e1sg_jesd204b_rx_core_pll" with 2 modules, 1 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core Documentation
-Info: No documentation filesets were found for components in ip_arria10_e1sg_jesd204b_rx_core_pll. No files generated.
-Info: Finished: Generate IP Core Documentation
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation_previous.rpt b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation_previous.rpt
deleted file mode 100644
index 0878d48afddfa15e972d7f77a498a039b79f3b1c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_generation_previous.rpt
+++ /dev/null
@@ -1,21 +0,0 @@
-Info: Generated by version: 19.4 build 64
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.ip --block-symbol-file --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll --family="Arria 10" --part=10AX115U2F45E1SG
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll.core_pll: Able to implement PLL with user settings
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info: 
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.ip --synthesis=VHDL --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll --family="Arria 10" --part=10AX115U2F45E1SG
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll.core_pll: Able to implement PLL with user settings
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Transforming system: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Naming system components in system: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Processing generation queue"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Generating: ip_arria10_e1sg_jesd204b_rx_core_pll"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: "Generating: ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_1930_acf6m3q"
-Info: ip_arria10_e1sg_jesd204b_rx_core_pll: Done "ip_arria10_e1sg_jesd204b_rx_core_pll" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core Documentation
-Info: No documentation filesets were found for components in ip_arria10_e1sg_jesd204b_rx_core_pll. No files generated.
-Info: Finished: Generate IP Core Documentation
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.v b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.v
deleted file mode 100644
index 4abbfc97c777310b6c65c1b3bac694d3fd040347..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.v
+++ /dev/null
@@ -1,8 +0,0 @@
-	ip_arria10_e1sg_jesd204b_rx_core_pll u0 (
-		.locked_export (_connected_to_locked_export_), //  output,  width = 1,  locked.export
-		.outclk0_clk   (_connected_to_outclk0_clk_),   //  output,  width = 1, outclk0.clk
-		.outclk1_clk   (_connected_to_outclk1_clk_),   //  output,  width = 1, outclk1.clk
-		.refclk_clk    (_connected_to_refclk_clk_),    //   input,  width = 1,  refclk.clk
-		.reset_reset   (_connected_to_reset_reset_)    //   input,  width = 1,   reset.reset
-	);
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.vhd
deleted file mode 100644
index 10de088f9d15a6e655b7ba451420bb20beb84b37..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll_inst.vhd
+++ /dev/null
@@ -1,19 +0,0 @@
-	component ip_arria10_e1sg_jesd204b_rx_core_pll is
-		port (
-			locked_export : out std_logic;        -- export
-			outclk0_clk   : out std_logic;        -- clk
-			outclk1_clk   : out std_logic;        -- clk
-			refclk_clk    : in  std_logic := 'X'; -- clk
-			reset_reset   : in  std_logic := 'X'  -- reset
-		);
-	end component ip_arria10_e1sg_jesd204b_rx_core_pll;
-
-	u0 : component ip_arria10_e1sg_jesd204b_rx_core_pll
-		port map (
-			locked_export => CONNECTED_TO_locked_export, --  locked.export
-			outclk0_clk   => CONNECTED_TO_outclk0_clk,   -- outclk0.clk
-			outclk1_clk   => CONNECTED_TO_outclk1_clk,   -- outclk1.clk
-			refclk_clk    => CONNECTED_TO_refclk_clk,    --  refclk.clk
-			reset_reset   => CONNECTED_TO_reset_reset    --   reset.reset
-		);
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/modelsim_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/modelsim_files.tcl
deleted file mode 100644
index f35ab45a026dda7a1348f384795263b23e41571e..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/modelsim_files.tcl
+++ /dev/null
@@ -1,66 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_design_libraries {} {
-    set libraries [dict create]
-    dict set libraries altera_iopll_180                     1
-    dict set libraries ip_arria10_e1sg_jesd204b_rx_core_pll 1
-    return $libraries
-  }
-  
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [list]
-    lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo"]\"  -work altera_iopll_180"
-    lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"]\"  -work ip_arria10_e1sg_jesd204b_rx_core_pll"                               
-    return $design_files
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-  proc normalize_path {FILEPATH} {
-      if {[catch { package require fileutil } err]} { 
-          return $FILEPATH 
-      } 
-      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
-      if {[file pathtype $FILEPATH] eq "relative"} { 
-          set path [fileutil::relative [pwd] $path] 
-      } 
-      return $path 
-  } 
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/ncsim_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/ncsim_files.tcl
deleted file mode 100644
index c5b9cd7375324a4baa633f7ba58dd193d1ebcab1..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/ncsim_files.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_design_libraries {} {
-    set libraries [dict create]
-    dict set libraries altera_iopll_180                     1
-    dict set libraries ip_arria10_e1sg_jesd204b_rx_core_pll 1
-    return $libraries
-  }
-  
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [list]
-    lappend design_files "ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo\"  -work altera_iopll_180 -cdslib  ./cds_libs/altera_iopll_180.cds.lib"
-    lappend design_files "ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd\"  -work ip_arria10_e1sg_jesd204b_rx_core_pll"                                                                       
-    return $design_files
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/riviera_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/riviera_files.tcl
deleted file mode 100644
index 18c2c88d2bd64c0c6a532389c6dd6c32f8574994..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/riviera_files.tcl
+++ /dev/null
@@ -1,66 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_design_libraries {} {
-    set libraries [dict create]
-    dict set libraries altera_iopll_180                     1
-    dict set libraries ip_arria10_e1sg_jesd204b_rx_core_pll 1
-    return $libraries
-  }
-  
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [list]
-    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo"]\"  -work altera_iopll_180"
-    lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd"]\"  -work ip_arria10_e1sg_jesd204b_rx_core_pll"                                     
-    return $design_files
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-  proc normalize_path {FILEPATH} {
-      if {[catch { package require fileutil } err]} { 
-          return $FILEPATH 
-      } 
-      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
-      if {[file pathtype $FILEPATH] eq "relative"} { 
-          set path [fileutil::relative [pwd] $path] 
-      } 
-      return $path 
-  } 
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcs_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcs_files.tcl
deleted file mode 100644
index b4489707a4650098e878320682d5fde942333650..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcs_files.tcl
+++ /dev/null
@@ -1,47 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {QSYS_SIMDIR} {
-    set design_files [dict create]
-    error "Skipping VCS script generation since VHDL file $QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd is required for simulation"
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcsmx_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcsmx_files.tcl
deleted file mode 100644
index 845ae01b9ec3a1006d89badec938ff04e931e651..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/vcsmx_files.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_design_libraries {} {
-    set libraries [dict create]
-    dict set libraries altera_iopll_180                     1
-    dict set libraries ip_arria10_e1sg_jesd204b_rx_core_pll 1
-    return $libraries
-  }
-  
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [list]
-    lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo\"  -work altera_iopll_180"
-    lappend design_files "vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd\"  -work ip_arria10_e1sg_jesd204b_rx_core_pll"                              
-    return $design_files
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/xcelium_files.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/xcelium_files.tcl
deleted file mode 100644
index e1209870734dbb9bddc7b8d23ce0b09abf9fb823..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/common/xcelium_files.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-namespace eval ip_arria10_e1sg_jesd204b_rx_core_pll {
-  proc get_design_libraries {} {
-    set libraries [dict create]
-    dict set libraries altera_iopll_180                     1
-    dict set libraries ip_arria10_e1sg_jesd204b_rx_core_pll 1
-    return $libraries
-  }
-  
-  proc get_memory_files {QSYS_SIMDIR} {
-    set memory_files [list]
-    return $memory_files
-  }
-  
-  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [dict create]
-    return $design_files
-  }
-  
-  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
-    set design_files [list]
-    lappend design_files "xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo\"  -work altera_iopll_180 -cdslib  ./cds_libs/altera_iopll_180.cds.lib"
-    lappend design_files "xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"$QSYS_SIMDIR/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd\"  -work ip_arria10_e1sg_jesd204b_rx_core_pll"                                                                       
-    return $design_files
-  }
-  
-  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
-    set ELAB_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ELAB_OPTIONS
-  }
-  
-  
-  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
-    set SIM_OPTIONS ""
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $SIM_OPTIONS
-  }
-  
-  
-  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
-    set ENV_VARIABLES [dict create]
-    set LD_LIBRARY_PATH [dict create]
-    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
-    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
-    } else {
-    }
-    return $ENV_VARIABLES
-  }
-  
-  
-}
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
deleted file mode 100644
index 2b1c174b32d69b0ead67b2e95a917d6c1918520c..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/sim/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
+++ /dev/null
@@ -1,44 +0,0 @@
--- ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
-
--- Generated using ACDS version 18.0 219
-
-library IEEE;
-library altera_iopll_180;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity ip_arria10_e1sg_jesd204b_rx_core_pll is
-	port (
-		locked   : out std_logic;        --  locked.export
-		outclk_0 : out std_logic;        -- outclk0.clk
-		outclk_1 : out std_logic;        -- outclk1.clk
-		refclk   : in  std_logic := '0'; --  refclk.clk
-		rst      : in  std_logic := '0'  --   reset.reset
-	);
-end entity ip_arria10_e1sg_jesd204b_rx_core_pll;
-
-architecture rtl of ip_arria10_e1sg_jesd204b_rx_core_pll is
-	component ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama_cmp is
-		port (
-			rst      : in  std_logic := 'X'; -- reset
-			refclk   : in  std_logic := 'X'; -- clk
-			locked   : out std_logic;        -- export
-			outclk_0 : out std_logic;        -- clk
-			outclk_1 : out std_logic         -- clk
-		);
-	end component ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama_cmp;
-
-	for core_pll : ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama_cmp
-		use entity altera_iopll_180.ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama;
-begin
-
-	core_pll : component ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama_cmp
-		port map (
-			rst      => rst,      --   reset.reset
-			refclk   => refclk,   --  refclk.clk
-			locked   => locked,   --  locked.export
-			outclk_0 => outclk_0, -- outclk0.clk
-			outclk_1 => outclk_1  -- outclk1.clk
-		);
-
-end architecture rtl; -- of ip_arria10_e1sg_jesd204b_rx_core_pll
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
deleted file mode 100644
index 996de9fad70c723577ed7cfbe555670982510a4a..0000000000000000000000000000000000000000
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll/synth/ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
+++ /dev/null
@@ -1,44 +0,0 @@
--- ip_arria10_e1sg_jesd204b_rx_core_pll.vhd
-
--- Generated using ACDS version 19.4 64
-
-library IEEE;
-library ip_arria10_e1sg_jesd204b_rx_core_pll;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity ip_arria10_e1sg_jesd204b_rx_core_pll is
-	port (
-		locked_export : out std_logic;        --  locked.export
-		outclk0_clk   : out std_logic;        -- outclk0.clk
-		outclk1_clk   : out std_logic;        -- outclk1.clk
-		refclk_clk    : in  std_logic := '0'; --  refclk.clk
-		reset_reset   : in  std_logic := '0'  --   reset.reset
-	);
-end entity ip_arria10_e1sg_jesd204b_rx_core_pll;
-
-architecture rtl of ip_arria10_e1sg_jesd204b_rx_core_pll is
-	component ip_arria10_e1sg_jesd204b_rx_core_pll_cmp is
-		port (
-			locked   : out std_logic;        -- export
-			outclk_0 : out std_logic;        -- clk
-			outclk_1 : out std_logic;        -- clk
-			refclk   : in  std_logic := 'X'; -- clk
-			rst      : in  std_logic := 'X'  -- reset
-		);
-	end component ip_arria10_e1sg_jesd204b_rx_core_pll_cmp;
-
-	for iopll_0 : ip_arria10_e1sg_jesd204b_rx_core_pll_cmp
-		use entity ip_arria10_e1sg_jesd204b_rx_core_pll.ip_arria10_e1sg_jesd204b_rx_core_pll;
-begin
-
-	iopll_0 : component ip_arria10_e1sg_jesd204b_rx_core_pll_cmp
-		port map (
-			locked   => locked_export, --  locked.export
-			outclk_0 => outclk0_clk,   -- outclk0.clk
-			outclk_1 => outclk1_clk,   -- outclk1.clk
-			refclk   => refclk_clk,    --  refclk.clk
-			rst      => reset_reset    --   reset.reset
-		);
-
-end architecture rtl; -- of ip_arria10_e1sg_jesd204b_rx_core_pll
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.ip b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip
similarity index 99%
rename from libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.ip
rename to libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip
index 267e0a1000d74d639697a436fe7cee9ae59eb8d8..dd2400e45d53457aaefcd0a502be71439a052188 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.ip
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip
@@ -1,7 +1,7 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>Intel Corporation</ipxact:vendor>
-  <ipxact:library>ip_arria10_e1sg_jesd204b_rx_core_pll</ipxact:library>
+  <ipxact:library>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</ipxact:library>
   <ipxact:name>core_pll</ipxact:name>
   <ipxact:version>19.3.0</ipxact:version>
   <ipxact:busInterfaces>
@@ -70,7 +70,7 @@
         <ipxact:parameter parameterId="clockRate" type="longint">
           <ipxact:name>clockRate</ipxact:name>
           <ipxact:displayName>Clock rate</ipxact:displayName>
-          <ipxact:value>100000000</ipxact:value>
+          <ipxact:value>200000000</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="externallyDriven" type="bit">
           <ipxact:name>externallyDriven</ipxact:name>
@@ -226,7 +226,7 @@
         <ipxact:parameter parameterId="clockRate" type="longint">
           <ipxact:name>clockRate</ipxact:name>
           <ipxact:displayName>Clock rate</ipxact:displayName>
-          <ipxact:value>100000000</ipxact:value>
+          <ipxact:value>200000000</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="clockRateKnown" type="bit">
           <ipxact:name>clockRateKnown</ipxact:name>
@@ -345,7 +345,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>Intel Corporation</ipxact:vendor>
-      <ipxact:library>ip_arria10_e1sg_jesd204b_rx_core_pll</ipxact:library>
+      <ipxact:library>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</ipxact:library>
       <ipxact:name>altera_iopll</ipxact:name>
       <ipxact:version>19.3.0</ipxact:version>
     </altera:entity_info>
@@ -544,12 +544,12 @@
         <ipxact:parameter parameterId="gui_reference_clock_frequency" type="real">
           <ipxact:name>gui_reference_clock_frequency</ipxact:name>
           <ipxact:displayName>Reference Clock Frequency</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_reference_clock_frequency_ps" type="real">
           <ipxact:name>gui_reference_clock_frequency_ps</ipxact:name>
           <ipxact:displayName>Reference Clock Frequency</ipxact:displayName>
-          <ipxact:value>10000.0</ipxact:value>
+          <ipxact:value>5000.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_use_coreclk" type="bit">
           <ipxact:name>gui_use_coreclk</ipxact:name>
@@ -1074,7 +1074,7 @@
         <ipxact:parameter parameterId="gui_output_clock_frequency1" type="real">
           <ipxact:name>gui_output_clock_frequency1</ipxact:name>
           <ipxact:displayName>Desired Frequency</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_output_clock_frequency2" type="real">
           <ipxact:name>gui_output_clock_frequency2</ipxact:name>
@@ -1164,7 +1164,7 @@
         <ipxact:parameter parameterId="gui_output_clock_frequency_ps1" type="real">
           <ipxact:name>gui_output_clock_frequency_ps1</ipxact:name>
           <ipxact:displayName>Desired Frequency</ipxact:displayName>
-          <ipxact:value>10000.0</ipxact:value>
+          <ipxact:value>5000.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_output_clock_frequency_ps2" type="real">
           <ipxact:name>gui_output_clock_frequency_ps2</ipxact:name>
@@ -1254,7 +1254,7 @@
         <ipxact:parameter parameterId="gui_actual_output_clock_frequency1" type="string">
           <ipxact:name>gui_actual_output_clock_frequency1</ipxact:name>
           <ipxact:displayName>Actual Frequency</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_output_clock_frequency2" type="string">
           <ipxact:name>gui_actual_output_clock_frequency2</ipxact:name>
@@ -1339,12 +1339,12 @@
         <ipxact:parameter parameterId="gui_actual_output_clock_frequency_range0" type="string">
           <ipxact:name>gui_actual_output_clock_frequency_range0</ipxact:name>
           <ipxact:displayName>Legal Frequencies</ipxact:displayName>
-          <ipxact:value>99.305556,99.333333,99.375,100.0,100.666667,100.714286</ipxact:value>
+          <ipxact:value>99.595142,99.607843,99.649123,100.0,100.350877,100.392157</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_output_clock_frequency_range1" type="string">
           <ipxact:name>gui_actual_output_clock_frequency_range1</ipxact:name>
           <ipxact:displayName>Legal Frequencies</ipxact:displayName>
-          <ipxact:value>93.333333,93.75,94.117647,100.0,106.666667,107.142857</ipxact:value>
+          <ipxact:value>183.333333,185.714286,187.5,200.0,214.285714,216.666667</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_output_clock_frequency_range2" type="string">
           <ipxact:name>gui_actual_output_clock_frequency_range2</ipxact:name>
@@ -1789,12 +1789,12 @@
         <ipxact:parameter parameterId="gui_actual_phase_shift_range0" type="string">
           <ipxact:name>gui_actual_phase_shift_range0</ipxact:name>
           <ipxact:displayName>Legal Phase Shifts</ipxact:displayName>
-          <ipxact:value>0.0,78.1,83.3,89.3,96.2,104.2</ipxact:value>
+          <ipxact:value>0.0,78.1,89.3,104.2,125.0,156.2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_phase_shift_range1" type="string">
           <ipxact:name>gui_actual_phase_shift_range1</ipxact:name>
           <ipxact:displayName>Legal Phase Shifts</ipxact:displayName>
-          <ipxact:value>0.0,78.1,83.3,89.3,96.2,104.2</ipxact:value>
+          <ipxact:value>0.0,78.1,89.3,104.2,125.0,156.2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_phase_shift_range2" type="string">
           <ipxact:name>gui_actual_phase_shift_range2</ipxact:name>
@@ -1969,12 +1969,12 @@
         <ipxact:parameter parameterId="gui_actual_phase_shift_deg_range0" type="string">
           <ipxact:name>gui_actual_phase_shift_deg_range0</ipxact:name>
           <ipxact:displayName>Legal Phase Shifts</ipxact:displayName>
-          <ipxact:value>0.0,2.8,3.0,3.2,3.5,3.8</ipxact:value>
+          <ipxact:value>0.0,2.8,3.2,3.8,4.5,5.6</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_phase_shift_deg_range1" type="string">
           <ipxact:name>gui_actual_phase_shift_deg_range1</ipxact:name>
           <ipxact:displayName>Legal Phase Shifts</ipxact:displayName>
-          <ipxact:value>0.0,2.8,3.0,3.2,3.5,3.8</ipxact:value>
+          <ipxact:value>0.0,5.6,6.4,7.5,9.0,11.2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_phase_shift_deg_range2" type="string">
           <ipxact:name>gui_actual_phase_shift_deg_range2</ipxact:name>
@@ -2239,12 +2239,12 @@
         <ipxact:parameter parameterId="gui_actual_duty_cycle_range0" type="string">
           <ipxact:name>gui_actual_duty_cycle_range0</ipxact:name>
           <ipxact:displayName>Legal Duty Cycles</ipxact:displayName>
-          <ipxact:value>46.43,46.67,46.88,50.0,53.12,53.33</ipxact:value>
+          <ipxact:value>45.83,46.43,46.88,50.0,53.12,53.57</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_duty_cycle_range1" type="string">
           <ipxact:name>gui_actual_duty_cycle_range1</ipxact:name>
           <ipxact:displayName>Legal Duty Cycles</ipxact:displayName>
-          <ipxact:value>46.43,46.67,46.88,50.0,53.12,53.33</ipxact:value>
+          <ipxact:value>41.67,42.86,43.75,50.0,56.25,57.14</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="gui_actual_duty_cycle_range2" type="string">
           <ipxact:name>gui_actual_duty_cycle_range2</ipxact:name>
@@ -2334,7 +2334,7 @@
         <ipxact:parameter parameterId="parameterTable_values" type="string">
           <ipxact:name>parameterTable_values</ipxact:name>
           <ipxact:displayName>Parameter Values</ipxact:displayName>
-          <ipxact:value>6,1,600.0 MHz,6,6,1,1,1,1,1,1,1,false,3,3,false,false,256,256,false,true,3,3,256,256,256,256,256,256,256,3,3,256,256,256,256,256,256,256,false,false,false,false,false,false,false,false,false,false,false,true,true,true,true,true,true,true,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting14,pll_bw_res_setting3</ipxact:value>
+          <ipxact:value>4,1,800.0 MHz,8,4,1,1,1,1,1,1,1,false,2,2,false,false,256,256,false,true,4,2,256,256,256,256,256,256,256,4,2,256,256,256,256,256,256,256,false,false,false,false,false,false,false,false,false,false,false,true,true,true,true,true,true,true,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting10,pll_bw_res_setting2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="mifTable_names" type="string">
           <ipxact:name>mifTable_names</ipxact:name>
@@ -2364,7 +2364,7 @@
         <ipxact:parameter parameterId="m_cnt_hi_div" type="int">
           <ipxact:name>m_cnt_hi_div</ipxact:name>
           <ipxact:displayName>m_cnt_hi_div</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="eff_m_cnt" type="int">
           <ipxact:name>eff_m_cnt</ipxact:name>
@@ -2374,7 +2374,7 @@
         <ipxact:parameter parameterId="multiply_factor" type="int">
           <ipxact:name>multiply_factor</ipxact:name>
           <ipxact:displayName>multiply_factor</ipxact:displayName>
-          <ipxact:value>6</ipxact:value>
+          <ipxact:value>4</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="use_core_refclk" type="bit">
           <ipxact:name>use_core_refclk</ipxact:name>
@@ -2384,7 +2384,7 @@
         <ipxact:parameter parameterId="m_cnt_lo_div" type="int">
           <ipxact:name>m_cnt_lo_div</ipxact:name>
           <ipxact:displayName>m_cnt_lo_div</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="n_cnt_hi_div" type="int">
           <ipxact:name>n_cnt_hi_div</ipxact:name>
@@ -2424,12 +2424,12 @@
         <ipxact:parameter parameterId="pll_cp_current" type="string">
           <ipxact:name>pll_cp_current</ipxact:name>
           <ipxact:displayName>pll_cp_current</ipxact:displayName>
-          <ipxact:value>pll_cp_setting14</ipxact:value>
+          <ipxact:value>pll_cp_setting10</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="pll_bwctrl" type="string">
           <ipxact:name>pll_bwctrl</ipxact:name>
           <ipxact:displayName>pll_bwctrl</ipxact:displayName>
-          <ipxact:value>pll_bw_res_setting3</ipxact:value>
+          <ipxact:value>pll_bw_res_setting2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="pll_ripplecap_ctrl" type="string">
           <ipxact:name>pll_ripplecap_ctrl</ipxact:name>
@@ -2449,7 +2449,7 @@
         <ipxact:parameter parameterId="reference_clock_frequency" type="string">
           <ipxact:name>reference_clock_frequency</ipxact:name>
           <ipxact:displayName>reference_clock_frequency</ipxact:displayName>
-          <ipxact:value>100.0 MHz</ipxact:value>
+          <ipxact:value>200.0 MHz</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="pll_fractional_cout" type="int">
           <ipxact:name>pll_fractional_cout</ipxact:name>
@@ -2494,12 +2494,12 @@
         <ipxact:parameter parameterId="pll_output_clk_frequency" type="string">
           <ipxact:name>pll_output_clk_frequency</ipxact:name>
           <ipxact:displayName>pll_output_clk_frequency</ipxact:displayName>
-          <ipxact:value>600.0 MHz</ipxact:value>
+          <ipxact:value>800.0 MHz</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="pll_pfd_frequency" type="string">
           <ipxact:name>pll_pfd_frequency</ipxact:name>
           <ipxact:displayName>pll_pfd_frequency</ipxact:displayName>
-          <ipxact:value>100.0 MHz</ipxact:value>
+          <ipxact:value>200.0 MHz</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="mimic_fbclk_type" type="string">
           <ipxact:name>mimic_fbclk_type</ipxact:name>
@@ -2624,12 +2624,12 @@
         <ipxact:parameter parameterId="c_cnt_hi_div0" type="int">
           <ipxact:name>c_cnt_hi_div0</ipxact:name>
           <ipxact:displayName>c_cnt_hi_div0</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>4</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="c_cnt_hi_div1" type="int">
           <ipxact:name>c_cnt_hi_div1</ipxact:name>
           <ipxact:displayName>c_cnt_hi_div1</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="c_cnt_hi_div2" type="int">
           <ipxact:name>c_cnt_hi_div2</ipxact:name>
@@ -2714,12 +2714,12 @@
         <ipxact:parameter parameterId="c_cnt_lo_div0" type="int">
           <ipxact:name>c_cnt_lo_div0</ipxact:name>
           <ipxact:displayName>c_cnt_lo_div0</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>4</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="c_cnt_lo_div1" type="int">
           <ipxact:name>c_cnt_lo_div1</ipxact:name>
           <ipxact:displayName>c_cnt_lo_div1</ipxact:displayName>
-          <ipxact:value>3</ipxact:value>
+          <ipxact:value>2</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="c_cnt_lo_div2" type="int">
           <ipxact:name>c_cnt_lo_div2</ipxact:name>
@@ -3259,7 +3259,7 @@
         <ipxact:parameter parameterId="output_clock_frequency1" type="string">
           <ipxact:name>output_clock_frequency1</ipxact:name>
           <ipxact:displayName>output_clock_frequency1</ipxact:displayName>
-          <ipxact:value>100.0 MHz</ipxact:value>
+          <ipxact:value>200.0 MHz</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="output_clock_frequency2" type="string">
           <ipxact:name>output_clock_frequency2</ipxact:name>
@@ -3749,7 +3749,7 @@
         <ipxact:parameter parameterId="hp_actual_output_clock_frequency_fp1" type="real">
           <ipxact:name>hp_actual_output_clock_frequency_fp1</ipxact:name>
           <ipxact:displayName>hp_actual_output_clock_frequency_fp1</ipxact:displayName>
-          <ipxact:value>100.0</ipxact:value>
+          <ipxact:value>200.0</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="hp_actual_output_clock_frequency_fp2" type="real">
           <ipxact:name>hp_actual_output_clock_frequency_fp2</ipxact:name>
@@ -4145,7 +4145,7 @@
                 &lt;parameterValueMap&gt;
                     &lt;entry&gt;
                         &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
+                        &lt;value&gt;200000000&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;externallyDriven&lt;/key&gt;
@@ -4268,7 +4268,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;clockRate&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
+                        &lt;value&gt;200000000&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;clockRateKnown&lt;/key&gt;
@@ -4313,7 +4313,7 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;100000000&lt;/value&gt;
+                        &lt;value&gt;200000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/consumedSystemInfos&gt;
             &lt;/value&gt;
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qsys
similarity index 96%
rename from libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys
rename to libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qsys
index 4da24227c31d764dc221fbf068d3b40dfa7c3068..54d51724bd607a1f157b66a1c62b4e59bf8d88c9 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll.qsys
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qsys
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<system name="ip_arria10_e1sg_jesd204b_rx_core_pll">
+<system name="ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz">
  <component
    name="$${FILENAME}"
    displayName="$${FILENAME}"
@@ -10,9 +10,6 @@
    tool="QsysPro" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $system
-   {
-   }
    element iopll_0
    {
       datum _sortIndex
@@ -58,7 +55,7 @@
                 <consumedSystemInfos>
                     <entry>
                         <key>CLOCK_RATE</key>
-                        <value>100000000</value>
+                        <value>200000000</value>
                     </entry>
                 </consumedSystemInfos>
             </value>
@@ -194,7 +191,7 @@
                         </entry>
                         <entry>
                             <key>clockRate</key>
-                            <value>100000000</value>
+                            <value>200000000</value>
                         </entry>
                         <entry>
                             <key>clockRateKnown</key>
@@ -236,7 +233,7 @@
                     <parameterValueMap>
                         <entry>
                             <key>clockRate</key>
-                            <value>100000000</value>
+                            <value>200000000</value>
                         </entry>
                         <entry>
                             <key>externallyDriven</key>
@@ -340,7 +337,7 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>CLOCK_RATE</key>
-                            <value>100000000</value>
+                            <value>200000000</value>
                         </entry>
                     </suppliedSystemInfos>
                     <consumedSystemInfos/>
@@ -462,7 +459,7 @@
                     </entry>
                     <entry>
                         <key>clockRate</key>
-                        <value>100000000</value>
+                        <value>200000000</value>
                     </entry>
                     <entry>
                         <key>clockRateKnown</key>
@@ -504,7 +501,7 @@
                 <parameterValueMap>
                     <entry>
                         <key>clockRate</key>
-                        <value>100000000</value>
+                        <value>200000000</value>
                     </entry>
                     <entry>
                         <key>externallyDriven</key>
@@ -553,30 +550,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>ip_arria10_e1sg_jesd204b_rx_core_pll</hdlLibraryName>
+    <hdlLibraryName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
+            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
+            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetName>
-            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll</fileSetFixedName>
+            <fileSetName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetName>
+            <fileSetFixedName>ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip_arria10_e1sg_jesd204b_rx_core_pll.ip</parameter>
+  <parameter name="logicalView">ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap>
         <entry>
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index 3314adb3fb9c925b007133b02960a759c4555ce4..437a13979ef0e04eb36d85c524e9ddaa900add1d 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -61,7 +61,8 @@ ENTITY tech_jesd204b IS
     g_technology          : NATURAL := c_tech_arria10_e1sg;
     g_nof_streams         : NATURAL := 12;
     g_nof_sync_n          : NATURAL := 12;
-    g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_direction           : STRING  := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_jesd_freq           : STRING  := "200MHz"
   );
   PORT (
     -- JESD204B external signals
@@ -101,7 +102,8 @@ BEGIN
       g_sim                => g_sim,                
       g_nof_streams        => g_nof_streams,      
       g_nof_sync_n         => g_nof_sync_n,        
-      g_direction          => g_direction
+      g_direction          => g_direction,
+      g_jesd_freq          => g_jesd_freq
     )
     PORT MAP(
       jesd204b_refclk      => jesd204b_refclk,   
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
index 49e05c6aa2f7084ad7275c63baf72e1ba99415e2..005c3d19248439476678b4955ef5a36e6801d3f8 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
@@ -39,7 +39,8 @@ ENTITY tech_jesd204b_arria10_e1sg IS
     g_sim                 : BOOLEAN := FALSE;
     g_nof_streams         : NATURAL := 12;
     g_nof_sync_n          : NATURAL := 12;
-    g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_direction           : STRING  := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_jesd_freq           : STRING  := "200MHz"
   );
   PORT (
     -- JESD204B external signals
@@ -78,14 +79,15 @@ BEGIN
     g_sim                => g_sim,                
     g_nof_streams        => g_nof_streams,      
     g_nof_sync_n         => g_nof_sync_n,        
-    g_direction          => g_direction
+    g_direction          => g_direction,
+    g_jesd_freq          => g_jesd_freq
   )
   PORT MAP(
     jesd204b_refclk      => jesd204b_refclk,   
     jesd204b_sysref      => jesd204b_sysref,   
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
-    jesd204b_disable_arr  => jesd204b_disable_arr,
+    jesd204b_disable_arr => jesd204b_disable_arr,
     jesd204b_reset       => jesd204b_reset,
 
     rx_src_out_arr       => rx_src_out_arr,          
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 0008089677c1adf31cc016d385ef235836c9ae56..a2cf74d445cf14a991c12cefb48caf95436e7dec 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -40,7 +40,8 @@ PACKAGE tech_jesd204b_component_pkg IS
     g_sim                 : BOOLEAN := FALSE;
     g_nof_streams         : NATURAL := 1;
     g_nof_sync_n          : NATURAL := 1;
-    g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_direction           : STRING  := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+    g_jesd_freq           : STRING  := "200MHz"
   );
  PORT (
     -- JESD204B external signals