diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index a95cee5c482c81e4a56e7efc4095dc617db1da21..14dfd8a984cda38fe936af12e313163de94bf2e8 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -42,140 +42,11 @@
-- dynamic nof_pkt control. When the nof_pkt control input is used, g_nof_pkt sets
-- the maximum number of packets that can be merged.
-- . the nof_pkt control input is read on completion of the current block. The current
--- working value is kept in r (t_reg). nof_pkt = 0 is ignored.
+-- working value is kept in r (t_reg).
-- . with g_align_at_sync=true the merge can be forced to restart at a snk_in.sync.
---
--- Issues:
---
--- Design steps:
--- A) No flow control
--- . Start with the Gaisler p_comb, p_reg template:
---
--- /----------------------------\
--- | nxt_r r |
--- | /------\ . . |
--- \-->| | . . |
--- snk_in -------->| | ---> p_reg -----*--> src_out
--- snk_out <--------|p_comb| <------------------- src_in
--- \------/ .
--- .
--- snk --> src : latency + 1
---
--- The following signals are registered in r: outputs, internal states. Typically do not yet
--- add pipelining registers, because these are not functional and can be added later using
--- common_pipeline or dp_pipeline components. For the design start with a timing diagram of the
--- input and output for merging e.g. 3 packets. Draw the sop and eop and also draw the case that
--- there is a data invalid gap between packets. There needs to be a packet counter so, also
--- draw this signal.
--- . Using the timing diagram, now assign each of the v fields. Try to keep the implementation
--- for each field seperate, i.e. do not combine multiple fields into one if then else statement.
--- The reason is that keeping each field implementation seperate, makes the code more clear and
--- also eases making modifications later on. Mark the implementation section by a comment line.
--- . Typically use r in the if condition and at the right of the := assignment. Depending only
--- on r for implementing v has the advantage that the order of the code section is not important,
--- i.e. similar as with seperate combinatorial processes. However for some cases it can be
--- beneficial to use v in the condition or in the assignment, e.g. as with v.busy.
--- . If the component will not support flow control, then the snk - src latency may be made
--- > 1. However to prepare for adding flow control later on it is prefered to keep the input -
--- output latency at 1. Keeping the snk - src latency at 1 typically also makes the
--- implementation more clear, because if more latency is needed, then it may be better to
--- partition the function over two or more components. The snk - src latency of 1 is not
--- functional, because the nxt_r with latency 0 also could be used as output. However the
--- registering of outputs can be functional. From digital implementation point of view it is
--- appropriate though to continue with the r outputs and assign these to the entity outputs.
--- . When the architecture HDL implementation looks clean coded then compile it. When it compiles
--- OK commit it.
--- . Next step is to add a test bench. For dp_packet_merge it is beneficial to first also implement
--- the reverse function dp_packet_unmerge, because that allows the test bench to have the same
--- stimuli input counter data also appear as counter data at the output for verification.
--- Furthermore even though the reverse function may not be needed yet in an application it
--- happens quite often that it will become useful in the future.
--- . For the stimuli and verification use the counter data procedures from tb_dp_pkg.vhd. The
--- test bench consists of stimuli --> DUT --> reverse DUT --> verification. First keep data
--- valid active and use nof_pkt > 1. When that works OK, commit the DUT and the test bench.
--- After that try the extreme values for control, i.e. nof_pkt = 0 should yield no output and
--- nof_pkt = 1 should yield output = input. Then add dynamic in_en to get data not valid gaps
--- during and between the packets. Also try dynamic changing of nof_pkt. When that all
--- works commit the VHDL files.
---
--- B) Add flow control using dp_latency_adapter:
---
--- /----------------------------\
--- | nxt_r r |
--- | /------\ . . | /-------\
--- \-->| | . . | |dp |
--- snk_in -------->| | ---> p_reg -----*---->|latency|---> src_out
--- snk_out <--------|p_comb| <---------------------|adapter|<--- src_in
--- . \------/ . \-------/ .
--- . . .
--- . . .
--- . . .
--- RL=1 RL=2 RL=1
---
--- C) Add flow control using dp_hold_input
--- . Adding flow control implies adding dp_hold_input to connect to the snk_in/skn_out and using
--- pend_src_out/hold_src_in instead in p_comb:
---
--- |-----| <---------------------------------------------\
--- | | nxt_r r |
--- | | /------\ . . |
--- | dp | | | . . |
--- snk_in --> |hold | --> pend_src_out --> | | ---> p_reg -----*--> src_out
--- snk_out <-- |input| <-- hold_src_in <-- |p_comb| <------------------- src_in
--- . |-----| . \------/ .
--- . . .
--- RL=1 RL=0 RL=1
---
--- The ready latency (RL) at the input is RL=1. The RL at the output must also be RL=1. The
--- dp_hold_input effectively achieves that the pend_src_out/hold_src_in have RL=0.
--- The snk - src latency of the function is 1, so at the output the RL then becomes RL=1 again.
--- Inside p_comb the v output valid now only get assigned with the pend_src_out valid when
--- src_in.ready='1'. Internally in dp_hold_input the next_src_out.valid = pend_src_out.valid
--- AND src_in.ready, and similar for the sop, eop amd sync. Therefore the p_comb can also use
--- next_src_out instead of pend_src_out in combination with src_in.ready. The advantage of
--- using next_src_out is that it makes the code more compact. The advantange of using
--- pend_src_out and src_in.ready explicitly is that it may make it more clear how src_in.ready
--- is used.
--- . Typically the p_comb can simply pass on src_in to hold_src_in, however it may also control
--- hold_src_in by itself if this function also needs some extra flow control, e.g. to halt or
--- flush the input.
--- . Most components only need to pass on the src_in.xon to hold_src_in.xon. Hence this can be
--- the last statement in p_comb.
--- . In the test bench now also apply the src_in.ready to verify that the component behaves
--- correctly for allways active ready and random ready flow control.
--- . Make a multi-test bench tb_tb_dp_packet_merge to verify different tb settings for the DUT
--- stimuli and add it to the overall DP module tb_tb_tb_dp_backpressure regression test bench.
---
--- D) Potential alternative to add flow control using dp_pipeline
---
--- . This scheme has not been verified yet, but it could work:
---
--- /-----------------------------\
--- | nxt_r r | dp_pipeline_stream
--- | /------\ . . | <--select none or one-->
--- \-->| |---o-> p_reg -----/ ____ /-----\
--- | | | |dp | |dp |
--- snk_in -------->| | \------------------->|pipe|-->|pipe |--> src_out
--- snk_out <--------|p_comb|<-----------------------|line|<--|line |--- src_in
--- . \------/ . |____| |ready| .
--- . RL=0 . \-----/ .
--- RL=1 RL=1 RL=1
---
--- . dp_pipeline_stream = wires or dp_pipeline or dp_pipeline_ready
--- - dp_pipeline pipelines the sosi
--- - dp_pipeline_ready pipelines the siso and also the sosi
--- . without flow control there is no siso, so then dp_pipeline_stream degenerates
--- to common_pipeline.
--- . The nxt_r contains combinatorially (= functionally) already what src_out will become in
--- the next cycle and because it is combinatorially related to the input it preserves the
--- RL=1 (whereas p_reg has RL=2). Leading nxt_r through dp_pipeline includes the flow control
--- to it.
--- . Compared to using dp_hold_input using dp_pipeline costs twice more registers, because
--- dp_pipeline internally has a register stage and p_reg is still needed. Still synthesis
--- may be able to optimize away some redundant registers.
--- . The advantage of this scheme it that it allows designing the function without flow
--- control according to scheme A). Then make nxt_r available instead of r and lead nxt_r
--- through dp_pipeline to register it and to add the flow control.
+-- . Optional flow control dependent on g_use_ready and g_pipeline_ready, see
+-- description of dp_add_flow_control.
+
library IEEE,common_lib;
use IEEE.std_logic_1164.all;
@@ -185,10 +56,12 @@ use work.dp_stream_pkg.all;
entity dp_packet_merge is
generic (
- g_nof_pkt : natural;
- g_align_at_sync : boolean := false;
- g_bsn_increment : natural := 0;
- g_bsn_err_bi : natural := 0 -- bit index (bi) in scr_out.err for snk_in.bsn error
+ g_use_ready : boolean := true;
+ g_pipeline_ready : boolean := false;
+ g_nof_pkt : natural;
+ g_align_at_sync : boolean := false;
+ g_bsn_increment : natural := 0;
+ g_bsn_err_bi : natural := 0 -- bit index (bi) in scr_out.err for snk_in.bsn error
);
port (
rst : in std_logic;
@@ -200,7 +73,7 @@ entity dp_packet_merge is
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
- src_in : in t_dp_siso;
+ src_in : in t_dp_siso := c_dp_siso_rdy;
src_out : out t_dp_sosi
);
end dp_packet_merge;
@@ -217,52 +90,32 @@ architecture rtl of dp_packet_merge is
src_out : t_dp_sosi;
end record;
- constant c_use_dp_latency_adapter : boolean := true; -- when TRUE adjust RL from 2 to 1, else use dp_hold_input to keep RL at 1.
-
signal r, nxt_r : t_reg;
-
- signal dp_latency_adapter_snk_out : t_dp_siso;
- signal dp_latency_adapter_snk_in : t_dp_sosi;
- signal dp_latency_adapter_src_in : t_dp_siso;
- signal dp_latency_adapter_src_out : t_dp_sosi;
begin
- -- Map t_reg outputs to entity outputs
+ -- Map logic function outputs to entity outputs
nof_pkt_out <= TO_UVEC(r.nof_pkt, ceil_log2(g_nof_pkt + 1));
- no_dp_latency_adapter : if c_use_dp_latency_adapter = false generate
- snk_out <= src_in;
- src_out <= r.src_out;
-
- -- can put dp_hold_input here --
- end generate;
-
- gen_dp_latency_adapter : if c_use_dp_latency_adapter = true generate
- snk_out <= dp_latency_adapter_snk_out;
- dp_latency_adapter_snk_in <= r.src_out;
-
- u_dp_latency_adapter : entity work.dp_latency_adapter
+ u_dp_add_flow_control : entity work.dp_add_flow_control
generic map (
- g_in_latency => 2,
- g_out_latency => 1
+ g_use_ready => g_use_ready,
+ g_pipeline_ready => g_pipeline_ready
)
port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dp_latency_adapter_snk_out,
- snk_in => dp_latency_adapter_snk_in,
- -- ST source
- src_in => dp_latency_adapter_src_in,
- src_out => dp_latency_adapter_src_out
- );
+ rst => rst,
+ clk => clk,
- dp_latency_adapter_src_in <= src_in;
- src_out <= dp_latency_adapter_src_out;
- end generate;
+ snk_out => snk_out,
+ snk_in => nxt_r.src_out, -- combinatorial input
+ snk_in_reg => r.src_out, -- registered input
+
+ src_in => src_in,
+ src_out => src_out
+ );
- -- p_reg
+ -- p_reg function state register
r <= nxt_r when rising_edge(clk);
+ -- Logic function
p_comb : process(rst, r, snk_in, nof_pkt)
variable v : t_reg;
begin
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index e930389b8ddff1f06b57caa0a977ae33aac45266..9a8401456e7753a45023be5912ec77afb4eb0af7 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -19,6 +19,7 @@
--
--------------------------------------------------------------------------------
+-- Author: E. Kooistra
-- Purpose: Unmerge each input packet into output packets of length g_pkt_len.
-- Description:
-- . The merged packet length of the snk_in input packets must be an integer
@@ -48,25 +49,8 @@
-- _ _ _ _ _ _
-- src_out.eop ___________|0|_____|1|_____|2|_____|0|_____|1|_____|2|___
--
--- . Flow control.
--- . The component does not add additional snk_out.ready flow control itself,
--- but it can listen to external src_in.ready flow control.
--- - If g_use_src_in_ready = false, then src_in is ignored, so no flow
--- control, else do use flow control by src_in.ready.
--- - If g_use_src_in_ready = true, then g_use_dp_latency_adapter = false
--- determines that the src_in.ready is used combinatorially else the
--- src_in.ready is used registered.
--- . The p_reg increases the ready latency (RL) by 1, because p_comb does
--- not use src_in.ready, instead p_comb drives d.src_out based on the
--- snk_in.sop, eop, valid. Therefore g_use_dp_latency_adapter = true is
--- needed to restore the RL from 2 to 1 for the src_out the output. The
--- alternative is to use a dp_pipeline to register d.src_out in
--- combination with src_in.ready at the input, to keep RL at 1.
--- The p_reg keeps the internal state of the component. With dp_pipeline
--- a separate output register is needed to store src_out. With the
--- dp_latency_adapter a feq register stages are needed to store src_out,
--- but the adantage of dp_latency_adapter is that it also registers the
--- src_in.ready so that may ease timing closure.
+-- . Optional flow control dependent on g_use_ready and g_pipeline_ready, see
+-- description of dp_add_flow_control.
library IEEE,common_lib;
use IEEE.std_logic_1164.all;
@@ -76,11 +60,11 @@ use work.dp_stream_pkg.all;
entity dp_packet_unmerge is
generic (
- g_use_src_in_ready : boolean := false;
- g_use_dp_latency_adapter : boolean := true;
- g_nof_pkt_max : natural := 1; -- Maximum nof packets to unmerge each incoming packet to
- g_pkt_len : natural := 1; -- Length of the unmerged packets
- g_bsn_increment : natural := 0
+ g_use_ready : boolean := true;
+ g_pipeline_ready : boolean := false;
+ g_nof_pkt_max : natural := 1; -- Maximum nof packets to unmerge each incoming packet to
+ g_pkt_len : natural := 1; -- Length of the unmerged packets
+ g_bsn_increment : natural := 0
);
port (
rst : in std_logic;
@@ -89,12 +73,13 @@ entity dp_packet_unmerge is
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
- src_in : in t_dp_siso := c_dp_siso_rst;
+ src_in : in t_dp_siso := c_dp_siso_rdy;
src_out : out t_dp_sosi
);
end dp_packet_unmerge;
architecture rtl of dp_packet_unmerge is
+ -- Internal state of logic function
type t_reg is record
pkt_cnt : natural range 0 to g_nof_pkt_max + 1;
val_cnt : natural range 0 to g_pkt_len + 1;
@@ -106,61 +91,29 @@ architecture rtl of dp_packet_unmerge is
signal r : t_reg;
signal d : t_reg;
- -- Signals for g_use_dp_latency_adapter = true
- signal dp_latency_adapter_snk_out : t_dp_siso;
- signal dp_latency_adapter_snk_in : t_dp_sosi;
- signal dp_latency_adapter_src_in : t_dp_siso;
- signal dp_latency_adapter_src_out : t_dp_sosi;
begin
- -- Map t_reg outputs to entity outputs
- no_flow_control : if g_use_src_in_ready = false generate
- snk_out <= c_dp_siso_rdy;
- src_out <= r.src_out;
- end generate;
-
- gen_use_src_in_ready : if g_use_src_in_ready = true generate
- gen_dp_pipeline : if g_use_dp_latency_adapter = false generate
- u_dp_pipeline : entity work.dp_pipeline
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => d.src_out,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
- end generate;
-
- gen_dp_latency_adapter : if g_use_dp_latency_adapter = true generate
- snk_out <= dp_latency_adapter_snk_out;
- dp_latency_adapter_snk_in <= r.src_out;
-
- u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 2,
- g_out_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dp_latency_adapter_snk_out,
- snk_in => dp_latency_adapter_snk_in,
- -- ST source
- src_in => dp_latency_adapter_src_in,
- src_out => dp_latency_adapter_src_out
- );
-
- dp_latency_adapter_src_in <= src_in;
- src_out <= dp_latency_adapter_src_out;
- end generate;
- end generate;
-
- -- p_reg
+ -- Map logic function outputs to entity outputs
+ u_dp_add_flow_control : entity work.dp_add_flow_control
+ generic map (
+ g_use_ready => g_use_ready,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out,
+ snk_in => d.src_out, -- combinatorial input
+ snk_in_reg => r.src_out, -- registered input
+
+ src_in => src_in,
+ src_out => src_out
+ );
+
+ -- p_reg function state register
r <= d when rising_edge(clk);
+ -- Logic function
p_comb : process(rst, r, snk_in)
variable v : t_reg;
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index fe8db32e2774d35401ff9d87f905ebed4d17a82e..42624ba3ea0b2b1778240d19a80e9e19e62df7b4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -61,6 +61,7 @@ entity tb_dp_packet_merge is
g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- specific
+ g_pipeline_ready : boolean := true;
g_data_w : natural := 4;
g_nof_repeat : natural := 24;
g_nof_pkt : natural := 3;
@@ -75,6 +76,7 @@ end tb_dp_packet_merge;
architecture tb of tb_dp_packet_merge is
constant c_rl : natural := 1;
+ constant c_use_ready : boolean := g_flow_control_verify /= e_active;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -298,10 +300,12 @@ begin
-- Merge every g_nof_pkt incomming packets into output packets
u_dp_packet_merge : entity work.dp_packet_merge
generic map (
- g_nof_pkt => g_nof_pkt,
- g_align_at_sync => g_align_at_sync,
- g_bsn_increment => g_bsn_increment,
- g_bsn_err_bi => c_bsn_err_bi
+ g_use_ready => c_use_ready,
+ g_pipeline_ready => g_pipeline_ready,
+ g_nof_pkt => g_nof_pkt,
+ g_align_at_sync => g_align_at_sync,
+ g_bsn_increment => g_bsn_increment,
+ g_bsn_err_bi => c_bsn_err_bi
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
index cc2fa6efa0d2f36f9731ff8179816012a7b0d140..24e34cbaf24916cfd18356d48c1a80dfd0351acd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
@@ -44,10 +44,10 @@ entity tb_dp_packet_merge_unmerge is
generic (
-- general
-- . always active, random or pulse flow control
- g_flow_control_stimuli : t_dp_flow_control_enum := e_random;
- g_flow_control_verify : t_dp_flow_control_enum := e_random;
+ g_flow_control_stimuli : t_dp_flow_control_enum := e_active;
+ g_flow_control_verify : t_dp_flow_control_enum := e_active;
-- specific
- g_use_dp_latency_adapter : boolean := true;
+ g_pipeline_ready : boolean := true;
g_data_w : natural := 16;
g_nof_repeat : natural := 24;
g_nof_pkt : natural := 3;
@@ -59,7 +59,7 @@ end tb_dp_packet_merge_unmerge;
architecture tb of tb_dp_packet_merge_unmerge is
constant c_rl : natural := 1;
- constant c_use_src_in_ready : boolean := g_flow_control_verify /= e_active;
+ constant c_use_ready : boolean := g_flow_control_verify /= e_active;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -310,11 +310,11 @@ begin
------------------------------------------------------------------------------
u_dp_packet_unmerge : entity work.dp_packet_unmerge
generic map (
- g_use_src_in_ready => c_use_src_in_ready,
- g_use_dp_latency_adapter => g_use_dp_latency_adapter,
- g_nof_pkt_max => g_nof_pkt,
- g_pkt_len => g_pkt_len,
- g_bsn_increment => g_bsn_increment
+ g_use_ready => c_use_ready,
+ g_pipeline_ready => g_pipeline_ready,
+ g_nof_pkt_max => g_nof_pkt,
+ g_pkt_len => g_pkt_len,
+ g_bsn_increment => g_bsn_increment
)
port map (
rst => rst,
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
index f08c53a92dc06f1dc773deeb6ae7823f63b478d2..8ae19f6b60bc83899124ef30cf2f886af2627a20 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
@@ -27,7 +27,7 @@ use dp_lib.tb_dp_pkg.all;
-- Purpose: Verify multiple variations of tb_dp_packet_merge
-- Description:
-- Usage:
--- > as 3
+-- > as 8, to see that correct instances are generated
-- > run -all
entity tb_tb_dp_packet_merge is
@@ -41,6 +41,7 @@ begin
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- -- specific
+ -- g_pipeline_ready : boolean := true;
-- g_data_w : natural := 4;
-- g_nof_repeat : natural := 20;
-- g_nof_pkt : natural := 3;
@@ -51,27 +52,28 @@ begin
-- g_bsn_increment : natural := 0;
-- g_bsn_err_at_pkt_index : natural := 3;
- u_act_act_8_nof_0 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 0, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_1 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 1, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_2 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 2, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_4 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 4, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_5 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 5, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_6 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 6, 29, 0, false, false, 1, 0);
- u_act_act_8_nof_7 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 7, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_0 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 0, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_1 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 1, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_2 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 2, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_4 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 4, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_5 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 5, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_6 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 6, 29, 0, false, false, 1, 0);
+ u_act_act_8_nof_7 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 7, 29, 0, false, false, 1, 0);
- u_rnd_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_random, e_active, 8, c_nof_repeat, 3, 29, 0, false, false, 2, 0);
- u_rnd_rnd_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_random, e_random, 8, c_nof_repeat, 3, 29, 0, false, false, 3, 0);
- u_pls_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_active, 8, c_nof_repeat, 3, 29, 0, false, false, 4, 0);
- u_pls_rnd_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_random, 8, c_nof_repeat, 3, 29, 0, false, false, 5, 0);
- u_pls_pls_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_pulse, 8, c_nof_repeat, 3, 29, 0, false, false, 6, 0);
+ u_rnd_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_random, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, false, 2, 0);
+ u_rnd_rnd_8_nof_3_comb : entity work.tb_dp_packet_merge generic map ( e_random, e_random, false, 8, c_nof_repeat, 3, 29, 0, false, false, 3, 0);
+ u_rnd_rnd_8_nof_3_reg : entity work.tb_dp_packet_merge generic map ( e_random, e_random, true, 8, c_nof_repeat, 3, 29, 0, false, false, 3, 0);
+ u_pls_act_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, false, 4, 0);
+ u_pls_rnd_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_random, true, 8, c_nof_repeat, 3, 29, 0, false, false, 5, 0);
+ u_pls_pls_8_nof_3 : entity work.tb_dp_packet_merge generic map ( e_pulse, e_pulse, true, 8, c_nof_repeat, 3, 29, 0, false, false, 6, 0);
- u_rnd_act_8_nof_1 : entity work.tb_dp_packet_merge generic map ( e_random, e_active, 8, c_nof_repeat, 1, 29, 0, false, false, 1, 0);
- u_rnd_act_8_nof_3_gap : entity work.tb_dp_packet_merge generic map ( e_random, e_active, 8, c_nof_repeat, 3, 29, 17, false, false, 1, 0);
+ u_rnd_act_8_nof_1 : entity work.tb_dp_packet_merge generic map ( e_random, e_active, true, 8, c_nof_repeat, 1, 29, 0, false, false, 1, 0);
+ u_rnd_act_8_nof_3_gap : entity work.tb_dp_packet_merge generic map ( e_random, e_active, true, 8, c_nof_repeat, 3, 29, 17, false, false, 1, 0);
- u_act_act_8_nof_3_no_err : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 0, 10);
- u_act_act_8_nof_3_err_10 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 10);
- u_act_act_8_nof_3_err_11 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 11);
- u_act_act_8_nof_3_err_12 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 12);
- u_act_act_8_nof_3_err_13 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 13);
+ u_act_act_8_nof_3_no_err : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, true, 0, 10);
+ u_act_act_8_nof_3_err_10 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 10);
+ u_act_act_8_nof_3_err_11 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 11);
+ u_act_act_8_nof_3_err_12 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 12);
+ u_act_act_8_nof_3_err_13 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, true, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 13);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge_unmerge.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge_unmerge.vhd
index 76246a0f14ad60d6e512b3a6e1b190b70fa04485..7fd9034f6fb81169d4c7b189a370006c2f78b9d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge_unmerge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge_unmerge.vhd
@@ -25,7 +25,7 @@ use dp_lib.tb_dp_pkg.all;
-- Purpose: Verify multiple variations of tb_dp_packet_merge_unmerge
-- Description:
-- Usage:
--- > as 3
+-- > as 8, to see that correct instances are generated
-- > run -all
entity tb_tb_dp_packet_merge_unmerge is
@@ -39,7 +39,7 @@ begin
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- -- specific
- -- g_use_dp_latency_adapter : boolean := true;
+ -- g_pipeline_ready : boolean := true;
-- g_data_w : natural := 4;
-- g_nof_repeat : natural := 20;
-- g_nof_pkt : natural := 3;
@@ -59,8 +59,8 @@ begin
u_act_act_8_nof_7 : entity work.tb_dp_packet_merge_unmerge generic map ( e_active, e_active, true, 8, c_nof_repeat, 7, 29, 0, 1);
u_rnd_act_8_nof_3 : entity work.tb_dp_packet_merge_unmerge generic map ( e_random, e_active, true, 8, c_nof_repeat, 3, 29, 0, 1);
- u_rnd_rnd_8_nof_3_pipe : entity work.tb_dp_packet_merge_unmerge generic map ( e_random, e_random, false, 8, c_nof_repeat, 3, 29, 0, 1);
- u_rnd_rnd_8_nof_3_adapt : entity work.tb_dp_packet_merge_unmerge generic map ( e_random, e_random, true, 8, c_nof_repeat, 3, 29, 0, 1);
+ u_rnd_rnd_8_nof_3_comb : entity work.tb_dp_packet_merge_unmerge generic map ( e_random, e_random, false, 8, c_nof_repeat, 3, 29, 0, 1);
+ u_rnd_rnd_8_nof_3_reg : entity work.tb_dp_packet_merge_unmerge generic map ( e_random, e_random, true, 8, c_nof_repeat, 3, 29, 0, 1);
u_pls_act_8_nof_3 : entity work.tb_dp_packet_merge_unmerge generic map ( e_pulse, e_active, true, 8, c_nof_repeat, 3, 29, 0, 1);
u_pls_rnd_8_nof_3 : entity work.tb_dp_packet_merge_unmerge generic map ( e_pulse, e_random, true, 8, c_nof_repeat, 3, 29, 0, 1);
u_pls_pls_8_nof_3 : entity work.tb_dp_packet_merge_unmerge generic map ( e_pulse, e_pulse, true, 8, c_nof_repeat, 3, 29, 0, 1);