From 771ecbc0b4c8a412bd0d787fee03d421cdd5e6b3 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Fri, 26 Sep 2014 14:11:34 +0000 Subject: [PATCH] Ported and renamed from $UNB phy_xaui_*.vhd into ip_stratixiv_phy_xaui_*.vhd. --- .../xaui/ip_stratixiv_phy_xaui_0.vhd | 274 ++++++++++++++++++ .../xaui/ip_stratixiv_phy_xaui_1.vhd | 274 ++++++++++++++++++ .../xaui/ip_stratixiv_phy_xaui_2.vhd | 274 ++++++++++++++++++ .../xaui/ip_stratixiv_phy_xaui_soft.vhd | 223 ++++++++++++++ 4 files changed, 1045 insertions(+) create mode 100644 libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_0.vhd create mode 100644 libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_1.vhd create mode 100644 libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_2.vhd create mode 100644 libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_soft.vhd diff --git a/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_0.vhd b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_0.vhd new file mode 100644 index 0000000000..9d5d76a338 --- /dev/null +++ b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_0.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %XAUI PHY v11.1% +-- GENERATION: XML +-- ip_stratixiv_phy_xaui_0.vhd + +-- Generated using ACDS version 11.1 173 at 2012.02.16.13:46:35 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ip_stratixiv_phy_xaui_0 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk + xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export + rx_ready : out std_logic; -- rx_ready.export + tx_ready : out std_logic; -- tx_ready.export + phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk + phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address + phy_mgmt_read : in std_logic := '0'; -- .read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata + phy_mgmt_write : in std_logic := '0'; -- .write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + phy_mgmt_waitrequest : out std_logic; -- .waitrequest + rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data + tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data + rx_channelaligned : out std_logic; -- rx_channelaligned.data + rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data + rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data + rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data + rx_analogreset : in std_logic := '0'; -- rx_analogreset.data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data + rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data + rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data + rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data + cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data + pll_powerdown : in std_logic := '0'; -- pll_powerdown.data + gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data + pll_locked : out std_logic; -- pll_locked.data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data + ); +end entity ip_stratixiv_phy_xaui_0; + +architecture rtl of ip_stratixiv_phy_xaui_0 is + component altera_xcvr_xaui is + generic ( + device_family : string := "Stratix IV"; + starting_channel_number : integer := 0; + interface_type : string := "Hard XAUI"; + data_rate : string := "3125 Mbps"; + xaui_pll_type : string := "AUTO"; + BASE_DATA_RATE : string := ""; + use_control_and_status_ports : integer := 0; + external_pma_ctrl_reconf : integer := 0; + recovered_clk_out : integer := 0; + number_of_interfaces : integer := 1; + reconfig_interfaces : integer := 1; + use_rx_rate_match : integer := 0; + tx_termination : string := "OCT_100_OHMS"; + tx_vod_selection : integer := 4; + tx_preemp_pretap : integer := 0; + tx_preemp_pretap_inv : integer := 0; + tx_preemp_tap_1 : integer := 0; + tx_preemp_tap_2 : integer := 0; + tx_preemp_tap_2_inv : integer := 0; + rx_common_mode : string := "0.82v"; + rx_termination : string := "OCT_100_OHMS"; + rx_eq_dc_gain : integer := 0; + rx_eq_ctrl : integer := 0; + mgmt_clk_in_mhz : integer := 150 + ); + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + xgmii_tx_clk : in std_logic := 'X'; -- clk + xgmii_rx_clk : out std_logic; -- clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export + rx_ready : out std_logic; -- export + tx_ready : out std_logic; -- export + phy_mgmt_clk : in std_logic := 'X'; -- clk + phy_mgmt_clk_reset : in std_logic := 'X'; -- reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address + phy_mgmt_read : in std_logic := 'X'; -- read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata + phy_mgmt_write : in std_logic := 'X'; -- write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + phy_mgmt_waitrequest : out std_logic; -- waitrequest + rx_digitalreset : in std_logic := 'X'; -- data + tx_digitalreset : in std_logic := 'X'; -- data + rx_channelaligned : out std_logic; -- data + rx_syncstatus : out std_logic_vector(7 downto 0); -- data + rx_disperr : out std_logic_vector(7 downto 0); -- data + rx_errdetect : out std_logic_vector(7 downto 0); -- data + rx_analogreset : in std_logic := 'X'; -- data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- data + rx_rlv : out std_logic_vector(3 downto 0); -- data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_patterndetect : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- data + rx_runningdisp : out std_logic_vector(7 downto 0); -- data + cal_blk_powerdown : in std_logic := 'X'; -- data + pll_powerdown : in std_logic := 'X'; -- data + gxb_powerdown : in std_logic := 'X'; -- data + pll_locked : out std_logic; -- data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_recovered_clk : out std_logic_vector(3 downto 0); -- export + tx_clk312_5 : out std_logic -- export + ); + end component altera_xcvr_xaui; + +begin + + ip_stratixiv_phy_xaui_0_inst : component altera_xcvr_xaui + generic map ( + device_family => "Stratix IV", + starting_channel_number => 0, + interface_type => "Hard XAUI", + data_rate => "3125 Mbps", + xaui_pll_type => "CMU", + BASE_DATA_RATE => "", + use_control_and_status_ports => 1, + external_pma_ctrl_reconf => 1, + recovered_clk_out => 0, + number_of_interfaces => 1, + reconfig_interfaces => 1, + use_rx_rate_match => 0, + tx_termination => "OCT_100_OHMS", + tx_vod_selection => 4, + tx_preemp_pretap => 0, + tx_preemp_pretap_inv => 0, + tx_preemp_tap_1 => 0, + tx_preemp_tap_2 => 0, + tx_preemp_tap_2_inv => 0, + rx_common_mode => "0.82v", + rx_termination => "OCT_100_OHMS", + rx_eq_dc_gain => 0, + rx_eq_ctrl => 0, + mgmt_clk_in_mhz => 150 + ) + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk + xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk + xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data + xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data + xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export + xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export + rx_ready => rx_ready, -- rx_ready.export + tx_ready => tx_ready, -- tx_ready.export + phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk + phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset + phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address + phy_mgmt_read => phy_mgmt_read, -- .read + phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata + phy_mgmt_write => phy_mgmt_write, -- .write + phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata + phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest + rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data + tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data + rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data + rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data + rx_disperr => rx_disperr, -- rx_disperr.data + rx_errdetect => rx_errdetect, -- rx_errdetect.data + rx_analogreset => rx_analogreset, -- rx_analogreset.data + rx_invpolarity => rx_invpolarity, -- rx_invpolarity.data + rx_set_locktodata => rx_set_locktodata, -- rx_set_locktodata.data + rx_set_locktoref => rx_set_locktoref, -- rx_set_locktoref.data + rx_seriallpbken => rx_seriallpbken, -- rx_seriallpbken.data + tx_invpolarity => tx_invpolarity, -- tx_invpolarity.data + rx_is_lockedtodata => rx_is_lockedtodata, -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error => rx_phase_comp_fifo_error, -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref => rx_is_lockedtoref, -- rx_is_lockedtoref.data + rx_rlv => rx_rlv, -- rx_rlv.data + rx_rmfifoempty => rx_rmfifoempty, -- rx_rmfifoempty.data + rx_rmfifofull => rx_rmfifofull, -- rx_rmfifofull.data + tx_phase_comp_fifo_error => tx_phase_comp_fifo_error, -- tx_phase_comp_fifo_error.data + rx_patterndetect => rx_patterndetect, -- rx_patterndetect.data + rx_rmfifodatadeleted => rx_rmfifodatadeleted, -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted => rx_rmfifodatainserted, -- rx_rmfifodatainserted.data + rx_runningdisp => rx_runningdisp, -- rx_runningdisp.data + cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data + pll_powerdown => pll_powerdown, -- pll_powerdown.data + gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data + pll_locked => pll_locked, -- pll_locked.data + reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data + reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data + rx_recovered_clk => open, -- (terminated) + tx_clk312_5 => open -- (terminated) + ); + +end architecture rtl; -- of ip_stratixiv_phy_xaui_0 +-- Retrieval info: <?xml version="1.0"?> +--<!-- +-- Generated by Altera MegaWizard Launcher Utility version 1.0 +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- ************************************************************ +-- Copyright (C) 1991-2012 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +----> +-- Retrieval info: <instance entity-name="altera_xcvr_xaui" version="11.1" > +-- Retrieval info: <generic name="device_family" value="Stratix IV" /> +-- Retrieval info: <generic name="starting_channel_number" value="0" /> +-- Retrieval info: <generic name="interface_type" value="Hard XAUI" /> +-- Retrieval info: <generic name="gui_pll_type" value="CMU" /> +-- Retrieval info: <generic name="GUI_BASE_DATA_RATE" value="" /> +-- Retrieval info: <generic name="use_control_and_status_ports" value="1" /> +-- Retrieval info: <generic name="external_pma_ctrl_reconf" value="1" /> +-- Retrieval info: <generic name="recovered_clk_out" value="0" /> +-- Retrieval info: <generic name="number_of_interfaces" value="1" /> +-- Retrieval info: <generic name="use_rx_rate_match" value="0" /> +-- Retrieval info: <generic name="tx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="tx_vod_selection" value="4" /> +-- Retrieval info: <generic name="tx_preemp_pretap" value="0" /> +-- Retrieval info: <generic name="tx_preemp_pretap_inv" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_1" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2_inv" value="0" /> +-- Retrieval info: <generic name="rx_common_mode" value="0.82v" /> +-- Retrieval info: <generic name="rx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="rx_eq_dc_gain" value="0" /> +-- Retrieval info: <generic name="rx_eq_ctrl" value="0" /> +-- Retrieval info: <generic name="mgmt_clk_in_hz" value="150000000" /> +-- Retrieval info: </instance> +-- IPFS_FILES : ip_stratixiv_phy_xaui_0.vho +-- RELATED_FILES: ip_stratixiv_phy_xaui_0.vhd, altera_xcvr_functions.sv, altera_xcvr_xaui.sv, hxaui_csr_h.sv, hxaui_csr.sv, alt_xcvr_mgmt2dec_phyreconfig.sv, alt_xcvr_mgmt2dec_xaui.sv, alt_pma_ch_controller_tgx.v, alt_pma_controller_tgx.v, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, hxaui_alt4gxb.v, hxaui.v, siv_xcvr_xaui.sv, alt_xcvr_reconfig_h.sv, alt_xcvr_reconfig_siv.sv, alt_xcvr_reconfig_analog.sv, alt_xcvr_reconfig_analog_tgx.v, alt_xcvr_reconfig_offset_cancellation.sv, alt_xcvr_reconfig_offset_cancellation_tgx.v, alt_xcvr_reconfig_eyemon_tgx.sv, alt_xcvr_reconfig_dfe_tgx.sv, alt_xcvr_reconfig_basic_tgx.v, alt_mutex_acq.v, alt_dprio.v, alt_xcvr_arbiter.sv, alt_xcvr_m2s.sv diff --git a/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_1.vhd b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_1.vhd new file mode 100644 index 0000000000..df8dcec410 --- /dev/null +++ b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_1.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %XAUI PHY v11.1% +-- GENERATION: XML +-- ip_stratixiv_phy_xaui_1.vhd + +-- Generated using ACDS version 11.1 173 at 2012.02.16.13:47:18 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ip_stratixiv_phy_xaui_1 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk + xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export + rx_ready : out std_logic; -- rx_ready.export + tx_ready : out std_logic; -- tx_ready.export + phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk + phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address + phy_mgmt_read : in std_logic := '0'; -- .read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata + phy_mgmt_write : in std_logic := '0'; -- .write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + phy_mgmt_waitrequest : out std_logic; -- .waitrequest + rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data + tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data + rx_channelaligned : out std_logic; -- rx_channelaligned.data + rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data + rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data + rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data + rx_analogreset : in std_logic := '0'; -- rx_analogreset.data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data + rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data + rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data + rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data + cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data + pll_powerdown : in std_logic := '0'; -- pll_powerdown.data + gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data + pll_locked : out std_logic; -- pll_locked.data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data + ); +end entity ip_stratixiv_phy_xaui_1; + +architecture rtl of ip_stratixiv_phy_xaui_1 is + component altera_xcvr_xaui is + generic ( + device_family : string := "Stratix IV"; + starting_channel_number : integer := 0; + interface_type : string := "Hard XAUI"; + data_rate : string := "3125 Mbps"; + xaui_pll_type : string := "AUTO"; + BASE_DATA_RATE : string := ""; + use_control_and_status_ports : integer := 0; + external_pma_ctrl_reconf : integer := 0; + recovered_clk_out : integer := 0; + number_of_interfaces : integer := 1; + reconfig_interfaces : integer := 1; + use_rx_rate_match : integer := 0; + tx_termination : string := "OCT_100_OHMS"; + tx_vod_selection : integer := 4; + tx_preemp_pretap : integer := 0; + tx_preemp_pretap_inv : integer := 0; + tx_preemp_tap_1 : integer := 0; + tx_preemp_tap_2 : integer := 0; + tx_preemp_tap_2_inv : integer := 0; + rx_common_mode : string := "0.82v"; + rx_termination : string := "OCT_100_OHMS"; + rx_eq_dc_gain : integer := 0; + rx_eq_ctrl : integer := 0; + mgmt_clk_in_mhz : integer := 150 + ); + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + xgmii_tx_clk : in std_logic := 'X'; -- clk + xgmii_rx_clk : out std_logic; -- clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export + rx_ready : out std_logic; -- export + tx_ready : out std_logic; -- export + phy_mgmt_clk : in std_logic := 'X'; -- clk + phy_mgmt_clk_reset : in std_logic := 'X'; -- reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address + phy_mgmt_read : in std_logic := 'X'; -- read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata + phy_mgmt_write : in std_logic := 'X'; -- write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + phy_mgmt_waitrequest : out std_logic; -- waitrequest + rx_digitalreset : in std_logic := 'X'; -- data + tx_digitalreset : in std_logic := 'X'; -- data + rx_channelaligned : out std_logic; -- data + rx_syncstatus : out std_logic_vector(7 downto 0); -- data + rx_disperr : out std_logic_vector(7 downto 0); -- data + rx_errdetect : out std_logic_vector(7 downto 0); -- data + rx_analogreset : in std_logic := 'X'; -- data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- data + rx_rlv : out std_logic_vector(3 downto 0); -- data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_patterndetect : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- data + rx_runningdisp : out std_logic_vector(7 downto 0); -- data + cal_blk_powerdown : in std_logic := 'X'; -- data + pll_powerdown : in std_logic := 'X'; -- data + gxb_powerdown : in std_logic := 'X'; -- data + pll_locked : out std_logic; -- data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_recovered_clk : out std_logic_vector(3 downto 0); -- export + tx_clk312_5 : out std_logic -- export + ); + end component altera_xcvr_xaui; + +begin + + ip_stratixiv_phy_xaui_1_inst : component altera_xcvr_xaui + generic map ( + device_family => "Stratix IV", + starting_channel_number => 4, + interface_type => "Hard XAUI", + data_rate => "3125 Mbps", + xaui_pll_type => "CMU", + BASE_DATA_RATE => "", + use_control_and_status_ports => 1, + external_pma_ctrl_reconf => 1, + recovered_clk_out => 0, + number_of_interfaces => 1, + reconfig_interfaces => 1, + use_rx_rate_match => 0, + tx_termination => "OCT_100_OHMS", + tx_vod_selection => 4, + tx_preemp_pretap => 0, + tx_preemp_pretap_inv => 0, + tx_preemp_tap_1 => 0, + tx_preemp_tap_2 => 0, + tx_preemp_tap_2_inv => 0, + rx_common_mode => "0.82v", + rx_termination => "OCT_100_OHMS", + rx_eq_dc_gain => 0, + rx_eq_ctrl => 0, + mgmt_clk_in_mhz => 150 + ) + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk + xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk + xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data + xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data + xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export + xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export + rx_ready => rx_ready, -- rx_ready.export + tx_ready => tx_ready, -- tx_ready.export + phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk + phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset + phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address + phy_mgmt_read => phy_mgmt_read, -- .read + phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata + phy_mgmt_write => phy_mgmt_write, -- .write + phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata + phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest + rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data + tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data + rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data + rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data + rx_disperr => rx_disperr, -- rx_disperr.data + rx_errdetect => rx_errdetect, -- rx_errdetect.data + rx_analogreset => rx_analogreset, -- rx_analogreset.data + rx_invpolarity => rx_invpolarity, -- rx_invpolarity.data + rx_set_locktodata => rx_set_locktodata, -- rx_set_locktodata.data + rx_set_locktoref => rx_set_locktoref, -- rx_set_locktoref.data + rx_seriallpbken => rx_seriallpbken, -- rx_seriallpbken.data + tx_invpolarity => tx_invpolarity, -- tx_invpolarity.data + rx_is_lockedtodata => rx_is_lockedtodata, -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error => rx_phase_comp_fifo_error, -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref => rx_is_lockedtoref, -- rx_is_lockedtoref.data + rx_rlv => rx_rlv, -- rx_rlv.data + rx_rmfifoempty => rx_rmfifoempty, -- rx_rmfifoempty.data + rx_rmfifofull => rx_rmfifofull, -- rx_rmfifofull.data + tx_phase_comp_fifo_error => tx_phase_comp_fifo_error, -- tx_phase_comp_fifo_error.data + rx_patterndetect => rx_patterndetect, -- rx_patterndetect.data + rx_rmfifodatadeleted => rx_rmfifodatadeleted, -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted => rx_rmfifodatainserted, -- rx_rmfifodatainserted.data + rx_runningdisp => rx_runningdisp, -- rx_runningdisp.data + cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data + pll_powerdown => pll_powerdown, -- pll_powerdown.data + gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data + pll_locked => pll_locked, -- pll_locked.data + reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data + reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data + rx_recovered_clk => open, -- (terminated) + tx_clk312_5 => open -- (terminated) + ); + +end architecture rtl; -- of ip_stratixiv_phy_xaui_1 +-- Retrieval info: <?xml version="1.0"?> +--<!-- +-- Generated by Altera MegaWizard Launcher Utility version 1.0 +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- ************************************************************ +-- Copyright (C) 1991-2012 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +----> +-- Retrieval info: <instance entity-name="altera_xcvr_xaui" version="11.1" > +-- Retrieval info: <generic name="device_family" value="Stratix IV" /> +-- Retrieval info: <generic name="starting_channel_number" value="4" /> +-- Retrieval info: <generic name="interface_type" value="Hard XAUI" /> +-- Retrieval info: <generic name="gui_pll_type" value="CMU" /> +-- Retrieval info: <generic name="GUI_BASE_DATA_RATE" value="" /> +-- Retrieval info: <generic name="use_control_and_status_ports" value="1" /> +-- Retrieval info: <generic name="external_pma_ctrl_reconf" value="1" /> +-- Retrieval info: <generic name="recovered_clk_out" value="0" /> +-- Retrieval info: <generic name="number_of_interfaces" value="1" /> +-- Retrieval info: <generic name="use_rx_rate_match" value="0" /> +-- Retrieval info: <generic name="tx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="tx_vod_selection" value="4" /> +-- Retrieval info: <generic name="tx_preemp_pretap" value="0" /> +-- Retrieval info: <generic name="tx_preemp_pretap_inv" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_1" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2_inv" value="0" /> +-- Retrieval info: <generic name="rx_common_mode" value="0.82v" /> +-- Retrieval info: <generic name="rx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="rx_eq_dc_gain" value="0" /> +-- Retrieval info: <generic name="rx_eq_ctrl" value="0" /> +-- Retrieval info: <generic name="mgmt_clk_in_hz" value="150000000" /> +-- Retrieval info: </instance> +-- IPFS_FILES : ip_stratixiv_phy_xaui_1.vho +-- RELATED_FILES: ip_stratixiv_phy_xaui_1.vhd, altera_xcvr_functions.sv, altera_xcvr_xaui.sv, hxaui_csr_h.sv, hxaui_csr.sv, alt_xcvr_mgmt2dec_phyreconfig.sv, alt_xcvr_mgmt2dec_xaui.sv, alt_pma_ch_controller_tgx.v, alt_pma_controller_tgx.v, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, hxaui_alt4gxb.v, hxaui.v, siv_xcvr_xaui.sv, alt_xcvr_reconfig_h.sv, alt_xcvr_reconfig_siv.sv, alt_xcvr_reconfig_analog.sv, alt_xcvr_reconfig_analog_tgx.v, alt_xcvr_reconfig_offset_cancellation.sv, alt_xcvr_reconfig_offset_cancellation_tgx.v, alt_xcvr_reconfig_eyemon_tgx.sv, alt_xcvr_reconfig_dfe_tgx.sv, alt_xcvr_reconfig_basic_tgx.v, alt_mutex_acq.v, alt_dprio.v, alt_xcvr_arbiter.sv, alt_xcvr_m2s.sv diff --git a/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_2.vhd b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_2.vhd new file mode 100644 index 0000000000..28395321ee --- /dev/null +++ b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_2.vhd @@ -0,0 +1,274 @@ +-- megafunction wizard: %XAUI PHY v11.1% +-- GENERATION: XML +-- ip_stratixiv_phy_xaui_2.vhd + +-- Generated using ACDS version 11.1 173 at 2012.02.16.13:47:52 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ip_stratixiv_phy_xaui_2 is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk + xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export + rx_ready : out std_logic; -- rx_ready.export + tx_ready : out std_logic; -- tx_ready.export + phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk + phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address + phy_mgmt_read : in std_logic := '0'; -- .read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata + phy_mgmt_write : in std_logic := '0'; -- .write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + phy_mgmt_waitrequest : out std_logic; -- .waitrequest + rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data + tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data + rx_channelaligned : out std_logic; -- rx_channelaligned.data + rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data + rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data + rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data + rx_analogreset : in std_logic := '0'; -- rx_analogreset.data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data + rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data + rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data + rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data + cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data + pll_powerdown : in std_logic := '0'; -- pll_powerdown.data + gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data + pll_locked : out std_logic; -- pll_locked.data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data + ); +end entity ip_stratixiv_phy_xaui_2; + +architecture rtl of ip_stratixiv_phy_xaui_2 is + component altera_xcvr_xaui is + generic ( + device_family : string := "Stratix IV"; + starting_channel_number : integer := 0; + interface_type : string := "Hard XAUI"; + data_rate : string := "3125 Mbps"; + xaui_pll_type : string := "AUTO"; + BASE_DATA_RATE : string := ""; + use_control_and_status_ports : integer := 0; + external_pma_ctrl_reconf : integer := 0; + recovered_clk_out : integer := 0; + number_of_interfaces : integer := 1; + reconfig_interfaces : integer := 1; + use_rx_rate_match : integer := 0; + tx_termination : string := "OCT_100_OHMS"; + tx_vod_selection : integer := 4; + tx_preemp_pretap : integer := 0; + tx_preemp_pretap_inv : integer := 0; + tx_preemp_tap_1 : integer := 0; + tx_preemp_tap_2 : integer := 0; + tx_preemp_tap_2_inv : integer := 0; + rx_common_mode : string := "0.82v"; + rx_termination : string := "OCT_100_OHMS"; + rx_eq_dc_gain : integer := 0; + rx_eq_ctrl : integer := 0; + mgmt_clk_in_mhz : integer := 150 + ); + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + xgmii_tx_clk : in std_logic := 'X'; -- clk + xgmii_rx_clk : out std_logic; -- clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export + rx_ready : out std_logic; -- export + tx_ready : out std_logic; -- export + phy_mgmt_clk : in std_logic := 'X'; -- clk + phy_mgmt_clk_reset : in std_logic := 'X'; -- reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address + phy_mgmt_read : in std_logic := 'X'; -- read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata + phy_mgmt_write : in std_logic := 'X'; -- write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + phy_mgmt_waitrequest : out std_logic; -- waitrequest + rx_digitalreset : in std_logic := 'X'; -- data + tx_digitalreset : in std_logic := 'X'; -- data + rx_channelaligned : out std_logic; -- data + rx_syncstatus : out std_logic_vector(7 downto 0); -- data + rx_disperr : out std_logic_vector(7 downto 0); -- data + rx_errdetect : out std_logic_vector(7 downto 0); -- data + rx_analogreset : in std_logic := 'X'; -- data + rx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + tx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- data + rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- data + rx_rlv : out std_logic_vector(3 downto 0); -- data + rx_rmfifoempty : out std_logic_vector(3 downto 0); -- data + rx_rmfifofull : out std_logic_vector(3 downto 0); -- data + tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data + rx_patterndetect : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- data + rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- data + rx_runningdisp : out std_logic_vector(7 downto 0); -- data + cal_blk_powerdown : in std_logic := 'X'; -- data + pll_powerdown : in std_logic := 'X'; -- data + gxb_powerdown : in std_logic := 'X'; -- data + pll_locked : out std_logic; -- data + reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_recovered_clk : out std_logic_vector(3 downto 0); -- export + tx_clk312_5 : out std_logic -- export + ); + end component altera_xcvr_xaui; + +begin + + ip_stratixiv_phy_xaui_2_inst : component altera_xcvr_xaui + generic map ( + device_family => "Stratix IV", + starting_channel_number => 8, + interface_type => "Hard XAUI", + data_rate => "3125 Mbps", + xaui_pll_type => "CMU", + BASE_DATA_RATE => "", + use_control_and_status_ports => 1, + external_pma_ctrl_reconf => 1, + recovered_clk_out => 0, + number_of_interfaces => 1, + reconfig_interfaces => 1, + use_rx_rate_match => 0, + tx_termination => "OCT_100_OHMS", + tx_vod_selection => 4, + tx_preemp_pretap => 0, + tx_preemp_pretap_inv => 0, + tx_preemp_tap_1 => 0, + tx_preemp_tap_2 => 0, + tx_preemp_tap_2_inv => 0, + rx_common_mode => "0.82v", + rx_termination => "OCT_100_OHMS", + rx_eq_dc_gain => 0, + rx_eq_ctrl => 0, + mgmt_clk_in_mhz => 150 + ) + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk + xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk + xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data + xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data + xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export + xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export + rx_ready => rx_ready, -- rx_ready.export + tx_ready => tx_ready, -- tx_ready.export + phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk + phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset + phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address + phy_mgmt_read => phy_mgmt_read, -- .read + phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata + phy_mgmt_write => phy_mgmt_write, -- .write + phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata + phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest + rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data + tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data + rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data + rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data + rx_disperr => rx_disperr, -- rx_disperr.data + rx_errdetect => rx_errdetect, -- rx_errdetect.data + rx_analogreset => rx_analogreset, -- rx_analogreset.data + rx_invpolarity => rx_invpolarity, -- rx_invpolarity.data + rx_set_locktodata => rx_set_locktodata, -- rx_set_locktodata.data + rx_set_locktoref => rx_set_locktoref, -- rx_set_locktoref.data + rx_seriallpbken => rx_seriallpbken, -- rx_seriallpbken.data + tx_invpolarity => tx_invpolarity, -- tx_invpolarity.data + rx_is_lockedtodata => rx_is_lockedtodata, -- rx_is_lockedtodata.data + rx_phase_comp_fifo_error => rx_phase_comp_fifo_error, -- rx_phase_comp_fifo_error.data + rx_is_lockedtoref => rx_is_lockedtoref, -- rx_is_lockedtoref.data + rx_rlv => rx_rlv, -- rx_rlv.data + rx_rmfifoempty => rx_rmfifoempty, -- rx_rmfifoempty.data + rx_rmfifofull => rx_rmfifofull, -- rx_rmfifofull.data + tx_phase_comp_fifo_error => tx_phase_comp_fifo_error, -- tx_phase_comp_fifo_error.data + rx_patterndetect => rx_patterndetect, -- rx_patterndetect.data + rx_rmfifodatadeleted => rx_rmfifodatadeleted, -- rx_rmfifodatadeleted.data + rx_rmfifodatainserted => rx_rmfifodatainserted, -- rx_rmfifodatainserted.data + rx_runningdisp => rx_runningdisp, -- rx_runningdisp.data + cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data + pll_powerdown => pll_powerdown, -- pll_powerdown.data + gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data + pll_locked => pll_locked, -- pll_locked.data + reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data + reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data + rx_recovered_clk => open, -- (terminated) + tx_clk312_5 => open -- (terminated) + ); + +end architecture rtl; -- of ip_stratixiv_phy_xaui_2 +-- Retrieval info: <?xml version="1.0"?> +--<!-- +-- Generated by Altera MegaWizard Launcher Utility version 1.0 +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- ************************************************************ +-- Copyright (C) 1991-2012 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +----> +-- Retrieval info: <instance entity-name="altera_xcvr_xaui" version="11.1" > +-- Retrieval info: <generic name="device_family" value="Stratix IV" /> +-- Retrieval info: <generic name="starting_channel_number" value="8" /> +-- Retrieval info: <generic name="interface_type" value="Hard XAUI" /> +-- Retrieval info: <generic name="gui_pll_type" value="CMU" /> +-- Retrieval info: <generic name="GUI_BASE_DATA_RATE" value="" /> +-- Retrieval info: <generic name="use_control_and_status_ports" value="1" /> +-- Retrieval info: <generic name="external_pma_ctrl_reconf" value="1" /> +-- Retrieval info: <generic name="recovered_clk_out" value="0" /> +-- Retrieval info: <generic name="number_of_interfaces" value="1" /> +-- Retrieval info: <generic name="use_rx_rate_match" value="0" /> +-- Retrieval info: <generic name="tx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="tx_vod_selection" value="4" /> +-- Retrieval info: <generic name="tx_preemp_pretap" value="0" /> +-- Retrieval info: <generic name="tx_preemp_pretap_inv" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_1" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2_inv" value="0" /> +-- Retrieval info: <generic name="rx_common_mode" value="0.82v" /> +-- Retrieval info: <generic name="rx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="rx_eq_dc_gain" value="0" /> +-- Retrieval info: <generic name="rx_eq_ctrl" value="0" /> +-- Retrieval info: <generic name="mgmt_clk_in_hz" value="150000000" /> +-- Retrieval info: </instance> +-- IPFS_FILES : ip_stratixiv_phy_xaui_2.vho +-- RELATED_FILES: ip_stratixiv_phy_xaui_2.vhd, altera_xcvr_functions.sv, altera_xcvr_xaui.sv, hxaui_csr_h.sv, hxaui_csr.sv, alt_xcvr_mgmt2dec_phyreconfig.sv, alt_xcvr_mgmt2dec_xaui.sv, alt_pma_ch_controller_tgx.v, alt_pma_controller_tgx.v, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, hxaui_alt4gxb.v, hxaui.v, siv_xcvr_xaui.sv, alt_xcvr_reconfig_h.sv, alt_xcvr_reconfig_siv.sv, alt_xcvr_reconfig_analog.sv, alt_xcvr_reconfig_analog_tgx.v, alt_xcvr_reconfig_offset_cancellation.sv, alt_xcvr_reconfig_offset_cancellation_tgx.v, alt_xcvr_reconfig_eyemon_tgx.sv, alt_xcvr_reconfig_dfe_tgx.sv, alt_xcvr_reconfig_basic_tgx.v, alt_mutex_acq.v, alt_dprio.v, alt_xcvr_arbiter.sv, alt_xcvr_m2s.sv diff --git a/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_soft.vhd b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_soft.vhd new file mode 100644 index 0000000000..a29570dff5 --- /dev/null +++ b/libraries/technology/ip_stratixiv/xaui/ip_stratixiv_phy_xaui_soft.vhd @@ -0,0 +1,223 @@ +-- megafunction wizard: %XAUI PHY v11.1% +-- GENERATION: XML +-- ip_stratixiv_phy_xaui_soft.vhd + +-- Generated using ACDS version 11.1 173 at 2012.02.13.13:55:45 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ip_stratixiv_phy_xaui_soft is + port ( + pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk + xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk + xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export + rx_ready : out std_logic; -- rx_ready.export + tx_ready : out std_logic; -- tx_ready.export + phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk + phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address + phy_mgmt_read : in std_logic := '0'; -- .read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata + phy_mgmt_write : in std_logic := '0'; -- .write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata + phy_mgmt_waitrequest : out std_logic; -- .waitrequest + rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data + tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data + rx_channelaligned : out std_logic; -- rx_channelaligned.data + rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data + rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data + rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data + cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data + pll_powerdown : in std_logic := '0'; -- pll_powerdown.data + gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data + pll_locked : out std_logic; -- pll_locked.data + reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- reconfig_from_xcvr.data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data + ); +end entity ip_stratixiv_phy_xaui_soft; + +architecture rtl of ip_stratixiv_phy_xaui_soft is + component altera_xcvr_xaui is + generic ( + device_family : string := "Stratix IV"; + starting_channel_number : integer := 0; + interface_type : string := "Hard XAUI"; + data_rate : string := "3125 Mbps"; + xaui_pll_type : string := "AUTO"; + BASE_DATA_RATE : string := ""; + use_control_and_status_ports : integer := 0; + external_pma_ctrl_reconf : integer := 0; + recovered_clk_out : integer := 0; + number_of_interfaces : integer := 1; + reconfig_interfaces : integer := 1; + use_rx_rate_match : integer := 0; + tx_termination : string := "OCT_100_OHMS"; + tx_vod_selection : integer := 4; + tx_preemp_pretap : integer := 0; + tx_preemp_pretap_inv : integer := 0; + tx_preemp_tap_1 : integer := 0; + tx_preemp_tap_2 : integer := 0; + tx_preemp_tap_2_inv : integer := 0; + rx_common_mode : string := "0.82v"; + rx_termination : string := "OCT_100_OHMS"; + rx_eq_dc_gain : integer := 0; + rx_eq_ctrl : integer := 0; + mgmt_clk_in_mhz : integer := 150 + ); + port ( + pll_ref_clk : in std_logic := 'X'; -- clk + xgmii_tx_clk : in std_logic := 'X'; -- clk + xgmii_rx_clk : out std_logic; -- clk + xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data + xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data + xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export + rx_ready : out std_logic; -- export + tx_ready : out std_logic; -- export + phy_mgmt_clk : in std_logic := 'X'; -- clk + phy_mgmt_clk_reset : in std_logic := 'X'; -- reset + phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address + phy_mgmt_read : in std_logic := 'X'; -- read + phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata + phy_mgmt_write : in std_logic := 'X'; -- write + phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + phy_mgmt_waitrequest : out std_logic; -- waitrequest + rx_digitalreset : in std_logic := 'X'; -- data + tx_digitalreset : in std_logic := 'X'; -- data + rx_channelaligned : out std_logic; -- data + rx_syncstatus : out std_logic_vector(7 downto 0); -- data + rx_disperr : out std_logic_vector(7 downto 0); -- data + rx_errdetect : out std_logic_vector(7 downto 0); -- data + cal_blk_powerdown : in std_logic := 'X'; -- data + pll_powerdown : in std_logic := 'X'; -- data + gxb_powerdown : in std_logic := 'X'; -- data + pll_locked : out std_logic; -- data + reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- data + reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data + rx_recovered_clk : out std_logic_vector(3 downto 0); -- export + tx_clk312_5 : out std_logic -- export + ); + end component altera_xcvr_xaui; + +begin + + ip_stratixiv_phy_xaui_soft_inst : component altera_xcvr_xaui + generic map ( + device_family => "Stratix IV", + starting_channel_number => 12, + interface_type => "Soft XAUI", + data_rate => "3125 Mbps", + xaui_pll_type => "ATX", + BASE_DATA_RATE => "", + use_control_and_status_ports => 1, + external_pma_ctrl_reconf => 1, + recovered_clk_out => 0, + number_of_interfaces => 1, + reconfig_interfaces => 4, + use_rx_rate_match => 0, + tx_termination => "OCT_100_OHMS", + tx_vod_selection => 4, + tx_preemp_pretap => 0, + tx_preemp_pretap_inv => 0, + tx_preemp_tap_1 => 0, + tx_preemp_tap_2 => 0, + tx_preemp_tap_2_inv => 0, + rx_common_mode => "0.82v", + rx_termination => "OCT_100_OHMS", + rx_eq_dc_gain => 0, + rx_eq_ctrl => 0, + mgmt_clk_in_mhz => 150 + ) + port map ( + pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk + xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk + xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk + xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data + xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data + xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export + xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export + rx_ready => rx_ready, -- rx_ready.export + tx_ready => tx_ready, -- tx_ready.export + phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk + phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset + phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address + phy_mgmt_read => phy_mgmt_read, -- .read + phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata + phy_mgmt_write => phy_mgmt_write, -- .write + phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata + phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest + rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data + tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data + rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data + rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data + rx_disperr => rx_disperr, -- rx_disperr.data + rx_errdetect => rx_errdetect, -- rx_errdetect.data + cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data + pll_powerdown => pll_powerdown, -- pll_powerdown.data + gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data + pll_locked => pll_locked, -- pll_locked.data + reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data + reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data + rx_recovered_clk => open, -- (terminated) + tx_clk312_5 => open -- (terminated) + ); + +end architecture rtl; -- of ip_stratixiv_phy_xaui_soft +-- Retrieval info: <?xml version="1.0"?> +--<!-- +-- Generated by Altera MegaWizard Launcher Utility version 1.0 +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- ************************************************************ +-- Copyright (C) 1991-2012 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +----> +-- Retrieval info: <instance entity-name="altera_xcvr_xaui" version="11.1" > +-- Retrieval info: <generic name="device_family" value="Stratix IV" /> +-- Retrieval info: <generic name="starting_channel_number" value="12" /> +-- Retrieval info: <generic name="interface_type" value="Soft XAUI" /> +-- Retrieval info: <generic name="gui_pll_type" value="ATX" /> +-- Retrieval info: <generic name="GUI_BASE_DATA_RATE" value="" /> +-- Retrieval info: <generic name="use_control_and_status_ports" value="1" /> +-- Retrieval info: <generic name="external_pma_ctrl_reconf" value="1" /> +-- Retrieval info: <generic name="recovered_clk_out" value="0" /> +-- Retrieval info: <generic name="number_of_interfaces" value="1" /> +-- Retrieval info: <generic name="use_rx_rate_match" value="0" /> +-- Retrieval info: <generic name="tx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="tx_vod_selection" value="4" /> +-- Retrieval info: <generic name="tx_preemp_pretap" value="0" /> +-- Retrieval info: <generic name="tx_preemp_pretap_inv" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_1" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2" value="0" /> +-- Retrieval info: <generic name="tx_preemp_tap_2_inv" value="0" /> +-- Retrieval info: <generic name="rx_common_mode" value="0.82v" /> +-- Retrieval info: <generic name="rx_termination" value="OCT_100_OHMS" /> +-- Retrieval info: <generic name="rx_eq_dc_gain" value="0" /> +-- Retrieval info: <generic name="rx_eq_ctrl" value="0" /> +-- Retrieval info: <generic name="mgmt_clk_in_hz" value="150000000" /> +-- Retrieval info: </instance> +-- IPFS_FILES : ip_stratixiv_phy_xaui_soft.vho +-- RELATED_FILES: ip_stratixiv_phy_xaui_soft.vhd, altera_xcvr_functions.sv, alt_pma_functions.sv, altera_xcvr_xaui.sv, hxaui_csr_h.sv, hxaui_csr.sv, alt_xcvr_mgmt2dec_phyreconfig.sv, alt_xcvr_mgmt2dec_xaui.sv, alt_pma_ch_controller_tgx.v, alt_pma_controller_tgx.v, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, alt_soft_xaui_pcs.v, alt_soft_xaui_reset.v, alt_soft_xaui_rx.v, alt_soft_xaui_rx_8b10b_dec.v, alt_soft_xaui_rx_channel_synch.v, alt_soft_xaui_rx_deskew.v, alt_soft_xaui_rx_deskew_channel.v, alt_soft_xaui_rx_deskew_ram.v, alt_soft_xaui_rx_invalid_code_det.v, alt_soft_xaui_rx_parity.v, alt_soft_xaui_rx_parity_4b.v, alt_soft_xaui_rx_parity_6b.v, alt_soft_xaui_rx_rate_match.v, alt_soft_xaui_rx_rate_match_ram.v, alt_soft_xaui_rx_rl_chk_6g.v, alt_soft_xaui_rx_sm.v, alt_soft_xaui_tx.v, alt_soft_xaui_tx_8b10b_enc.v, alt_soft_xaui_tx_idle_conv.v, l_modules.v, serdes_4_unit_lc_siv.v, serdes_4_unit_siv.v, serdes_4unit.v, sxaui.v, siv_xcvr_low_latency_phy_nr.sv, siv_xcvr_xaui.sv, alt_xcvr_reconfig_h.sv, alt_xcvr_reconfig_siv.sv, alt_xcvr_reconfig_analog.sv, alt_xcvr_reconfig_analog_tgx.v, alt_xcvr_reconfig_offset_cancellation.sv, alt_xcvr_reconfig_offset_cancellation_tgx.v, alt_xcvr_reconfig_eyemon_tgx.sv, alt_xcvr_reconfig_dfe_tgx.sv, alt_xcvr_reconfig_basic_tgx.v, alt_mutex_acq.v, alt_dprio.v, alt_xcvr_arbiter.sv, alt_xcvr_m2s.sv -- GitLab