diff --git a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
index e6894f64e14e00b7fed5826306882d7aeae971fe..39e21de98a90bb33568d11fbeed94e304dc52444 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
@@ -35,37 +35,39 @@ ARCHITECTURE tb OF tb_mms_ppsh IS
CONSTANT c_clk_freq : NATURAL := 1000; -- clock frequency in Hz
CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
CONSTANT c_pps_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
-
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL clk : STD_LOGIC := '1';
-
+
-- DUT
SIGNAL pps_ext : STD_LOGIC;
SIGNAL pps_sys : STD_LOGIC;
-
+
SIGNAL reg_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_miso : t_mem_miso;
-
+
-- Verify
SIGNAL bsn : NATURAL;
SIGNAL pps_toggle : STD_LOGIC;
SIGNAL pps_stable : STD_LOGIC;
SIGNAL capture_cnt : NATURAL;
-
+ SIGNAL offset_cnt : NATURAL;
+ SIGNAL last_offset_cnt : NATURAL;
+
BEGIN
-- Usage:
-- > as 10
-- > run -all
-- p_verify assert when unexpected capture_cnt and pps_stable are read via MM
-
+
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
rst <= '1', '0' AFTER 7*c_clk_period;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
p_pps_ext : PROCESS
VARIABLE v_pps_period : NATURAL := c_pps_period;
BEGIN
@@ -85,42 +87,53 @@ BEGIN
proc_common_wait_some_cycles(clk, 1);
pps_ext <= '0';
END LOOP;
-
+
WAIT;
END PROCESS;
-
+
p_mm_stimuli : PROCESS
VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
BEGIN
proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
-
+
v_word := '0' & TO_UVEC(c_pps_period, 31); -- capture_edge = '0' = at rising edge
-- expected_cnt = c_pps_period = 1000
proc_mem_mm_bus_wr(1, v_word, clk, reg_mosi);
-
+
+
-- Simulate reading PPS status every 10 PPS periods
proc_common_wait_some_cycles(clk, 10);
FOR I IN 0 TO 9 LOOP
proc_common_wait_some_cycles(clk, c_pps_period*10);
-
+
proc_mem_mm_bus_rd(0, clk, reg_mosi);
- proc_common_wait_some_cycles(clk, 1);
+ proc_common_wait_some_cycles(clk, 1);
pps_toggle <= reg_miso.rddata(31);
pps_stable <= reg_miso.rddata(30);
capture_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
END LOOP;
-
+
+ -- Simulate reading PPS offset counter every 0.1 PPS periods
+ proc_common_wait_some_cycles(clk, 10);
+ FOR I IN 0 TO 4 LOOP
+ proc_common_wait_some_cycles(clk, c_pps_period/10);
+ last_offset_cnt <= offset_cnt;
+ proc_mem_mm_bus_rd(2, clk, reg_mosi);
+ proc_common_wait_some_cycles(clk, 1);
+ offset_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
+ END LOOP;
+
proc_common_wait_some_cycles(clk, 100);
tb_end <= '1';
WAIT;
END PROCESS;
-
+
p_verify : PROCESS
BEGIN
proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
-
+
proc_common_wait_some_cycles(clk, c_pps_period/2); -- Verification offset
-- 1
proc_common_wait_some_cycles(clk, c_pps_period*10);
@@ -158,14 +171,20 @@ BEGIN
proc_common_wait_some_cycles(clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "9) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "9) Wrong capture_cnt" SEVERITY ERROR;
+ -- 10
+ proc_common_wait_some_cycles(clk, c_pps_period/10);
+ ASSERT offset_cnt=last_offset_cnt REPORT "10) Wrong offset_cnt" SEVERITY ERROR;
+ -- 11
+ proc_common_wait_some_cycles(clk, c_pps_period/10);
+ ASSERT offset_cnt=last_offset_cnt REPORT "11) Wrong offset_cnt" SEVERITY ERROR;
WAIT;
END PROCESS;
-
-
+
+
-----------------------------------------------------------------------------
-- DUT: PPSH
-----------------------------------------------------------------------------
-
+
dut : ENTITY work.mms_ppsh
GENERIC MAP (
g_st_clk_freq => c_clk_freq
@@ -177,11 +196,11 @@ BEGIN
st_rst => rst,
st_clk => clk,
pps_ext => pps_ext,
-
+
-- Memory-mapped clock domain
reg_mosi => reg_mosi,
reg_miso => reg_miso,
-
+
-- Streaming clock domain
pps_sys => pps_sys
);
diff --git a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
index e675a9c7843fe5cbc9e0eff93624025e0d373799..c77528573229ab1c1f0a02b4e6eb4f71530351b0 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
@@ -33,7 +33,7 @@ ARCHITECTURE tb OF tb_ppsh IS
CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
CONSTANT c_pps_default_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
CONSTANT c_pps_skew : TIME := 7*c_clk_period/10;
-
+
-- The state name tells what kind of test is being done
TYPE t_state_enum IS (
s_idle,
@@ -49,7 +49,7 @@ ARCHITECTURE tb OF tb_ppsh IS
SIGNAL rst : STD_LOGIC := '1';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL pps : STD_LOGIC;
-
+
-- DUT
SIGNAL pps_ext : STD_LOGIC;
SIGNAL pps_sys : STD_LOGIC;
@@ -57,24 +57,24 @@ ARCHITECTURE tb OF tb_ppsh IS
SIGNAL capture_edge : STD_LOGIC;
SIGNAL capture_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
SIGNAL offset_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
-
+
-- Verify
-
+
BEGIN
-- Usage: 'run -all', observe unsigned capture_cnt, there should occur no
-- REPORT errors.
-
+
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
rst <= '1', '0' AFTER 7*c_clk_period;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
-- Verify that using the falling capture edge indeed does change timing by
-- using a c_pps_skew that is > 0.5 c_clk_period and < c_clk_period
capture_edge <= '0', '1' AFTER 5000 ms, '0' AFTER 7000 ms;
-
+
-- Verify the capture_cnt
p_pps_default_period : PROCESS
BEGIN
@@ -132,7 +132,7 @@ BEGIN
END LOOP;
-- Missing PPS pulses
tb_state <= s_missing_pps;
-
+
-- End
tb_state <= s_end;
WAIT FOR c_pps_default_period*c_clk_period;
@@ -140,14 +140,14 @@ BEGIN
WAIT;
END PROCESS;
- -- Apply some PPS to CLK skew
+ -- Apply some PPS to CLK skew
pps_ext <= TRANSPORT pps AFTER c_pps_skew;
-
-
+
+
-----------------------------------------------------------------------------
-- DUT: PPSH
-----------------------------------------------------------------------------
-
+
dut : ENTITY work.ppsh
GENERIC MAP (
g_clk_freq => c_clk_freq
@@ -168,7 +168,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Verify capture_cnt
-----------------------------------------------------------------------------
-
+
-- Simple verify scheme that matches the stimuli from p_pps_default_period
p_verify : PROCESS(clk)
BEGIN
@@ -181,69 +181,85 @@ BEGIN
UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value." SEVERITY ERROR;
END IF;
-
+
-- Verify influence of PPS capture edge selection
IF (NOW > 6000 ms) AND (NOW <= 6000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 6 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 7000 ms) AND (NOW <= 7000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 7 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 8000 ms) AND (NOW <= 8000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 8 s." SEVERITY ERROR;
END IF;
END IF;
-
+
-- Verify external PPS period fluctuations at specific stimuli moments
IF (NOW > 10000 ms) AND (NOW <= 10000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 10 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 22000 ms) AND (NOW <= 22000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 22 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 25000 ms) AND (NOW <= 25000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 25 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 28000 ms) AND (NOW <= 28000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 28 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 30000 ms) AND (NOW <= 30000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 30 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 35000 ms) AND (NOW <= 35000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 35 s." SEVERITY ERROR;
END IF;
END IF;
-
+
IF (NOW > 49000 ms) AND (NOW <= 49000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 49 s." SEVERITY ERROR;
END IF;
END IF;
+
+ -- check if offset_cnt is counting
+ IF (NOW > 7500 ms) AND (NOW <= 7500 ms + c_clk_period) THEN
+ --REPORT "PPSH : offset_cnt = " & integer'image(To_integer(unsigned(offset_cnt))) SEVERITY ERROR;
+ IF UNSIGNED(offset_cnt)/=475 THEN
+ REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
+ END IF;
+ END IF;
+
+ IF (NOW > 7700 ms) AND (NOW <= 7700 ms + c_clk_period) THEN
+ --REPORT "PPSH : offset_cnt = " & integer'image(To_integer(unsigned(offset_cnt))) SEVERITY ERROR;
+ IF UNSIGNED(offset_cnt)/=675 THEN
+ REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
+ END IF;
+ END IF;
+
END IF;
END PROCESS;
-
+
END tb;