diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg b/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg index 3aed629267af16d20d071102e2b32a845f170805..3a411dc0ce1b32b1d3994c06b97211ae84244208 100644 --- a/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg +++ b/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg @@ -1,6 +1,6 @@ hdl_lib_name = aartfaac_fn_sdo hdl_library_clause_name = aartfaac_fn_sdo_lib -hdl_lib_uses_synth = unb1_board +hdl_lib_uses_synth = unb1_board tr_xaui tr_10GbE tr_nonbonded hdl_lib_uses_sim = hdl_lib_technology = ip_stratixiv @@ -8,6 +8,7 @@ hdl_lib_technology = ip_stratixiv synth_top_level_entity = quartus_copy_files = + src/quartus/sopc_aartfaac_fn_sdo.sopc . modelsim_copy_files = @@ -17,18 +18,17 @@ synth_files = src/vhdl/aartfaac_fn_sdo.vhd test_bench_files = - tb/vhdl/tb_aartfaac_fn_sdo.vhd - + quartus_qsf_files = $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf quartus_tcl_files = -# quartus/aartfaac_fn_sdo_pins.tcl + quartus/aartfaac_fn_sdo_pins.tcl quartus_vhdl_files = quartus_qip_files = - $HDL_BUILD_DIR/unb1/quartus/aartfaac_fn_sdo/sopc_aartfaac_fn_sdo/sopc_aartfaac_fn_sdo.qip + $HDL_BUILD_DIR/unb1/quartus/aartfaac_fn_sdo/sopc_aartfaac_fn_sdo.qip quartus_sdc_files = $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc b/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc index 946a38643c77403d91defc63534a755ed0d7bc54..3cddc24548e323463d16322f69ceb8aa89338a36 100644 --- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc +++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc @@ -14,7 +14,7 @@ { datum baseAddress { - value = "672"; + value = "768"; type = "long"; } } @@ -22,7 +22,7 @@ { datum _sortIndex { - value = "10"; + value = "18"; type = "int"; } } @@ -100,6 +100,19 @@ type = "String"; } } + element pio_system_info.mem + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "0"; + type = "long"; + } + } element reg_unb_sens.mem { datum baseAddress @@ -108,11 +121,19 @@ type = "long"; } } - element reg_diag_data_buffer.mem + element reg_tr_xaui.mem { datum baseAddress { - value = "576"; + value = "16384"; + type = "long"; + } + } + element reg_diagnostics.mem + { + datum baseAddress + { + value = "256"; type = "long"; } } @@ -124,7 +145,7 @@ type = "long"; } } - element reg_wdi.mem + element rom_system_info.mem { datum _lockedAddress { @@ -133,57 +154,68 @@ } datum baseAddress { - value = "12288"; + value = "4096"; type = "long"; } } - element reg_diagnostics.mem + element reg_diag_data_buffer.mem { datum baseAddress { - value = "256"; + value = "576"; type = "long"; } } - element reg_tr_10GbE.mem + element ram_diag_data_buffer.mem { datum baseAddress { - value = "32768"; + value = "262144"; type = "long"; } } - element pio_system_info.mem + element reg_mdio_0.mem { - datum _lockedAddress + datum baseAddress { - value = "1"; - type = "boolean"; + value = "608"; + type = "long"; } + } + element reg_tr_10GbE.mem + { datum baseAddress { - value = "0"; + value = "32768"; type = "long"; } } - element rom_system_info.mem + element reg_mdio_2.mem { - datum _lockedAddress + datum baseAddress { - value = "1"; - type = "boolean"; + value = "672"; + type = "long"; } + } + element reg_mdio_1.mem + { datum baseAddress { - value = "4096"; + value = "640"; type = "long"; } } - element ram_diag_data_buffer.mem + element reg_wdi.mem { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "262144"; + value = "12288"; type = "long"; } } @@ -191,7 +223,7 @@ { datum baseAddress { - value = "16384"; + value = "24576"; type = "long"; } } @@ -236,7 +268,7 @@ { datum _sortIndex { - value = "15"; + value = "14"; type = "int"; } } @@ -244,7 +276,7 @@ { datum _sortIndex { - value = "13"; + value = "12"; type = "int"; } } @@ -270,7 +302,7 @@ } datum baseAddress { - value = "608"; + value = "704"; type = "long"; } } @@ -278,7 +310,7 @@ { datum _sortIndex { - value = "17"; + value = "16"; type = "int"; } } @@ -286,7 +318,7 @@ { datum _sortIndex { - value = "16"; + value = "15"; type = "int"; } } @@ -298,11 +330,35 @@ type = "int"; } } + element reg_mdio_0 + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + } + element reg_mdio_1 + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + } + element reg_mdio_2 + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + } element reg_tr_10GbE { datum _sortIndex { - value = "18"; + value = "17"; type = "int"; } } @@ -314,11 +370,19 @@ type = "int"; } } + element reg_tr_xaui + { + datum _sortIndex + { + value = "19"; + type = "int"; + } + } element reg_unb_sens { datum _sortIndex { - value = "12"; + value = "11"; type = "int"; } } @@ -326,7 +390,7 @@ { datum _sortIndex { - value = "14"; + value = "13"; type = "int"; } } @@ -334,15 +398,23 @@ { datum _sortIndex { - value = "11"; + value = "10"; type = "int"; } } + element pio_wdi.s1 + { + datum baseAddress + { + value = "736"; + type = "long"; + } + } element pio_debug_wave.s1 { datum baseAddress { - value = "624"; + value = "720"; type = "long"; } } @@ -359,27 +431,19 @@ type = "long"; } } - element pio_pps.s1 - { - datum baseAddress - { - value = "656"; - type = "long"; - } - } - element pio_wdi.s1 + element timer_0.s1 { datum baseAddress { - value = "640"; + value = "512"; type = "long"; } } - element timer_0.s1 + element pio_pps.s1 { datum baseAddress { - value = "512"; + value = "752"; type = "long"; } } @@ -406,10 +470,10 @@ <parameter name="globalResetBus" value="true" /> <parameter name="hdlLanguage" value="VHDL" /> <parameter name="maxAdditionalLatency" value="0" /> - <parameter name="projectName" value="aartfaac_fn_sdo.qpf" /> + <parameter name="projectName" value="" /> <parameter name="sopcBorderPoints" value="true" /> - <parameter name="systemHash" value="-44423241518" /> - <parameter name="timeStamp" value="1395327914772" /> + <parameter name="systemHash" value="-60671328635" /> + <parameter name="timeStamp" value="1441368791753" /> <parameter name="useTestBenchNamingPattern" value="false" /> <module kind="clock_source" version="11.1" enabled="1" name="clk_0"> <parameter name="clockFrequency" value="25000000" /> @@ -510,7 +574,7 @@ <parameter name="dcache_numTCDM" value="_0" /> <parameter name="dcache_lineSize" value="_32" /> <parameter name="dcache_bursts" value="false" /> - <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_tr_nonbonded.mem' start='0x80' end='0xC0' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='timer_0.s1' start='0x200' end='0x220' /><slave name='reg_unb_sens.mem' start='0x220' end='0x240' /><slave name='reg_diag_data_buffer.mem' start='0x240' end='0x260' /><slave name='altpll_0.pll_slave' start='0x260' end='0x270' /><slave name='pio_debug_wave.s1' start='0x270' end='0x280' /><slave name='pio_wdi.s1' start='0x280' end='0x290' /><slave name='pio_pps.s1' start='0x290' end='0x2A0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A0' end='0x2A8' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_tr_10GbE.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter> + <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_tr_nonbonded.mem' start='0x80' end='0xC0' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='timer_0.s1' start='0x200' end='0x220' /><slave name='reg_unb_sens.mem' start='0x220' end='0x240' /><slave name='reg_diag_data_buffer.mem' start='0x240' end='0x260' /><slave name='reg_mdio_0.mem' start='0x260' end='0x280' /><slave name='reg_mdio_1.mem' start='0x280' end='0x2A0' /><slave name='reg_mdio_2.mem' start='0x2A0' end='0x2C0' /><slave name='altpll_0.pll_slave' start='0x2C0' end='0x2D0' /><slave name='pio_debug_wave.s1' start='0x2D0' end='0x2E0' /><slave name='pio_wdi.s1' start='0x2E0' end='0x2F0' /><slave name='pio_pps.s1' start='0x2F0' end='0x300' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x300' end='0x308' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_tr_10GbE.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter> <parameter name="dataAddrWidth" value="19" /> <parameter name="customInstSlavesSystemInfo" value="<info/>" /> <parameter name="cpuReset" value="false" /> @@ -787,9 +851,6 @@ q]]></parameter> <parameter name="timeoutPulseOutput" value="false" /> <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter> </module> - <module kind="avs_eth_coe" version="1.0" enabled="1" name="avs_eth_0"> - <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" /> - </module> <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info"> <parameter name="g_adr_w" value="10" /> <parameter name="g_dat_w" value="32" /> @@ -851,6 +912,33 @@ q]]></parameter> <parameter name="g_dat_w" value="32" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> </module> + <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0"> + <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" /> + </module> + <module + kind="avs_common_mm_readlatency0" + version="1.0" + enabled="1" + name="reg_tr_xaui"> + <parameter name="g_adr_w" value="11" /> + <parameter name="g_dat_w" value="32" /> + <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> + </module> + <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_0"> + <parameter name="g_adr_w" value="3" /> + <parameter name="g_dat_w" value="32" /> + <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> + </module> + <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_1"> + <parameter name="g_adr_w" value="3" /> + <parameter name="g_dat_w" value="32" /> + <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> + </module> + <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_2"> + <parameter name="g_adr_w" value="3" /> + <parameter name="g_dat_w" value="32" /> + <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" /> + </module> <connection kind="avalon" version="11.1" @@ -889,7 +977,7 @@ q]]></parameter> start="cpu_0.data_master" end="jtag_uart_0.avalon_jtag_slave"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x02a0" /> + <parameter name="baseAddress" value="0x0300" /> </connection> <connection kind="interrupt" @@ -904,7 +992,7 @@ q]]></parameter> start="cpu_0.data_master" end="altpll_0.pll_slave"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0260" /> + <parameter name="baseAddress" value="0x02c0" /> </connection> <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" /> <connection @@ -929,7 +1017,7 @@ q]]></parameter> start="cpu_0.data_master" end="pio_debug_wave.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0270" /> + <parameter name="baseAddress" value="0x02d0" /> </connection> <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" /> <connection @@ -938,7 +1026,7 @@ q]]></parameter> start="cpu_0.data_master" end="pio_wdi.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0280" /> + <parameter name="baseAddress" value="0x02e0" /> </connection> <connection kind="clock" @@ -978,38 +1066,6 @@ q]]></parameter> <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq"> <parameter name="irqNumber" value="1" /> </connection> - <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" /> - <connection - kind="avalon" - version="11.1" - start="cpu_0.data_master" - end="avs_eth_0.mms_tse"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x2000" /> - </connection> - <connection - kind="avalon" - version="11.1" - start="cpu_0.data_master" - end="avs_eth_0.mms_reg"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x00c0" /> - </connection> - <connection - kind="avalon" - version="11.1" - start="cpu_0.data_master" - end="avs_eth_0.mms_ram"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x4000" /> - </connection> - <connection - kind="interrupt" - version="11.1" - start="cpu_0.d_irq" - end="avs_eth_0.interrupt"> - <parameter name="irqNumber" value="2" /> - </connection> <connection kind="clock" version="11.1" @@ -1065,7 +1121,7 @@ q]]></parameter> start="cpu_0.data_master" end="pio_pps.s1"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0290" /> + <parameter name="baseAddress" value="0x02f0" /> </connection> <connection kind="clock" @@ -1106,4 +1162,88 @@ q]]></parameter> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x8000" /> </connection> + <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" /> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="avs_eth_0.mms_tse"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x2000" /> + </connection> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="avs_eth_0.mms_reg"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x00c0" /> + </connection> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="avs_eth_0.mms_ram"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x6000" /> + </connection> + <connection + kind="interrupt" + version="11.1" + start="cpu_0.d_irq" + end="avs_eth_0.interrupt"> + <parameter name="irqNumber" value="2" /> + </connection> + <connection + kind="clock" + version="11.1" + start="altpll_0.c0" + end="reg_tr_xaui.system" /> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="reg_tr_xaui.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x4000" /> + </connection> + <connection + kind="clock" + version="11.1" + start="altpll_0.c0" + end="reg_mdio_0.system" /> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="reg_mdio_0.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0260" /> + </connection> + <connection + kind="clock" + version="11.1" + start="altpll_0.c0" + end="reg_mdio_1.system" /> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="reg_mdio_1.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0280" /> + </connection> + <connection + kind="clock" + version="11.1" + start="altpll_0.c0" + end="reg_mdio_2.system" /> + <connection + kind="avalon" + version="11.1" + start="cpu_0.data_master" + end="reg_mdio_2.mem"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x02a0" /> + </connection> </system> diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd index 435eb0d8b68989b2a77171b29915de58b0656ee6..1538c1d32f485050b164dbf68535a07ac6bbce2d 100644 --- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd +++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- Copyright (C) 2014 +-- Copyright (C) 2015 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands @@ -30,18 +30,19 @@ -- . MAC: 10.99.x.8 for FN0 -- . IP : 10.99.x.9 for FN0 -LIBRARY IEEE, common_lib, unb_common_lib, tse_lib, dp_lib, tr_nonbonded_lib, tr_xaui_lib, tr_10GbE_lib, diag_lib; +LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib, tech_tse_lib, dp_lib, tr_nonbonded_lib, tech_mac_10g_lib, tr_10GbE_lib, diag_lib; --tr_xaui_lib USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE common_lib.common_pkg.ALL; USE common_lib.common_mem_pkg.ALL; -USE unb_common_lib.unb_common_pkg.ALL; -USE unb_common_lib.unb_peripherals_pkg.ALL; +USE common_lib.common_interface_layers_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +--USE unb1_board_lib.unb_peripherals_pkg.ALL; USE common_lib.common_field_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL; -USE tse_lib.tse_pkg.ALL; -USE tse_lib.eth_pkg.ALL; -USE tr_xaui_lib.tr_xaui_pkg.ALL; +USE tech_tse_lib.tech_tse_pkg.ALL; +USE eth_lib.eth_pkg.ALL; +--USE tr_xaui_lib.tr_xaui_pkg.ALL; ENTITY aartfaac_fn_sdo IS GENERIC ( @@ -57,9 +58,9 @@ ENTITY aartfaac_fn_sdo IS PPS : IN STD_LOGIC; WDI : OUT STD_LOGIC; - VERSION : IN STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0); - ID : IN STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0); - TESTIO : INOUT STD_LOGIC_VECTOR(c_unb_aux.testio_w-1 DOWNTO 0); + VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0); sens_sc : INOUT STD_LOGIC; sens_sd : INOUT STD_LOGIC; @@ -71,28 +72,28 @@ ENTITY aartfaac_fn_sdo IS SB_CLK : IN STD_LOGIC; -- SerDes Clock FN-BN SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN - FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - - SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0); - - SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO) - SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0); - SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0); - SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0); + FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + + SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); + + SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO) + SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); + SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); + SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor. -- So we need to assign a '1' to it. ); @@ -102,7 +103,7 @@ END aartfaac_fn_sdo; ARCHITECTURE str OF aartfaac_fn_sdo IS CONSTANT c_design_name : STRING := "aartfaac_fn_sdo"; - CONSTANT c_fw_version : t_unb_fw_version := (1, 1); + CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 1); CONSTANT c_nof_streams : NATURAL := 2; -- 2 BN @@ -119,7 +120,7 @@ ARCHITECTURE str OF aartfaac_fn_sdo IS SIGNAL mm_rst : STD_LOGIC; SIGNAL dp_rst : STD_LOGIC; SIGNAL dp_clk : STD_LOGIC; - SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb_nof_chip_w-1 DOWNTO 0); + SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- PIOs SIGNAL pout_wdi : STD_LOGIC; @@ -163,13 +164,17 @@ ARCHITECTURE str OF aartfaac_fn_sdo IS SIGNAL ram_diag_data_buf_miso : t_mem_miso; SIGNAL reg_diag_data_buf_mosi : t_mem_mosi; SIGNAL reg_diag_data_buf_miso : t_mem_miso := c_mem_miso_rst; + SIGNAL reg_tr_xaui_mosi : t_mem_mosi; + SIGNAL reg_tr_xaui_miso : t_mem_miso := c_mem_miso_rst; + SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); + SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); SIGNAL reg_tr_10GbE_mosi : t_mem_mosi; SIGNAL reg_tr_10GbE_miso : t_mem_miso; -- DP signals - SIGNAL term_rx_serial_2arr : t_unb_mesh_sl_2arr; - SIGNAL term_src_in_2arr : t_unb_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy)); - SIGNAL term_src_out_2arr : t_unb_mesh_sosi_2arr; + SIGNAL term_rx_serial_2arr : t_unb1_board_mesh_sl_2arr; + SIGNAL term_src_in_2arr : t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy)); + SIGNAL term_src_out_2arr : t_unb1_board_mesh_sosi_2arr; SIGNAL diag_data_buffer_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_fifo_dc_mixed_widths_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); SIGNAL dp_fifo_dc_mixed_widths_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0); @@ -179,8 +184,8 @@ ARCHITECTURE str OF aartfaac_fn_sdo IS SIGNAL tr_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); - SIGNAL unb_xaui_tx_arr : t_unb_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); - SIGNAL unb_xaui_rx_arr : t_unb_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); + SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); + SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); -- Vitesse MDIO signals SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0); @@ -192,9 +197,9 @@ BEGIN ----------------------------------------------------------------------------- -- I/O wiring: mesh transceivers ----------------------------------------------------------------------------- - u_mesh_io : ENTITY unb_common_lib.unb_mesh_io + u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io GENERIC MAP ( - g_bus_w => c_unb_ci.tr.bus_w + g_bus_w => c_unb1_board_ci.tr.bus_w ) PORT MAP ( rx_serial_2arr => term_rx_serial_2arr, @@ -214,13 +219,13 @@ BEGIN -- Mesh Terminals -- . Receive from BN0 and BN1 ----------------------------------------------------------------------------- - u_terminals_mesh : ENTITY unb_common_lib.unb_terminals_mesh + u_terminals_mesh : ENTITY unb1_board_lib.unb1_board_terminals_mesh GENERIC MAP ( g_sim => g_sim, g_sim_level => 1, g_node_type => e_fn, g_nof_bus => 4, - g_usr_data_w => c_tse_data_w, + g_usr_data_w => c_tech_tse_data_w, g_usr_frame_len => c_block_nof_words, --2 blocks of 8 subbands*96SP*195312.5Hz*32b = ~4800Mbps g_usr_nof_streams => 4, g_phy_nof_serial => 3, @@ -265,7 +270,7 @@ BEGIN u_data_buf : ENTITY diag_lib.mms_diag_data_buffer GENERIC MAP ( g_nof_streams => c_nof_streams, - g_data_w => c_tse_data_w, + g_data_w => c_tech_tse_data_w, g_buf_nof_data => 8192, g_buf_use_sync => FALSE ) @@ -287,7 +292,7 @@ BEGIN gen_dp_fifo_dc_mixed_widths : FOR i IN 0 TO c_nof_streams-1 GENERATE u_dp_fifo_dc_mixed_widths : ENTITY dp_lib.dp_fifo_dc_mixed_widths GENERIC MAP ( - g_wr_data_w => c_tse_data_w, + g_wr_data_w => c_tech_tse_data_w, g_rd_data_w => c_xgmii_data_w, g_use_ctrl => TRUE, g_wr_fifo_size => 2*c_block_nof_words @@ -345,16 +350,28 @@ BEGIN g_nof_macs => c_nof_10GbE_offload_streams, g_use_mdio => TRUE, g_mdio_epcs_dis => TRUE, -- Be compatible with 10GbE (Chelsio) card in PC - g_pkt_len => 1130, -- 1130 64b words = 9040B (enough for jumbo frame) +-- g_pkt_len => 1130, -- 1130 64b words = 9040B (enough for jumbo frame) + g_tx_fifo_fill => 1000, --FIXME more than enough but should be based on actual packet len. + g_tx_fifo_size => 2*1000, --FIXME g_word_alignment_padding => TRUE ) PORT MAP ( + tr_ref_clk_156 => SA_CLK, + tr_ref_rst_156 => sa_rst, + + cal_rec_clk => cal_rec_clk, + mm_rst => mm_rst, mm_clk => mm_clk, - tr_clk => SA_CLK, + reg_mac_mosi => reg_tr_10GbE_mosi, + reg_mac_miso => reg_tr_10GbE_miso, + + xaui_mosi => reg_tr_xaui_mosi, + xaui_miso => reg_tr_xaui_miso, - cal_rec_clk => cal_rec_clk, + mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0), + mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0), dp_rst => dp_rst, dp_clk => dp_clk, @@ -362,12 +379,10 @@ BEGIN snk_out_arr => tr_10GbE_snk_out_arr, snk_in_arr => tr_10GbE_snk_in_arr, - reg_mac_mosi => reg_tr_10GbE_mosi, - reg_mac_miso => reg_tr_10GbE_miso, - - xaui_tx_out_arr => xaui_tx_arr, - xaui_rx_in_arr => xaui_rx_arr, + xaui_tx_arr => xaui_tx_arr, + xaui_rx_arr => xaui_rx_arr, + mdio_rst => SI_FN_RSTN, mdio_mdc_arr => mdio_mdc_arr, mdio_mdat_in_arr => mdio_mdat_in_arr, mdio_mdat_oen_arr => mdio_mdat_oen_arr @@ -379,7 +394,7 @@ BEGIN xaui_rx_arr(i) <= unb_xaui_rx_arr(i); END GENERATE; - u_front_io : ENTITY unb_common_lib.unb_front_io + u_front_io : ENTITY unb1_board_lib.unb_front_io GENERIC MAP ( g_nof_xaui => c_nof_10GbE_offload_streams ) @@ -408,7 +423,7 @@ BEGIN ----------------------------------------------------------------------------- -- General control function ----------------------------------------------------------------------------- - u_ctrl : ENTITY unb_common_lib.ctrl_unb_common + u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board GENERIC MAP ( g_sim => g_sim, g_design_name => c_design_name, @@ -540,6 +555,10 @@ BEGIN reg_diagnostics_mosi => reg_diagnostics_mosi, reg_diagnostics_miso => reg_diagnostics_miso, + reg_mdio_mosi_arr => reg_mdio_mosi_arr, + reg_mdio_miso_arr => reg_mdio_miso_arr, + reg_tr_xaui_mosi => reg_tr_xaui_mosi, + reg_tr_xaui_miso => reg_tr_xaui_miso, reg_tr_10GbE_mosi => reg_tr_10GbE_mosi, reg_tr_10GbE_miso => reg_tr_10GbE_miso ); diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd index 82f645034a2038f02665c24461dd56f30249c95c..20a2797a64dbe1eb9ba07b11a935abd60ddf1637 100644 --- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd +++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd @@ -19,21 +19,24 @@ -- ------------------------------------------------------------------------------- -LIBRARY IEEE, common_lib, unb_common_lib, mm_lib, tse_lib, rsp_terminal_lib; +LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tech_tse_lib, technology_lib;--, rsp_terminal_lib; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE common_lib.common_pkg.ALL; USE common_lib.common_mem_pkg.ALL; -USE unb_common_lib.unb_common_pkg.ALL; -USE unb_common_lib.unb_peripherals_pkg.ALL; +USE common_lib.common_network_layers_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL; USE common_lib.tb_common_mem_pkg.ALL; -USE tse_lib.tse_pkg.ALL; -USE tse_lib.tb_tse_pkg.ALL; -USE tse_lib.eth_pkg.ALL; -USE tse_lib.eth_layers_pkg.ALL; -USE rsp_terminal_lib.rsp_terminal_pkg.ALL; +USE tech_tse_lib.tech_tse_pkg.ALL; +USE tech_tse_lib.tb_tech_tse_pkg.ALL; +USE eth_lib.eth_pkg.ALL; +--USE tse_lib.eth_layers_pkg.ALL; +--USE rsp_terminal_lib.rsp_terminal_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; ENTITY mmm_aartfaac_fn_sdo IS GENERIC ( @@ -136,8 +139,8 @@ ARCHITECTURE str OF mmm_aartfaac_fn_sdo IS ); END COMPONENT; - CONSTANT c_dut_src_mac : STD_LOGIC_VECTOR(c_eth_mac_slv'RANGE) := X"002286080001"; - SIGNAL eth_psc_access : STD_LOGIC; + CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001"; + SIGNAL sim_eth_psc_access : STD_LOGIC; CONSTANT c_dut_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en; SIGNAL i_eth1g_reg_mosi : t_mem_mosi; @@ -210,8 +213,9 @@ BEGIN eth1g_tse_mosi.rd <= '0'; WAIT FOR 400 ns; WAIT UNTIL rising_edge(i_mm_clk); - proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi); - +-- proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi); + proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi); + -- Enable RX proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en mm_bus_switch <= '0'; @@ -257,7 +261,7 @@ BEGIN -- the_avs_eth_0 coe_clk_export_from_the_avs_eth_0 => OPEN, coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst, - coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tse_byte_addr_w-1 DOWNTO 0), + coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0), coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr, coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd, @@ -278,7 +282,7 @@ BEGIN -- the_reg_unb_sens coe_clk_export_from_the_reg_unb_sens => OPEN, coe_reset_export_from_the_reg_unb_sens => OPEN, - coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0), + coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0), coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd, coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr, @@ -287,7 +291,7 @@ BEGIN -- the_reg_tr_nonbonded coe_clk_export_from_the_reg_tr_nonbonded => OPEN, coe_reset_export_from_the_reg_tr_nonbonded => OPEN, - coe_address_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.address(c_unb_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0), + coe_address_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0), coe_read_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.rd, coe_readdata_export_to_the_reg_tr_nonbonded => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_reg_tr_nonbonded => reg_tr_nonbonded_mosi.wr, @@ -296,7 +300,7 @@ BEGIN -- the_reg_diagnostics (in mms_tr_nonbonded) coe_clk_export_from_the_reg_diagnostics => OPEN, coe_reset_export_from_the_reg_diagnostics => OPEN, - coe_address_export_from_the_reg_diagnostics => reg_diagnostics_mosi.address(c_unb_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0), + coe_address_export_from_the_reg_diagnostics => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0), coe_read_export_from_the_reg_diagnostics => reg_diagnostics_mosi.rd, coe_readdata_export_to_the_reg_diagnostics => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wr, @@ -311,7 +315,7 @@ BEGIN -- the_pio_system_info: actually a avs_common_mm instance coe_clk_export_from_the_pio_system_info => OPEN, coe_reset_export_from_the_pio_system_info => OPEN, - coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), + coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd, coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr, @@ -320,7 +324,7 @@ BEGIN -- the_rom_system_info coe_clk_export_from_the_rom_system_info => OPEN, coe_reset_export_from_the_rom_system_info => OPEN, - coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), + coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd, coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,