diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..56e232cc5220e64d7f5fb1c211e5db3c89ea8d5e
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -0,0 +1,61 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+
+Contents:
+
+1) FIFO components
+2) Arria10 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+
+
+1) FIFO components:
+
+ ip_arria10_fifo_sc = Single clock FIFO
+ ip_arria10_fifo_dc = Dual clock FIFO
+ ip_arria10_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+
+
+2) Arria10 IP
+
+ The IP was ported from Stratix IV by:
+
+ . copy original MegaWizard <fifo_name>.vhd file
+ . rename <fifo_name>.vhd into ip_arria10_<fifo_name>.vhd (also replace name inside the file)
+ . commit the fifo/ip_arria10_<fifo_name>.vhd to preserve the MegaWizard original
+ . open in to Quartus 14, set device family to Arria10 and finish automatically convert to Qsys
+ . then generate HDL (select VHDL for both sim and synth) and finish to save it as ip_arria10_<fifo_name>.qsys
+
+ this yields:
+
+ ip_arria10_fifo_sc.qsys
+ ip_arria10_fifo_dc.qsys
+ ip_arria10_fifo_dc_mixed_widths.qsys
+
+ The Arria10 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+ FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+
+ The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
+ directly instantiates the altera_mf component.
+
+ The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
+ no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
+
+
+
+3) Implementation options (LUTs or block RAM)
+
+ The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K), however this is not supported yet. This would imply
+ adding a generic to set the appropriate parameter in the altera_mf.
+
+
+4) Synthesis trials
+
+ The quartus/fifo.qpf Quartus project was used to verify that the FIFO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+5) Issues
+
+ No issues.
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/fifo/hdllib.cfg b/libraries/technology/ip_arria10/fifo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f3c7f424ace2621ad4cca2e5abe74f86377d28df
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/hdllib.cfg
@@ -0,0 +1,14 @@
+hdl_lib_name = ip_arria10_fifo
+hdl_library_clause_name = ip_arria10_fifo_lib
+hdl_lib_uses = technology
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ ip_arria10_fifo_sc.vhd
+ ip_arria10_fifo_dc.vhd
+ ip_arria10_fifo_dc_mixed_widths.vhd
+
+test_bench_files =
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..c80e9005a2f435c2711debc724f6a893a58030b1
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.qsys
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element ip_arria10_fifo_dc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="data" internal="data" />
+ <port name="wrreq" internal="wrreq" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrusedw" internal="wrusedw" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="wrfull" internal="wrfull" />
+ </interface>
+ <module
+ kind="fifo"
+ version="14.0"
+ enabled="1"
+ name="ip_arria10_fifo_dc"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b1afae234e983d30c3204d5a64a747905c9e9de7
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
@@ -0,0 +1,224 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo
+
+-- ============================================================
+-- File Name: ip_arria10_fifo_dc.vhd
+-- Megafunction Name(s):
+-- dcfifo
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_fifo_dc IS
+ GENERIC (
+ g_dat_w : NATURAL;
+ g_nof_words : NATURAL
+ );
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_fifo_dc;
+
+
+ARCHITECTURE SYN OF ip_arria10_fifo_dc IS
+
+ SIGNAL sub_wire0 : STD_LOGIC ;
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+
+
+
+ COMPONENT dcfifo
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ wrclk : IN STD_LOGIC ;
+ rdempty : OUT STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+ aclr : IN STD_LOGIC ;
+ wrfull : OUT STD_LOGIC ;
+ rdclk : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ rdempty <= sub_wire0;
+ wrusedw <= sub_wire1(ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull <= sub_wire2;
+ q <= sub_wire3(g_dat_w-1 DOWNTO 0);
+ rdusedw <= sub_wire4(ceil_log2(g_nof_words)-1 DOWNTO 0);
+
+ dcfifo_component : dcfifo
+ GENERIC MAP (
+ intended_device_family => "Stratix IV",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ wrclk => wrclk,
+ rdreq => rdreq,
+ aclr => aclr,
+ rdclk => rdclk,
+ wrreq => wrreq,
+ data => data,
+ rdempty => sub_wire0,
+ wrusedw => sub_wire1,
+ wrfull => sub_wire2,
+ q => sub_wire3,
+ rdusedw => sub_wire4
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..2471308fd7968a0d8d49ac06204a7fad7b6f0b3b
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.qsys
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element ip_arria10_fifo_dc_mixed_widths
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="data" internal="data" />
+ <port name="wrreq" internal="wrreq" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrusedw" internal="wrusedw" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="wrfull" internal="wrfull" />
+ </interface>
+ <module
+ kind="fifo"
+ version="14.0"
+ enabled="1"
+ name="ip_arria10_fifo_dc_mixed_widths"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_output_width" value="16" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_diff_widths" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..738cc51dd3a869281e305b3747f6ba0aae6273ff
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
@@ -0,0 +1,231 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths
+
+-- ============================================================
+-- File Name: ip_arria10_fifo_dc_mixed_widths.vhd
+-- Megafunction Name(s):
+-- dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 218 06/27/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL;
+ g_rddat_w : NATURAL
+ );
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_ip_arria10_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE SYN OF ip_arria10_ip_arria10_fifo_dc_mixed_widths IS
+
+ SIGNAL sub_wire0 : STD_LOGIC ;
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (q'RANGE);
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (wrusedw'RANGE);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (rdusedw'RANGE);
+
+
+
+ COMPONENT dcfifo_mixed_widths
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ lpm_widthu_r : NATURAL;
+ lpm_width_r : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ rdclk : IN STD_LOGIC ;
+ wrfull : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (q'RANGE);
+ rdempty : OUT STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (wrusedw'RANGE);
+ aclr : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (data'RANGE);
+ rdreq : IN STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (rdusedw'RANGE)
+ );
+ END COMPONENT;
+
+BEGIN
+ wrfull <= sub_wire0;
+ q <= sub_wire1(q'RANGE);
+ rdempty <= sub_wire2;
+ wrusedw <= sub_wire3(wrusedw'RANGE);
+ rdusedw <= sub_wire4(rdusedw'RANGE);
+
+ dcfifo_mixed_widths_component : dcfifo_mixed_widths
+ GENERIC MAP (
+ intended_device_family => "Stratix IV",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_wrdat_w,
+ lpm_widthu => ceil_log2(g_nof_words),
+ lpm_widthu_r => ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
+ lpm_width_r => g_rddat_w,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ rdclk => rdclk,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ aclr => aclr,
+ data => data,
+ rdreq => rdreq,
+ wrfull => sub_wire0,
+ q => sub_wire1,
+ rdempty => sub_wire2,
+ wrusedw => sub_wire3,
+ rdusedw => sub_wire4
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "16"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL "rdusedw[6..0]"
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
+-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_dc_mixed_widths_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f242da88a46821285294070116370020e93e5a30
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.qsys
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element ip_arria10_fifo_sc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_sc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="data" internal="data" />
+ <port name="wrreq" internal="wrreq" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="clock" internal="clock" />
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_sc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="usedw" internal="usedw" />
+ <port name="full" internal="full" />
+ <port name="empty" internal="empty" />
+ </interface>
+ <module
+ kind="fifo"
+ version="14.0"
+ enabled="1"
+ name="ip_arria10_fifo_sc"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_Clock" value="0" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="1" />
+ <parameter name="GUI_delaypipe" value="3" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_sc_aclr" value="true" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsUsedW" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsUsedW" value="false" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_dc_aclr" value="false" />
+ <parameter name="GUI_write_aclr_synch" value="false" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..24ab13fa7f631e8e0245445ac5fc8c2c9bf8d28e
--- /dev/null
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
@@ -0,0 +1,206 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo
+
+-- ============================================================
+-- File Name: ip_arria10_fifo_sc.vhd
+-- Megafunction Name(s):
+-- scfifo
+--
+-- Simulation Library Files(s):
+--
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL;
+ g_nof_words : NATURAL
+ );
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_fifo_sc;
+
+
+ARCHITECTURE SYN OF ip_arria10_fifo_sc IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (usedw'RANGE);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC_VECTOR (data'RANGE);
+
+
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ clock : IN STD_LOGIC ;
+ usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ aclr : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ usedw <= sub_wire0;
+ empty <= sub_wire1;
+ full <= sub_wire2;
+ q <= sub_wire3;
+
+ scfifo_component : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Stratix IV",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => g_use_eab
+ )
+ PORT MAP (
+ clock => clock,
+ wrreq => wrreq,
+ aclr => aclr,
+ data => data,
+ rdreq => rdreq,
+ usedw => sub_wire0,
+ empty => sub_wire1,
+ full => sub_wire2,
+ q => sub_wire3
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_fifo_sc_wave*.jpg FALSE