From 74859ca79b8b93f693d511a77f0c57ff04e3f12a Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 13 Jun 2018 09:25:10 +0000
Subject: [PATCH] -Added overloaded version of proc_common_stop_simulation() to
tb_common_pkg; -Added proc_common_stop_simulation() and
proc_common_timeout_failure() to tb_tb_tech_eth_10g. . Reason: this tb
would make the unb1 regression test hang.
---
.../base/common/tb/vhdl/tb_common_pkg.vhd | 16 +++++++++++++++-
.../technology/eth_10g/tb_tb_tech_eth_10g.vhd | 19 ++++++++-----------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index cab5db0eea..db6e7b3faa 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -102,8 +102,11 @@ PACKAGE tb_common_pkg IS
-- Exit simulation on timeout failure
PROCEDURE proc_common_timeout_failure(CONSTANT c_timeout : IN TIME;
SIGNAL tb_end : IN STD_LOGIC);
-
+
+
-- Stop simulation using severity FAILURE when g_tb_end=TRUE, else for use in multi tb report as severity NOTE
+ PROCEDURE proc_common_stop_simulation(SIGNAL tb_end : IN STD_LOGIC);
+
PROCEDURE proc_common_stop_simulation(CONSTANT g_tb_end : IN BOOLEAN;
CONSTANT g_latency : IN NATURAL; -- latency between tb_done and tb_)end
SIGNAL clk : IN STD_LOGIC;
@@ -519,6 +522,17 @@ PACKAGE BODY tb_common_pkg IS
WAIT FOR 1 us;
END LOOP;
END PROCEDURE;
+
+ PROCEDURE proc_common_stop_simulation(SIGNAL tb_end : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+ -- For modelsim_regression_test_vhdl.py:
+ -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
+ -- stop the simulation using failure, without causing the test to fail.
+ WAIT FOR 1 ns;
+ REPORT "Tb simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCEDURE;
PROCEDURE proc_common_stop_simulation(CONSTANT g_tb_end : IN BOOLEAN;
CONSTANT g_latency : IN NATURAL;
diff --git a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
index a6c21ed141..da9e11a4fa 100644
--- a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
@@ -25,13 +25,13 @@
-- > as 5
-- > run -all
-LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
+LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib, common_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_mac_10g_lib.tb_tech_mac_10g_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
-
+USE common_lib.tb_common_pkg.ALL;
ENTITY tb_tb_tech_eth_10g IS
END tb_tb_tech_eth_10g;
@@ -62,14 +62,11 @@ BEGIN
u_no_dut : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, TRUE, 0, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(0));
u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(1));
u_sim_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(2));
-
+
+ -- Simulation end control
tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
-
- p_tb_end : PROCESS
- BEGIN
- WAIT UNTIL tb_end='1';
- WAIT FOR 1 ns;
- REPORT "Multi tb simulation finished." SEVERITY FAILURE;
- WAIT;
- END PROCESS;
+
+ proc_common_stop_simulation(tb_end);
+ proc_common_timeout_failure(1 ms, tb_end);
+
END tb;
--
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