From 747d37907be7371d8aaae95ef49f8370e2f5a5eb Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 7 Nov 2014 15:58:37 +0000
Subject: [PATCH] added 10GbE tests
---
.../revisions/unb1_test_10GbE/hdllib.cfg | 39 +++++
.../unb1_test_10GbE/tb_unb1_test_10GbE.vhd | 41 +++++
.../unb1_test_10GbE/unb1_test_10GbE.vhd | 157 ++++++++++++++++++
.../unb1_test_lpbk/unb1_test_lpbk.vhd | 1 +
.../designs/unb1_test/src/vhdl/unb1_test.vhd | 5 +-
.../unb1_test/tb/vhdl/tb_unb1_test.vhd | 52 ++++--
6 files changed, 280 insertions(+), 15 deletions(-)
create mode 100644 boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
create mode 100644 boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
create mode 100644 boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
new file mode 100644
index 0000000000..4c84606aa1
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -0,0 +1,39 @@
+hdl_lib_name = unb1_test_10GbE
+hdl_library_clause_name = unb1_test_10GbE_lib
+hdl_lib_uses = unb1_board unb1_test
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ unb1_test_10GbE.vhd
+
+test_bench_files =
+ tb_unb1_test_10GbE.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_unb1_test.qsys .
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex ../..
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ ../../quartus/unb1_test_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
new file mode 100644
index 0000000000..9b8f7d9e49
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -0,0 +1,41 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb1_test_10GbE.
+-- Description: see tb_unb1_test
+
+
+LIBRARY IEEE, unb1_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb1_test_10GbE IS
+END tb_unb1_test_10GbE;
+
+
+ARCHITECTURE tb OF tb_unb1_test_10GbE IS
+BEGIN
+ u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
+ GENERIC MAP (
+ g_design_name => "unb1_test_10GbE"
+ );
+END tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
new file mode 100644
index 0000000000..1779dd506b
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb1_board_lib, unb1_test_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+ENTITY unb1_test_10GbE IS
+ GENERIC (
+ g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
+ g_design_note : STRING := "Test Design with 10GbE";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+
+ -- Serial I/O
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+
+ BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
+ );
+END unb1_test_10GbE;
+
+
+ARCHITECTURE str OF unb1_test_10GbE IS
+
+BEGIN
+
+ u_revision : ENTITY unb1_test_lib.unb1_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ PORT MAP (
+ -- GENERAL
+ --CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX
+ );
+
+END str;
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
index 814377e5dd..1066f91b79 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
@@ -27,6 +27,7 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
ENTITY unb1_test_lpbk IS
GENERIC (
g_design_name : STRING := "unb1_test_lpbk"; -- use revision name = entity name = design name
+ g_design_note : STRING := "Test Design with loopback";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index b714809f23..655243c411 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -40,6 +40,7 @@ ENTITY unb1_test IS
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_design_name : STRING := "unb1_test"; -- set by QSF
+ g_design_note : STRING := "Test Design";
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
@@ -745,12 +746,12 @@ BEGIN
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
- in_sync => diag_data_buf_snk_in_arr(0).sop,
+ --in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
-----------------------------------------------------------------------------
-- Interface : Loopback
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 428e4e98c9..279315a4fc 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -69,6 +69,7 @@ ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_tr_clk_period : TIME := 40 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- DUT
@@ -94,15 +95,34 @@ ARCHITECTURE tb OF tb_unb1_test IS
-- 10GbE
SIGNAL tr_clk : STD_LOGIC := '0';
- -- Serial I/O
- SIGNAL FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ -- Serial I/O
+ SIGNAL SI_FN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL SI_FN_0_TXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_0_RXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SIGNAL SI_FN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL SI_FN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL SI_FN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL SI_FN_0_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SIGNAL SI_FN_1_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SIGNAL SI_FN_2_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SIGNAL SI_FN_3_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SIGNAL SI_FN_RSTN : STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+
+ SIGNAL BN_BI_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL BN_BI_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL BN_BI_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL BN_BI_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL BN_BI_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL BN_BI_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL BN_BI_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL BN_BI_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
@@ -121,8 +141,9 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+ tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Ethernet ref clock (25 MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -139,6 +160,11 @@ BEGIN
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ ------------------------------------------------------------------------------
+ -- 10GbE Loopback model
+ ------------------------------------------------------------------------------
+ SI_FN_0_RXp <= TRANSPORT SI_FN_0_TXp;-- AFTER c_cable_delay;
------------------------------------------------------------------------------
-- DUT
@@ -176,8 +202,8 @@ BEGIN
--SB_CLK => tr_clk,
-- Serial I/O
- SI_FN_0_TX => OPEN,
- SI_FN_0_RX => (OTHERS=>'0'),
+ SI_FN_0_TX => SI_FN_0_TXp,
+ SI_FN_0_RX => SI_FN_0_RXp,
SI_FN_1_TX => OPEN,
SI_FN_1_RX => (OTHERS=>'0'),
SI_FN_2_TX => OPEN,
--
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