diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index 5fc586cb1a24475deb6f73479999f2db63bd25a5..8969b9a7ff0cb1128987ac4c2dc78b35df0d0153 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -72,14 +72,14 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY tb_tr_nonbonded IS  
   GENERIC (
     g_data_w    : NATURAL := 32;
-    g_sim_level : NATURAL := 0
+    g_sim_level : NATURAL := 1
   );
 END ENTITY tb_tr_nonbonded;
 
 ARCHITECTURE str of tb_tr_nonbonded IS
 
   CONSTANT c_sim                 : BOOLEAN := TRUE;
-  CONSTANT c_nof_gx              : NATURAL := 2;
+  CONSTANT c_nof_gx              : NATURAL := 1;
   CONSTANT c_mbps                : NATURAL := 6250;
 
   CONSTANT tr_clk_period         : TIME := 6.4 ns;  -- 156.25 MHz
@@ -133,7 +133,9 @@ BEGIN
   p_bn_tr_clk : PROCESS
   BEGIN
     bn_clk_en <= '0';
-    WAIT FOR 1.6 ns ; -- 1/4 cycle behind
+    IF g_sim_level=0 THEN
+      WAIT FOR 1.6 ns ; -- with PHY use bn_tr_clk 1/4 cycle behind fn_tr_clk, with sim model the all tr_clk must have the same phase
+    END IF;
     bn_clk_en <= '1';
     WAIT;      
   END PROCESS;