diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
index d2b1a27c2eefb9895dcce74105cafc49f0d7a53e..a077318e1691f709cdca76977e761c4962849b90 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/quartus/sopc_apertif_unb1_fn_beamformer.sopc
@@ -22,7 +22,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "35";
type = "int";
}
}
@@ -92,27 +92,19 @@
type = "String";
}
}
- element ram_st_sst.mem
- {
- datum baseAddress
- {
- value = "16384";
- type = "long";
- }
- }
- element reg_dp_offload_tx.mem
+ element reg_dp_pkt_merge.mem
{
datum baseAddress
{
- value = "1640";
+ value = "1440";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_st_sst.mem
{
datum baseAddress
{
- value = "786432";
+ value = "1152";
type = "long";
}
}
@@ -129,205 +121,205 @@
type = "long";
}
}
- element reg_tr_xaui.mem
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "835584";
+ value = "4096";
type = "long";
}
}
- element reg_dp_pkt_merge.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "1440";
+ value = "1312";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "1344";
+ value = "786432";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "1312";
+ value = "768";
type = "long";
}
}
- element reg_st_sst.mem
+ element reg_dp_split.mem
{
datum baseAddress
{
- value = "1152";
+ value = "1408";
type = "long";
}
}
- element reg_diagnostics_mesh.mem
+ element reg_mdio_1.mem
{
datum baseAddress
{
- value = "256";
+ value = "1504";
type = "long";
}
}
- element ram_diag_bg.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "32768";
+ value = "0";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "1088";
+ value = "1640";
type = "long";
}
}
- element reg_mdio_0.mem
+ element reg_tr_nonbonded_mesh.mem
{
datum baseAddress
{
- value = "1472";
+ value = "1024";
type = "long";
}
}
- element ram_ss_ss_transp.mem
+ element reg_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "819200";
+ value = "1376";
type = "long";
}
}
- element reg_tr_nonbonded_mesh.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "1024";
+ value = "835584";
type = "long";
}
}
- element ram_bf_weights.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "262144";
+ value = "32768";
type = "long";
}
}
- element reg_mdio_1.mem
+ element ram_ss_ss_transp.mem
{
datum baseAddress
{
- value = "1504";
+ value = "819200";
type = "long";
}
}
- element reg_mdio_2.mem
+ element ram_st_sst.mem
{
datum baseAddress
{
- value = "1536";
+ value = "16384";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_diag_bg.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "4096";
+ value = "1344";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_ovr.mem
+ element reg_diag_data_buffer.mem
{
datum baseAddress
{
- value = "896";
+ value = "128";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element ram_bf_weights.mem
{
datum baseAddress
{
- value = "65536";
+ value = "262144";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "524288";
+ value = "1472";
type = "long";
}
}
- element reg_dp_ram_from_mm.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "1376";
+ value = "524288";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_mdio_2.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "1536";
type = "long";
}
}
- element reg_dp_split.mem
+ element ram_diag_data_buffer.mem
{
datum baseAddress
{
- value = "1408";
+ value = "65536";
type = "long";
}
}
- element ram_dp_ram_from_mm.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "512";
+ value = "1088";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_diagnostics_mesh.mem
{
datum baseAddress
{
- value = "768";
+ value = "256";
type = "long";
}
}
- element reg_diag_data_buffer.mem
+ element ram_dp_ram_from_mm.mem
{
datum baseAddress
{
- value = "128";
+ value = "512";
type = "long";
}
}
@@ -459,7 +451,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "36";
type = "int";
}
}
@@ -515,7 +507,7 @@
{
datum _sortIndex
{
- value = "30";
+ value = "29";
type = "int";
}
}
@@ -527,14 +519,6 @@
type = "int";
}
}
- element reg_dp_offload_tx_hdr_ovr
- {
- datum _sortIndex
- {
- value = "29";
- type = "int";
- }
- }
element reg_dp_pkt_merge
{
datum _sortIndex
@@ -563,7 +547,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "32";
type = "int";
}
}
@@ -571,7 +555,7 @@
{
datum _sortIndex
{
- value = "34";
+ value = "33";
type = "int";
}
}
@@ -579,7 +563,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "34";
type = "int";
}
}
@@ -595,7 +579,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "30";
type = "int";
}
}
@@ -611,7 +595,7 @@
{
datum _sortIndex
{
- value = "32";
+ value = "31";
type = "int";
}
}
@@ -639,6 +623,14 @@
type = "int";
}
}
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "1584";
+ type = "long";
+ }
+ }
element pio_pps.s1
{
datum baseAddress
@@ -668,14 +660,6 @@
type = "long";
}
}
- element pio_debug_wave.s1
- {
- datum baseAddress
- {
- value = "1584";
- type = "long";
- }
- }
element pio_wdi.s1
{
datum _lockedAddress
@@ -719,8 +703,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">apertif_unb1_fn_beamformer.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-75578276317" />
- <parameter name="timeStamp" value="1425482136704" />
+ <parameter name="systemHash" value="-77951753286" />
+ <parameter name="timeStamp" value="1429253411776" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -821,7 +805,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x300' end='0x380' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x380' end='0x400' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x400' end='0x440' /><slave name='reg_bsn_monitor.mem' start='0x440' end='0x480' /><slave name='reg_st_sst.mem' start='0x480' end='0x4C0' /><slave name='avs_eth_0.mms_reg' start='0x4C0' end='0x500' /><slave name='timer_0.s1' start='0x500' end='0x520' /><slave name='reg_unb_sens.mem' start='0x520' end='0x540' /><slave name='reg_diag_bg.mem' start='0x540' end='0x560' /><slave name='reg_dp_ram_from_mm.mem' start='0x560' end='0x580' /><slave name='reg_dp_split.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_pkt_merge.mem' start='0x5A0' end='0x5C0' /><slave name='reg_mdio_0.mem' start='0x5C0' end='0x5E0' /><slave name='reg_mdio_1.mem' start='0x5E0' end='0x600' /><slave name='reg_mdio_2.mem' start='0x600' end='0x620' /><slave name='altpll_0.pll_slave' start='0x620' end='0x630' /><slave name='pio_debug_wave.s1' start='0x630' end='0x640' /><slave name='pio_wdi.s1' start='0x640' end='0x650' /><slave name='pio_pps.s1' start='0x650' end='0x660' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x660' end='0x668' /><slave name='reg_dp_offload_tx.mem' start='0x668' end='0x670' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_transp.mem' start='0xC8000' end='0xCC000' /><slave name='reg_tr_xaui.mem' start='0xCC000' end='0xCE000' /><slave name='avs_eth_0.mms_ram' start='0xCE000' end='0xCF000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_diagnostics_mesh.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x300' end='0x380' /><slave name='reg_tr_nonbonded_mesh.mem' start='0x400' end='0x440' /><slave name='reg_bsn_monitor.mem' start='0x440' end='0x480' /><slave name='reg_st_sst.mem' start='0x480' end='0x4C0' /><slave name='avs_eth_0.mms_reg' start='0x4C0' end='0x500' /><slave name='timer_0.s1' start='0x500' end='0x520' /><slave name='reg_unb_sens.mem' start='0x520' end='0x540' /><slave name='reg_diag_bg.mem' start='0x540' end='0x560' /><slave name='reg_dp_ram_from_mm.mem' start='0x560' end='0x580' /><slave name='reg_dp_split.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_pkt_merge.mem' start='0x5A0' end='0x5C0' /><slave name='reg_mdio_0.mem' start='0x5C0' end='0x5E0' /><slave name='reg_mdio_1.mem' start='0x5E0' end='0x600' /><slave name='reg_mdio_2.mem' start='0x600' end='0x620' /><slave name='altpll_0.pll_slave' start='0x620' end='0x630' /><slave name='pio_debug_wave.s1' start='0x630' end='0x640' /><slave name='pio_wdi.s1' start='0x640' end='0x650' /><slave name='pio_pps.s1' start='0x650' end='0x660' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x660' end='0x668' /><slave name='reg_dp_offload_tx.mem' start='0x668' end='0x670' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_st_sst.mem' start='0x4000' end='0x8000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x80000' /><slave name='ram_ss_ss_wide.mem' start='0x80000' end='0xC0000' /><slave name='reg_tr_10GbE.mem' start='0xC0000' end='0xC8000' /><slave name='ram_ss_ss_transp.mem' start='0xC8000' end='0xCC000' /><slave name='reg_tr_xaui.mem' start='0xCC000' end='0xCE000' /><slave name='avs_eth_0.mms_ram' start='0xCE000' end='0xCF000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="20" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -1230,15 +1214,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
- <module
- kind="avs_common_mm"
- version="1.0"
- enabled="1"
- name="reg_dp_offload_tx_hdr_ovr">
- <parameter name="g_adr_w" value="5" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- </module>
<module
kind="avs_common_mm"
version="1.0"
@@ -1659,19 +1634,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0300" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_ovr.system" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_hdr_ovr.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0380" />
- </connection>
<connection
kind="clock"
version="11.1"
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index c3a9a3d8ced8ad5718cf3196cd2eec57260c2398..e98d884217eae21a8b170dc9a47891e1986e762d 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -290,8 +290,6 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
@@ -776,9 +774,7 @@ BEGIN
reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso
);
u_mmm : ENTITY work.mmm_apertif_unb1_fn_beamformer
@@ -867,8 +863,7 @@ BEGIN
reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
index ba778802d085acdfdb973b5f9ae19b690223bfa5..e210c9d00c7c70faba5fcc1c43a2985f9bc697c2 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
@@ -60,10 +60,7 @@ ENTITY apertif_unb1_fn_beamformer_udp_offload IS
reg_dp_offload_tx_miso : OUT t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- reg_dp_offload_tx_hdr_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_hdr_ovr_miso : OUT t_mem_miso := c_mem_miso_rst
+ reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst
);
END apertif_unb1_fn_beamformer_udp_offload;
@@ -128,9 +125,8 @@ BEGIN
g_def_nof_words_per_block => c_def_nof_words_per_block,
g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_output_fifo_depth => c_frame_nof_words,
g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
- g_hdr_field_ovr_init => c_hdr_field_ovr_init
+ g_hdr_field_sel => c_hdr_field_ovr_init
)
PORT MAP (
mm_rst => mm_rst,
@@ -145,9 +141,6 @@ BEGIN
reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
snk_in_arr => dp_offload_tx_snk_in_arr,
snk_out_arr => OPEN,
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
index e0aa828ebb1e53f8ef82a613e73b6acf765adef4..547fe582753973f23c31593c4362173238f6acf1 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
@@ -128,8 +128,6 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
reg_dp_offload_tx_miso : IN t_mem_miso;
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
- reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso;
@@ -604,16 +602,7 @@ BEGIN
coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_ovr
- coe_address_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
+
-- the_reg_tr_10GbE
coe_clk_export_from_the_reg_tr_10GbE => OPEN,
coe_reset_export_from_the_reg_tr_10GbE => OPEN,