From 73fb4051076e80ee29da306f6c845216eb96e1c7 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 2 Apr 2015 16:09:48 +0000
Subject: [PATCH] Added entry for reg_io_ddr
---
.../src/vhdl/mmm_unb1_ddr3_transpose.vhd | 20 +++++++++++++++++--
.../src/vhdl/unb1_ddr3_transpose.vhd | 17 +++++++++++++---
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 17435a68a3..28b71acba3 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -102,7 +102,11 @@ ENTITY mmm_unb_ddr3_transpose IS
reg_diag_data_buf_re_miso : IN t_mem_miso;
reg_bsn_monitor_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_miso : IN t_mem_miso
+ reg_bsn_monitor_miso : IN t_mem_miso;
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi : OUT t_mem_mosi;
+ reg_io_ddr_miso : IN t_mem_miso
);
END mmm_unb_ddr3_transpose;
@@ -196,7 +200,10 @@ BEGIN
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
-
+
+ u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -355,6 +362,15 @@ BEGIN
coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_io_ddr
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 DOWNTO 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor
coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1+c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 42cfb41296..7fd9bb7703 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -77,7 +77,7 @@ END unb1_ddr3_transpose;
ARCHITECTURE str OF unb1_ddr3_transpose IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 6);
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 8);
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 1, 0, 0, 1);
@@ -201,7 +201,11 @@ ARCHITECTURE str OF unb1_ddr3_transpose IS
-- BNS Monitor
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_miso : t_mem_miso;
+
SIGNAL bsn_sosi_arr : t_dp_sosi_arr(1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -369,7 +373,11 @@ BEGIN
-- BSN monitor
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
);
-----------------------------------------------------------------------------
@@ -465,6 +473,9 @@ BEGIN
dp_out_clk => dp_clk,
dp_out_rst => dp_rst,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
snk_out_arr => bg_siso_arr,
snk_in_arr => bg_sosi_arr,
--
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