From 73da5ceaf0b32e7217e33da204bf06374b0db4c2 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 4 Mar 2020 10:34:40 +0100
Subject: [PATCH] Moved and renamed MM bus code from common to mm HDL library.
---
libraries/base/common/hdllib.cfg | 9 ---------
libraries/base/mm/hdllib.cfg | 15 ++++++++++++++-
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index b5d7279942..c7c3d8323e 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -109,8 +109,6 @@ synth_files =
src/vhdl/common_fifo_rd.vhd
src/vhdl/common_blockreg.vhd
src/vhdl/common_fifo_dc_lock_control.vhd
- src/vhdl/common_mem_master_mux.vhd
- src/vhdl/common_mem_bus.vhd
src/vhdl/common_mem_mux.vhd
src/vhdl/common_mem_demux.vhd
src/vhdl/common_reg_cross_domain.vhd
@@ -147,7 +145,6 @@ synth_files =
tb/vhdl/tb_common_mem_pkg.vhd
test_bench_files =
- tb/vhdl/common_mem_waitrequest_model.vhd
tb/vhdl/tb_common_acapture.vhd
tb/vhdl/tb_common_add_sub.vhd
tb/vhdl/tb_common_adder_tree.vhd
@@ -165,8 +162,6 @@ test_bench_files =
tb/vhdl/tb_common_init.vhd
tb/vhdl/tb_common_int2float.vhd
tb/vhdl/tb_common_led_controller.vhd
- tb/vhdl/tb_common_mem_master_mux.vhd
- tb/vhdl/tb_common_mem_bus.vhd
tb/vhdl/tb_common_mem_mux.vhd
tb/vhdl/tb_common_multiplexer.vhd
tb/vhdl/tb_common_operation_tree.vhd
@@ -198,8 +193,6 @@ test_bench_files =
tb/vhdl/tb_tb_common_add_sub.vhd
tb/vhdl/tb_tb_common_adder_tree.vhd
- tb/vhdl/tb_tb_common_mem_bus.vhd
- tb/vhdl/tb_tb_common_mem_master_mux.vhd
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -226,8 +219,6 @@ regression_test_vhdl =
tb/vhdl/tb_tb_common_adder_tree.vhd
tb/vhdl/tb_tb_common_add_sub.vhd
- tb/vhdl/tb_tb_common_mem_bus.vhd
- tb/vhdl/tb_tb_common_mem_master_mux.vhd
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
diff --git a/libraries/base/mm/hdllib.cfg b/libraries/base/mm/hdllib.cfg
index b3180241c7..9fd9d7e678 100644
--- a/libraries/base/mm/hdllib.cfg
+++ b/libraries/base/mm/hdllib.cfg
@@ -8,21 +8,34 @@ synth_files =
src/vhdl/mm_fields.vhd
tb/vhdl/mm_file_pkg.vhd
tb/vhdl/mm_file_unb_pkg.vhd
+
src/verilog/timeout.v
src/verilog/wbs_arbiter.v
src/vhdl/mm_arbiter.vhd
+
+ src/vhdl/mm_bus.vhd
+ src/vhdl/mm_master_mux.vhd
+ src/vhdl/mm_slave_mux.vhd
test_bench_files =
tb/vhdl/mm_file.vhd
tb/vhdl/tb_mm_file.vhd
+
+ tb/vhdl/mm_waitrequest_model.vhd
+ tb/vhdl/tb_mm_bus.vhd
+ tb/vhdl/tb_mm_master_mux.vhd
+
tb/vhdl/tb_tb_mm_file.vhd
+ tb/vhdl/tb_tb_mm_bus.vhd
+ tb/vhdl/tb_tb_mm_master_mux.vhd
regression_test_vhdl =
tb/vhdl/tb_tb_mm_file.vhd
+ tb/vhdl/tb_tb_mm_bus.vhd
+ tb/vhdl/tb_tb_mm_master_mux.vhd
[modelsim_project_file]
[quartus_project_file]
-
--
GitLab