From 7383dcdcd5d12542a6ace5a758bff8b7582ef03c Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 13 Nov 2014 14:30:18 +0000
Subject: [PATCH] Move IP to /ip directory to be able to define IP specific
library in VHDL with its own hdllib.cfg.
---
.../ip_arria10/phy_10gbase_r/README.txt | 55 +++++++++++++++++++
.../ip_arria10/phy_10gbase_r/hdllib.cfg | 16 ++++++
.../phy_10gbase_r/{ => ip}/generate_ip.sh | 0
.../ip_arria10/phy_10gbase_r/ip/hdllib.cfg | 17 ++++++
.../{ => ip}/ip_arria10_phy_10gbase_r.qsys | 0
.../ip_arria10_phy_10gbase_r_top.vhd | 51 +++++++++++++++++
6 files changed, 139 insertions(+)
create mode 100644 libraries/technology/ip_arria10/phy_10gbase_r/README.txt
create mode 100644 libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
rename libraries/technology/ip_arria10/phy_10gbase_r/{ => ip}/generate_ip.sh (100%)
create mode 100644 libraries/technology/ip_arria10/phy_10gbase_r/ip/hdllib.cfg
rename libraries/technology/ip_arria10/phy_10gbase_r/{ => ip}/ip_arria10_phy_10gbase_r.qsys (100%)
create mode 100644 libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
new file mode 100644
index 0000000000..450030a182
--- /dev/null
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -0,0 +1,55 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The phy_10gbase_r IP is new for Arria10. However it serves the similar purpose as the phy_xaui IP for Stratix IV.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+ ip/ip_arria10_phy_10gbase_r.qsys
+
+Therefore first the IP needs to be generated using:
+
+ ip/generate_ip.sh
+
+
+3) Compilation, simulation and verification
+
+The genrated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ ip/compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ ip/generated/ip_arria10_phy_10gbase_r.qip
+
+is included in the ip/hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Generated ip_arria10_phy_10gbase_r.vhd uses IP specific library ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+
+ The ip/hdllib.cfg defines the IP specific library to make it known:
+
+ hdl_lib_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+ hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+
+ The ip_arria10_phy_10gbase_r_top.vhd wrapper makes the IP accessible via ip_arria10_phy_10gbase_r_lib, to
+ avoid that the IP specific library needs to be used at the technology independent level.
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
new file mode 100644
index 0000000000..1e3aa949f7
--- /dev/null
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_phy_10gbase_r
+hdl_library_clause_name = ip_arria10_phy_10gbase_r_lib
+hdl_lib_uses = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ ip_arria10_phy_10gbase_r_top.vhd
+
+test_bench_files =
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10/phy_10gbase_r/ip/generate_ip.sh
similarity index 100%
rename from libraries/technology/ip_arria10/phy_10gbase_r/generate_ip.sh
rename to libraries/technology/ip_arria10/phy_10gbase_r/ip/generate_ip.sh
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/ip/hdllib.cfg
new file mode 100644
index 0000000000..011b0f78f8
--- /dev/null
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+hdl_lib_uses =
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/ip/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =
+
+quartus_qip_files =
+ generated/ip_arria10_phy_10gbase_r.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys b/libraries/technology/ip_arria10/phy_10gbase_r/ip/ip_arria10_phy_10gbase_r.qsys
similarity index 100%
rename from libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
rename to libraries/technology/ip_arria10/phy_10gbase_r/ip/ip_arria10_phy_10gbase_r.qsys
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
new file mode 100644
index 0000000000..7a728bacc9
--- /dev/null
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
@@ -0,0 +1,51 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for generated ip_arria10_phy_10gbase_r.vhd
+-- Description:
+-- This wrapper avoids the need to vmap the ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140 library
+-- in the technology independent library that instantiate this IP.
+-- Remarks:
+-- . Manually created from generated ip_arria10_phy_10gbase_r.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140;
+
+entity ip_arria10_phy_10gbase_r_top is
+ port (
+
+
+ );
+end ip_arria10_phy_10gbase_r_top;
+
+architecture str of ip_arria10_phy_10gbase_r_top is
+begin
+
+ u_ip_arria10_phy_10gbase_r : entity ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140.ip_arria10_phy_10gbase_r
+ port map (
+
+
+ );
+
+end str;
--
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