From 735d4eda24a22ae5dfb34073d3a657b3eecb9f9b Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 9 Aug 2023 15:13:12 +0200
Subject: [PATCH] Use or define c_data_w = 2 * g_dsp_data_w.
---
libraries/base/reorder/src/vhdl/reorder_col.vhd | 6 +++---
.../base/reorder/src/vhdl/reorder_matrix.vhd | 2 +-
.../base/reorder/src/vhdl/reorder_retreive.vhd | 8 ++++----
.../base/reorder/src/vhdl/reorder_row_select.vhd | 10 +++++-----
.../tb/vhdl/tb_reorder_col_wide_row_select.vhd | 16 +++++++---------
5 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index 1c7d65153a..e4805d9aaf 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -62,7 +62,7 @@ entity reorder_col is
generic (
g_technology : natural := c_tech_select_default;
g_use_output_rl_adapter : boolean := false; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
- g_dsp_data_w : natural := 18;
+ g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
g_nof_ch_in : natural := 512;
g_nof_ch_sel : natural := 252; -- g_nof_ch_sel < g_nof_ch_in
g_select_file_name : string := "UNUSED";
@@ -87,12 +87,12 @@ entity reorder_col is
);
end reorder_col;
-
architecture str of reorder_col is
+ constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
constant c_store_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_in),
- dat_w => c_nof_complex * g_dsp_data_w,
+ dat_w => c_data_w,
nof_dat => g_nof_ch_in,
init_sl => '0'); -- ST side : stat_mosi
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 73ceaf6250..a656ab8152 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -60,7 +60,7 @@ entity reorder_matrix is
g_nof_inputs : natural := 24;
g_nof_internals : natural := 64;
g_nof_outputs : natural := 64;
- g_dsp_data_w : natural := 8;
+ g_dsp_data_w : natural := 8; -- complex data width, = c_data_w / 2
g_frame_size_in : natural := 64;
g_frame_size_out : natural := 128;
g_reorder_in_file_name : string := "UNUSED"; -- path_to_file.hex
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index 4f1c3761e2..12ddc0c358 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -43,10 +43,9 @@ use dp_lib.dp_stream_pkg.all;
-- reorder_col can store a frame and retrieve it immediately in any order, so worst
-- case the last stored data can be retrieved first.
-
entity reorder_retrieve is
generic (
- g_dsp_data_w : natural;
+ g_dsp_data_w : natural; -- complex data width, = c_data_w / 2
g_nof_ch_in : natural;
g_nof_ch_sel : natural
);
@@ -75,6 +74,7 @@ end reorder_retrieve;
architecture rtl of reorder_retrieve is
+ constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
constant c_retrieve_lat : natural := 2; -- fixed 1 for select buf read + 1 for store buf read
signal ch_cnt : integer range 0 to g_nof_ch_sel - 1;
@@ -159,9 +159,9 @@ begin
retrieve_mosi.address <= RESIZE_MEM_ADDRESS(select_miso.rddata(ceil_log2(g_nof_ch_in) - 1 downto 0));
-- The output_sosi has RL=2, because of the read accesses to the select buf followed by the read access to the store buf, both with read latency is 1, so c_retrieve_lat=2
- output_sosi.re <= RESIZE_DP_DSP_DATA(retrieve_miso.rddata( g_dsp_data_w - 1 downto 0));
+ output_sosi.re <= RESIZE_DP_DSP_DATA(retrieve_miso.rddata( g_dsp_data_w - 1 downto 0));
output_sosi.im <= RESIZE_DP_DSP_DATA(retrieve_miso.rddata(c_nof_complex * g_dsp_data_w - 1 downto g_dsp_data_w));
- output_sosi.data <= RESIZE_DP_DATA(retrieve_miso.rddata( c_nof_complex * g_dsp_data_w - 1 downto 0));
+ output_sosi.data <= RESIZE_DP_DATA(retrieve_miso.rddata(c_data_w - 1 downto 0));
output_sosi.valid <= retrieve_miso.rdval;
output_sosi.sop <= retrieve_sop_dly(c_retrieve_lat);
output_sosi.eop <= retrieve_eop_dly(c_retrieve_lat);
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 21722318aa..6221cfd293 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -42,7 +42,7 @@ use technology_lib.technology_select_pkg.all;
entity reorder_row_select is
generic (
g_technology : natural := c_tech_select_default;
- g_dsp_data_w : natural := 16;
+ g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
g_pipeline_in : natural := 1; -- pipeline in_data
@@ -87,8 +87,9 @@ begin
-- selection buffer.
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
- reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <= input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
- input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
+ reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
+ input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
+ input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
end generate;
---------------------------------------------------------------
@@ -114,7 +115,6 @@ begin
out_data => reorder_out_dat
);
-
---------------------------------------------------------------
-- REGISTERING AND PIPELINING
--
@@ -133,7 +133,7 @@ begin
-- Merge data output to the outgoing SOSI record.
for I in g_nof_outputs - 1 downto 0 loop
v.output_sosi_arr(I) := r.pipe_sosi_2arr(c_tot_pipeline-1)(0);
- v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w));
+ v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w));
v.output_sosi_arr(I).re := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - g_dsp_data_w - 1 downto I * c_data_w));
end loop;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 181d41c418..319940ecab 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -74,7 +74,7 @@ entity tb_reorder_col_wide_row_select is
generic(
g_nof_inputs : natural := 6; -- also nof rows
g_nof_outputs : natural := 2;
- g_dsp_data_w : natural := 16;
+ g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
g_nof_sync : natural := 5;
g_nof_block_per_sync : natural := 4;
g_nof_ch_in : natural := 1024; -- nof input words per block, identical for all input streams.
@@ -91,6 +91,9 @@ end tb_reorder_col_wide_row_select;
architecture tb of tb_reorder_col_wide_row_select is
+ constant c_use_complex : boolean := true;
+ constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
+
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -117,9 +120,8 @@ architecture tb of tb_reorder_col_wide_row_select is
signal bsn : natural := 10;
signal in_sosi_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_sosi_rst);
-
signal out_siso_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0) := (others => c_dp_siso_rdy);
- signal col_wide_select_sosi_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
+ signal col_wide_select_sosi_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0);
signal dly_out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0);
@@ -276,13 +278,13 @@ begin
end process;
end generate;
-
u_dut_col : entity work.reorder_col_wide_select
generic map (
g_nof_inputs => g_nof_inputs,
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => g_nof_ch_in,
- g_nof_ch_sel => c_nof_ch_sel
+ g_nof_ch_sel => c_nof_ch_sel,
+ g_use_complex => c_use_complex
)
port map (
dp_rst => rst,
@@ -294,7 +296,6 @@ begin
-- Streaming
input_sosi_arr => in_sosi_arr,
-
output_sosi_arr => col_wide_select_sosi_arr
);
@@ -315,10 +316,7 @@ begin
-- Streaming
input_sosi_arr => col_wide_select_sosi_arr,
-
output_sosi_arr => out_sosi_arr
);
-
-
end tb;
--
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