From 734dc3db236afa0e2259f738332dadf54095200b Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 10 Dec 2014 15:22:33 +0000
Subject: [PATCH] added the wrappers for pll_clk25 (arria10 only)
---
libraries/technology/pll/hdllib.cfg | 3 +-
libraries/technology/pll/tech_pll_clk25.vhd | 63 +++++++++++++++++++
.../technology/pll/tech_pll_component_pkg.vhd | 13 ++++
3 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 libraries/technology/pll/tech_pll_clk25.vhd
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index a564f15450..105d9f4bf5 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_pll
hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 common
+hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 ip_arria10_pll_clk25 common
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
@@ -11,5 +11,6 @@ synth_files =
tech_pll_clk200.vhd
tech_pll_clk200_p6.vhd
tech_pll_xgmii_mac_clocks.vhd
+ tech_pll_clk25.vhd
test_bench_files =
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
new file mode 100644
index 0000000000..5d1bd1c78d
--- /dev/null
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -0,0 +1,63 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_pll_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_pll_clk25_altera_iopll_140;
+
+ENTITY tech_pll_clk25 IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default
+ );
+ PORT (
+ areset : IN STD_LOGIC := '0';
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ c2 : OUT STD_LOGIC ;
+ c3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END tech_pll_clk25;
+
+ARCHITECTURE str OF tech_pll_clk25 IS
+
+BEGIN
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_pll_clk25
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 1fa2f09dd7..1d1ab71938 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -123,6 +123,19 @@ PACKAGE tech_pll_component_pkg IS
locked : OUT STD_LOGIC
);
END COMPONENT;
+
+ COMPONENT ip_arria10_pll_clk25 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
END tech_pll_component_pkg;
--
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