From 7339ea717b40e621947a769fffeeed4cfbe7e030 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 14 Jan 2021 18:20:06 +0100
Subject: [PATCH] Made tb_pfs simulate ok and made pft2 compile ok (tb_pft
input sig files still need to be regenerated with tb/data/tc.tcl.
---
applications/lofar1/pfs/hdllib.cfg | 4 +-
.../lofar1/pfs/src/vhdl/pfs_coefsbuf(str).vhd | 20 +--
.../lofar1/pfs/src/vhdl/pfs_filter(rtl).vhd | 9 +-
applications/lofar1/pfs/tb/vhdl/tb_pfs.vhd | 7 ++
applications/lofar1/pft2/hdllib.cfg | 5 +-
.../lofar1/pft2/src/vhdl/pft_bf(rtl).vhd | 114 ++++++++++++------
.../lofar1/pft2/src/vhdl/pft_bf_fw(rtl).vhd | 93 +++++++++-----
.../lofar1/pft2/src/vhdl/pft_buffer(rtl).vhd | 49 ++++++--
.../pft2/src/vhdl/pft_separate(rtl).vhd | 82 +++++++++----
.../lofar1/pft2/src/vhdl/pft_stage(str).vhd | 4 +-
.../lofar1/pft2/src/vhdl/pft_tmult(rtl).vhd | 52 +++++---
.../lofar1/pft2/src/vhdl/pft_top(str).vhd | 38 +-----
applications/lofar1/pft2/tb/vhdl/tb_pft2.vhd | 16 +--
13 files changed, 311 insertions(+), 182 deletions(-)
diff --git a/applications/lofar1/pfs/hdllib.cfg b/applications/lofar1/pfs/hdllib.cfg
index 9c2f5dcb99..106f0dc0d5 100644
--- a/applications/lofar1/pfs/hdllib.cfg
+++ b/applications/lofar1/pfs/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = pfs
hdl_library_clause_name = pfs_lib
-hdl_lib_uses_synth = common
+hdl_lib_uses_synth = common common_mult
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -25,6 +25,6 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
-
+ src/data data
[ise_project_file]
diff --git a/applications/lofar1/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 9797804cf9..73b65ff9f5 100644
--- a/applications/lofar1/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -1,26 +1,30 @@
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
ARCHITECTURE str OF pfs_coefsbuf IS
+ CONSTANT c_coefs_rom : t_c_mem := (latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0');
+
BEGIN
rom : ENTITY common_lib.common_rom
GENERIC MAP (
- g_dat_w => g_data_w,
- g_adr_w => g_addr_w,
- g_nof_words => g_nof_coefs,
- --g_init_file => "../../../../pfs/src/data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- g_init_file => "../../../../../pfs/src/data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+ g_ram => c_coefs_rom,
+ g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
)
PORT MAP (
rst => rst,
clk => clk,
- in_adr => addr,
- out_dat => data
+ rd_adr => addr,
+ rd_dat => data
);
END str;
diff --git a/applications/lofar1/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/pfs/src/vhdl/pfs_filter(rtl).vhd
index 7ab30215ba..2613953548 100644
--- a/applications/lofar1/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -1,4 +1,4 @@
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, common_mult_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
@@ -34,11 +34,14 @@ BEGIN
gen : FOR i IN 0 TO 7 GENERATE
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
- MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
+ --MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
+ MULT_ADD : ENTITY common_mult_lib.common_mult_add -- rtl
GENERIC MAP (
g_in_a_w => g_taps_w,
g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w+g_taps_w+1
+ g_out_dat_w => g_coef_w+g_taps_w+1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
)
PORT MAP (
clk => clk,
diff --git a/applications/lofar1/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/pfs/tb/vhdl/tb_pfs.vhd
index 440ab1d030..5e860b2533 100644
--- a/applications/lofar1/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/pfs/tb/vhdl/tb_pfs.vhd
@@ -1,3 +1,10 @@
+-- Usage:
+-- > as 5
+-- > run 100 us
+-- In Wave Window:
+-- . Copy pfs_dat_x
+-- . View pfs_dat_x in decimal radix and analog format (right click)
+
LIBRARY IEEE, pfs_lib, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
diff --git a/applications/lofar1/pft2/hdllib.cfg b/applications/lofar1/pft2/hdllib.cfg
index b75baaf241..e828e3bb91 100644
--- a/applications/lofar1/pft2/hdllib.cfg
+++ b/applications/lofar1/pft2/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = pft2
hdl_library_clause_name = pft2_lib
-hdl_lib_uses_synth = common
+hdl_lib_uses_synth = common common_mult
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -28,7 +28,6 @@ synth_files =
src/vhdl/pft_separate(rtl).vhd
src/vhdl/pft.vhd
src/vhdl/pft(str).vhd
- ../coregen/pfft.vhd
src/vhdl/pft_top.vhd
src/vhdl/pft_top(str).vhd
@@ -40,6 +39,6 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
-
+ tb/data data
[ise_project_file]
diff --git a/applications/lofar1/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/pft2/src/vhdl/pft_bf(rtl).vhd
index 14852ea239..7ef1dde1e4 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -216,55 +216,96 @@ BEGIN
-- Adds/ Subs ------------------------------------------------------------------
- cadd : ENTITY common_lib.common_caddsub
+-- Intel Altera lmp_add_sub carry in:
+-- ADD: out = a + b + cin => cin = '0' to have out = a + b
+-- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ --cadd : ENTITY common_lib.common_caddsub
+ --GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "ADD"
+ --)
+ --PORT MAP (
+ -- in_ar => add_ar,
+ -- in_ai => add_ai,
+ -- in_br => add_br,
+ -- in_bi => add_bi,
+ -- in_cr => '0',
+ -- in_ci => '0',
+ -- out_cr => add_cr,
+ -- out_ci => add_ci,
+ -- clk => clk,
+ -- rst => rst
+ --);
+
+ cadd : ENTITY common_complex_add_sub
GENERIC MAP (
- g_in_a_w => c_dat_w,
- g_in_b_w => c_dat_w,
- g_out_c_w => c_dat_w,
- g_pipeline => c_add_pipeline,
- g_add_sub => "ADD"
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- in_cr => '0',
- in_ci => '0',
- out_cr => add_cr,
- out_ci => add_ci,
- clk => clk,
- rst => rst
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
);
-
- csub : ENTITY common_lib.common_caddsub
+
+-- csub : ENTITY common_lib.common_caddsub
+-- GENERIC MAP (
+-- g_in_a_w => c_dat_w,
+-- g_in_b_w => c_dat_w,
+-- g_out_c_w => c_dat_w,
+-- g_pipeline => c_add_pipeline,
+-- g_add_sub => "SUB"
+-- )
+-- PORT MAP (
+-- in_ar => sub_ar,
+-- in_ai => sub_ai,
+-- in_br => sub_br,
+-- in_bi => sub_bi,
+-- in_cr => '1',
+-- in_ci => '1',
+-- out_cr => sub_cr,
+-- out_ci => sub_ci,
+-- clk => clk,
+-- rst => rst
+-- );
+
+ csub : ENTITY common_complex_add_sub
GENERIC MAP (
- g_in_a_w => c_dat_w,
- g_in_b_w => c_dat_w,
- g_out_c_w => c_dat_w,
- g_pipeline => c_add_pipeline,
- g_add_sub => "SUB"
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- in_cr => '1',
- in_ci => '1',
- out_cr => sub_cr,
- out_ci => sub_ci,
- clk => clk,
- rst => rst
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
);
-
+
-- regbank --------------------------------------------------------------------------
fifo_gen: IF c_regbank_size>8 GENERATE
fifo : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size,
- g_pft2_fifo => TRUE
+ g_nof_words => c_regbank_size
)
PORT MAP (
wr_dat => wr_dat,
@@ -276,6 +317,7 @@ BEGIN
);
END GENERATE fifo_gen;
+
fifo2_gen : IF c_regbank_size>c_pipeline AND c_regbank_size<=8 GENERATE
fifo2_reg : PROCESS (clk, rst)
BEGIN
diff --git a/applications/lofar1/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index 91eff02617..34e3539694 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -163,44 +163,81 @@ BEGIN
-- Adds/ Subs ----------------------------------------------------------------
- yr_cry <= NOT yr_add;
+-- Intel Altera lmp_add_sub carry in:
+-- ADD: out = a + b + cin => cin = '0' to have out = a + b
+-- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+-- yr_cry <= NOT yr_add;
- yr : ENTITY common_lib.common_addsub
+-- yr : ENTITY common_lib.common_addsub
+-- GENERIC MAP (
+-- g_in_a_w => g_in_dat_w,
+-- g_in_b_w => g_in_dat_w,
+-- g_out_c_w => g_out_dat_w,
+-- g_pipeline => c_add_pipeline,
+-- g_add_sub => "BOTH"
+-- )
+-- PORT MAP (
+-- in_a => yr_a,
+-- in_b => yr_b,
+-- in_cry => yr_cry,
+-- add_sub => yr_add,
+-- clk => clk,
+-- out_c => out_re
+-- );
+
+ yr : ENTITY common_add_sub
GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_c_w => g_out_dat_w,
- g_pipeline => c_add_pipeline,
- g_add_sub => "BOTH"
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_a => yr_a,
- in_b => yr_b,
- in_cry => yr_cry,
- add_sub => yr_add,
- clk => clk,
- out_c => out_re
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
);
-
- yi_cry <= NOT yi_add;
- yi : ENTITY common_lib.common_addsub
+-- yi_cry <= NOT yi_add;
+--
+-- yi : ENTITY common_lib.common_addsub
+-- GENERIC MAP (
+-- g_in_a_w => g_in_dat_w,
+-- g_in_b_w => g_in_dat_w,
+-- g_out_c_w => g_out_dat_w,
+-- g_pipeline => c_add_pipeline,
+-- g_add_sub => "BOTH"
+-- )
+-- PORT MAP (
+-- in_a => yi_a,
+-- in_b => yi_b,
+-- in_cry => yi_cry,
+-- add_sub => yi_add,
+-- clk => clk,
+-- out_c => out_im
+-- );
+
+ yi : ENTITY common_add_sub
GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_c_w => g_out_dat_w,
- g_pipeline => c_add_pipeline,
- g_add_sub => "BOTH"
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_a => yi_a,
- in_b => yi_b,
- in_cry => yi_cry,
- add_sub => yi_add,
- clk => clk,
- out_c => out_im
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
);
-
END rtl;
diff --git a/applications/lofar1/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/pft2/src/vhdl/pft_buffer(rtl).vhd
index fae28ce470..cf210fc486 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -5,6 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
LIBRARY common_lib;
USE common_lib.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
ARCHITECTURE rtl OF pft_buffer IS
@@ -12,6 +13,12 @@ ARCHITECTURE rtl OF pft_buffer IS
CONSTANT c_adr_w : NATURAL := g_fft_size_w+1;
CONSTANT c_nof_words : NATURAL := 2**c_adr_w;
+ CONSTANT c_ram : t_c_mem := (latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2*g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0');
+
SIGNAL rd_dat : STD_LOGIC_VECTOR(2*g_dat_w-1 DOWNTO 0);
SIGNAL wr_dat : STD_LOGIC_VECTOR(rd_dat'RANGE);
SIGNAL rd_adr_paged : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
@@ -98,22 +105,38 @@ BEGIN
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
- -- ram module
- ram : ENTITY common_lib.common_dpram
+-- -- ram module
+-- ram : ENTITY common_lib.common_dpram
+-- GENERIC MAP (
+-- g_dat_w => 2*g_dat_w,
+-- g_adr_w => c_adr_w,
+-- g_nof_words => c_nof_words
+-- )
+-- PORT MAP (
+-- rd_dat => rd_dat,
+-- rd_adr => rd_adr_paged,
+-- rd_en => rd_en,
+-- wr_dat => wr_dat,
+-- wr_adr => wr_adr_paged,
+-- wr_en => wr_en,
+-- clk => clk,
+-- rst => rst
+-- );
+
+ ram : ENTITY common_lib.common_ram_r_w
GENERIC MAP (
- g_dat_w => 2*g_dat_w,
- g_adr_w => c_adr_w,
- g_nof_words => c_nof_words
+ g_ram => c_ram
)
PORT MAP (
- rd_dat => rd_dat,
- rd_adr => rd_adr_paged,
- rd_en => rd_en,
- wr_dat => wr_dat,
- wr_adr => wr_adr_paged,
- wr_en => wr_en,
- clk => clk,
- rst => rst
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
);
+
END rtl;
diff --git a/applications/lofar1/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/pft2/src/vhdl/pft_separate(rtl).vhd
index 0e295ccefa..2c2322b280 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -170,36 +170,72 @@ BEGIN
nxt_out_val <= rdval_dly(rdval_dly'HIGH);
nxt_out_sync <= rdsync_dly(rdsync_dly'HIGH);
- add : ENTITY common_lib.common_addsub
+-- Intel Altera lmp_add_sub carry in:
+-- ADD: out = a + b + cin => cin = '0' to have out = a + b
+-- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+-- add : ENTITY common_lib.common_addsub
+-- GENERIC MAP (
+-- g_in_a_w => add0'LENGTH,
+-- g_in_b_w => add1'LENGTH,
+-- g_out_c_w => add_out'LENGTH,
+-- g_pipeline => c_add_delay-1,
+-- g_add_sub => "ADD"
+-- )
+-- PORT MAP (
+-- in_a => add0,
+-- in_b => add1,
+-- in_cry => '0',
+-- out_c => add_out,
+-- clk => clk
+-- );
+
+ add : ENTITY common_add_sub
GENERIC MAP (
- g_in_a_w => add0'LENGTH,
- g_in_b_w => add1'LENGTH,
- g_out_c_w => add_out'LENGTH,
- g_pipeline => c_add_delay-1,
- g_add_sub => "ADD"
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay-1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_a => add0,
- in_b => add1,
- in_cry => '0',
- out_c => add_out,
- clk => clk
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
);
-
- sub : ENTITY common_lib.common_addsub
+
+-- sub : ENTITY common_lib.common_addsub
+-- GENERIC MAP (
+-- g_in_a_w => sub0'LENGTH,
+-- g_in_b_w => sub1'LENGTH,
+-- g_out_c_w => sub_out'LENGTH,
+-- g_pipeline => c_add_delay-1,
+-- g_add_sub => "SUB"
+-- )
+-- PORT MAP (
+-- in_a => sub0,
+-- in_b => sub1,
+-- in_cry => '1',
+-- out_c => sub_out,
+-- clk => clk
+-- );
+
+ sub : ENTITY common_add_sub
GENERIC MAP (
- g_in_a_w => sub0'LENGTH,
- g_in_b_w => sub1'LENGTH,
- g_out_c_w => sub_out'LENGTH,
- g_pipeline => c_add_delay-1,
- g_add_sub => "SUB"
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay-1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
)
PORT MAP (
- in_a => sub0,
- in_b => sub1,
- in_cry => '1',
- out_c => sub_out,
- clk => clk
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
);
END rtl;
diff --git a/applications/lofar1/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/pft2/src/vhdl/pft_stage(str).vhd
index 149b2f4ffa..5fc944bfc7 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_stage(str).vhd
@@ -152,7 +152,7 @@ BEGIN
rst => rst
);
- u_rnd : ENTITY common_lib.common_cround
+ u_rnd : ENTITY common_lib.common_complex_round
GENERIC MAP (
g_representation => "SIGNED",
g_round => TRUE,
@@ -187,4 +187,4 @@ BEGIN
END GENERATE;
-END str;
\ No newline at end of file
+END str;
diff --git a/applications/lofar1/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/pft2/src/vhdl/pft_tmult(rtl).vhd
index f643328ccb..07dc3b9732 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -23,8 +23,10 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
+LIBRARY common_mult_lib;
LIBRARY common_lib;
-USE common_lib.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
ARCHITECTURE rtl OF pft_tmult IS
@@ -35,15 +37,25 @@ ARCHITECTURE rtl OF pft_tmult IS
CONSTANT c_coeff_w : NATURAL := 16;
CONSTANT c_mult_out_w : NATURAL := c_mult_in_w + c_coeff_w-1;
--- CONSTANT c_twid_file : STRING :=
--- "../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
--- & "_" & NATURAL'IMAGE(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ CONSTANT c_twid_rom : t_c_mem := (latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2*c_coeff_w, -- complex
+ nof_dat => 3*c_nof_twids/4, -- <= 2**g_addr_w
+ init_sl => '0');
+
CONSTANT c_twid_file : STRING :=
- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+ "data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ & "_" & NATURAL'IMAGE(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --CONSTANT c_twid_file : STRING :=
+ -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
CONSTANT c_read_pipeline : NATURAL := 1;
- CONSTANT c_mult_pipeline : NATURAL := 3;
+ CONSTANT c_mult_pipeline_input : NATURAL := 1; -- 0 or 1
+ CONSTANT c_mult_pipeline_product : NATURAL := 0; -- 0 or 1
+ CONSTANT c_mult_pipeline_adder : NATURAL := 1; -- 0 or 1
+ CONSTANT c_mult_pipeline_output : NATURAL := 1; -- >= 0
+ CONSTANT c_mult_pipeline : NATURAL := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
CONSTANT c_round_pipeline_in : NATURAL := 1;
CONSTANT c_round_pipeline_out : NATURAL := 1;
CONSTANT c_round_pipeline : NATURAL := c_round_pipeline_in + c_round_pipeline_out;
@@ -119,19 +131,17 @@ BEGIN
u_coeff : ENTITY common_lib.common_rom
GENERIC MAP (
- g_dat_w => coeff_dat'LENGTH,
- g_adr_w => adr'LENGTH,
- g_nof_words => 3*c_nof_twids/4,
+ g_ram => c_twid_rom,
g_init_file => c_twid_file
)
PORT MAP (
rst => rst,
clk => clk,
- in_adr => adr,
- out_dat => coeff_dat
+ rd_adr => adr,
+ rd_dat => coeff_dat
);
- u_rnd1 : ENTITY common_lib.common_cround
+ u_rnd1 : ENTITY common_lib.common_complex_round
GENERIC MAP (
g_representation => "SIGNED",
g_round => TRUE,
@@ -149,16 +159,18 @@ BEGIN
clk => clk
);
- -- complex multiplier: computes a * b
- --u_cmult : ENTITY common_lib.common_cmult(str)
- u_cmult : ENTITY common_lib.common_cmult(virtex)
+ u_cmult : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP (
+ g_variant => "IP",
g_in_a_w => c_mult_in_w,
g_in_b_w => c_coeff_w,
g_out_p_w => c_mult_out_w,
- g_pipeline => c_mult_pipeline,
- g_conjugate_b => FALSE
- )
+ g_conjugate_b => FALSE,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
PORT MAP (
in_ar => mult_in_re,
in_ai => mult_in_im,
@@ -169,7 +181,7 @@ BEGIN
clk => clk
);
- u_rnd2 : ENTITY common_lib.common_cround
+ u_rnd2 : ENTITY common_lib.common_complex_round
GENERIC MAP (
g_representation => "SIGNED",
g_round => TRUE,
diff --git a/applications/lofar1/pft2/src/vhdl/pft_top(str).vhd b/applications/lofar1/pft2/src/vhdl/pft_top(str).vhd
index decf9cf3d3..50dd0554d9 100644
--- a/applications/lofar1/pft2/src/vhdl/pft_top(str).vhd
+++ b/applications/lofar1/pft2/src/vhdl/pft_top(str).vhd
@@ -5,8 +5,6 @@ USE common_lib.common_pkg.ALL;
ARCHITECTURE str OF pft_top IS
- CONSTANT c_use_coregen_pfft : BOOLEAN := FALSE;
-
SIGNAL reg_in_re : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL reg_in_im : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL reg_in_val : STD_LOGIC;
@@ -38,7 +36,6 @@ BEGIN
END IF;
END PROCESS;
- gen_own : IF c_use_coregen_pfft = FALSE GENERATE
u_pft : ENTITY pft2_lib.pft
GENERIC MAP (
g_fft_size_w => g_fft_size_w,
@@ -59,36 +56,5 @@ BEGIN
clk => clk,
rst => rst
);
- END GENERATE;
-
- gen_cg : IF c_use_coregen_pfft = TRUE GENERATE
- pfft_in_sync <= reg_in_sync;
- pfft_in_re <= RESIZE_SVEC(reg_in_re, pfft_in_re'LENGTH);
- pfft_in_im <= RESIZE_SVEC(reg_in_im, pfft_in_im'LENGTH);
- d_out_re <= RESIZE_SVEC(pfft_out_re, d_out_re'LENGTH);
- d_out_im <= RESIZE_SVEC(pfft_out_im, d_out_im'LENGTH);
-
- u_pfft : ENTITY pft2_lib.pfft
- PORT MAP (
- clk => clk,
- sclr => rst,
- fwd_inv => '1',
- fwd_inv_we => '0',
- scale_sch => "1010101011",
- scale_sch_we => '0',
- start => pfft_in_sync,
- xn_re => pfft_in_re,
- xn_im => pfft_in_im,
- rfd => OPEN,
- dv => d_out_val,
- done => OPEN,
- busy => OPEN,
- edone => d_out_sync,
- xn_index => OPEN,
- xk_im => pfft_out_re,
- xk_re => pfft_out_im,
- xk_index => OPEN
- );
- END GENERATE;
-
-END str;
\ No newline at end of file
+
+END str;
diff --git a/applications/lofar1/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/pft2/tb/vhdl/tb_pft2.vhd
index 7488f64e57..fe065916f2 100644
--- a/applications/lofar1/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/pft2/tb/vhdl/tb_pft2.vhd
@@ -32,7 +32,7 @@ ENTITY tb_pft2 IS
g_fft_size_w : NATURAL := 10;
g_in_dat_w : NATURAL := 18;
g_out_dat_w : NATURAL := 18;
- g_tst_data_dir : STRING := "../../../../rsp/tb/tc/5. Datapath/5.2 PFT/"
+ g_tst_data_dir : STRING := "data/"
);
END tb_pft2;
@@ -305,7 +305,7 @@ BEGIN
g_file_name => c_file_pft_in_x,
g_file_repeat => c_repeat,
g_nof_data => 1,
- g_data_w => g_in_dat_w,
+ g_data_width => g_in_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -321,7 +321,7 @@ BEGIN
g_file_name => c_file_pft_in_y,
g_file_repeat => c_repeat,
g_nof_data => 1,
- g_data_w => g_in_dat_w,
+ g_data_width => g_in_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -342,7 +342,7 @@ BEGIN
g_file_name => c_file_pft_ref_x_re,
g_file_repeat => 1,
g_nof_data => 1,
- g_data_w => c_file_pft_dat_w,
+ g_data_width => c_file_pft_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -358,7 +358,7 @@ BEGIN
g_file_name => c_file_pft_ref_x_im,
g_file_repeat => 1,
g_nof_data => 1,
- g_data_w => c_file_pft_dat_w,
+ g_data_width => c_file_pft_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -374,7 +374,7 @@ BEGIN
g_file_name => c_file_pft_ref_y_re,
g_file_repeat => 1,
g_nof_data => 1,
- g_data_w => c_file_pft_dat_w,
+ g_data_width => c_file_pft_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -390,7 +390,7 @@ BEGIN
g_file_name => c_file_pft_ref_y_im,
g_file_repeat => 1,
g_nof_data => 1,
- g_data_w => c_file_pft_dat_w,
+ g_data_width => c_file_pft_dat_w,
g_data_type => "SIGNED"
)
PORT MAP (
@@ -579,4 +579,4 @@ BEGIN
nxt_out_y_im <= 0 WHEN out_val='0' ELSE TO_INTEGER(SIGNED(out_im)) WHEN toggle='1' ELSE out_y_im;
END GENERATE;
-END tb;
\ No newline at end of file
+END tb;
--
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