diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 0eaa2d444ed0bd11b1dc0e7e83300c66e5ed37dc..463cea6bfc723f2a13e538b43863da536af5746f 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -19,7 +19,7 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, ddr3_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -27,7 +27,8 @@ USE common_lib.common_mem_pkg.ALL;
 USE unb1_board_lib.unb1_board_pkg.ALL;
 USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
-USE ddr3_lib.ddr3_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;           
 
 ENTITY unb1_ddr3 IS
   GENERIC (
@@ -38,13 +39,7 @@ ENTITY unb1_ddr3 IS
     g_stamp_date    : NATURAL      := 0;     -- Date (YYYYMMDD)
     g_stamp_time    : NATURAL      := 0;     -- Time (HHMMSS)
     g_stamp_svn     : NATURAL      := 0;     -- SVN revision  
-    g_nof_MB        : NATURAL      := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
-    g_use_MB_I      : NATURAL      := 1;              -- 1: use MB_I  0: do not use
-    g_use_MB_II     : NATURAL      := 1;              -- 1: use MB_II 0: do not use
-    g_ddr           : t_c_ddr3_phy := c_ddr3_phy_4g;
-    g_mts           : NATURAL      := 800;
-    g_aux           : t_c_unb1_board_aux  := c_unb1_board_aux;
-    g_st_dat_w      : NATURAL      := 64             -- Any power of two 8..256
+    g_st_dat_w      : NATURAL      := 64     -- Any power of two 8..256
   );
   PORT (
     -- GENERAL
@@ -69,14 +64,9 @@ ENTITY unb1_ddr3 IS
     ETH_SGOUT              : OUT   STD_LOGIC;
     
     -- SO-DIMM Memory Bank I
-    MB_I_IN                : IN    t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);     
-    MB_I_IO                : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); 
-    MB_I_OU                : OUT   t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0); 
-                                                                                             
-    -- SO-DIMM Memory Bank II                                                                    
-    MB_II_IN               : IN    t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
-    MB_II_IO               : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
-    MB_II_OU               : OUT   t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0)   
+    MB_I_IN                : IN    t_tech_ddr3_phy_in;    
+    MB_I_IO                : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU                : OUT   t_tech_ddr3_phy_ou
   );
 END unb1_ddr3;
 
@@ -100,7 +90,9 @@ ARCHITECTURE str OF unb1_ddr3 IS
     -- END RECORD;
   CONSTANT c_use_phy        : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
   CONSTANT c_aux            : t_c_unb1_board_aux     := c_unb1_board_aux;
-  CONSTANT c_app_led_en     : BOOLEAN         := TRUE;
+  CONSTANT c_app_led_en     : BOOLEAN                := TRUE;
+  CONSTANT c_technology     : NATURAL                := c_tech_select_default;
+  CONSTANT c_tech_ddr       : t_c_tech_ddr           := c_tech_ddr3_4g_800m_master;
   
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
@@ -114,7 +106,9 @@ ARCHITECTURE str OF unb1_ddr3 IS
   
   SIGNAL dp_rst                     : STD_LOGIC;
   SIGNAL dp_clk                     : STD_LOGIC;
-  SIGNAL dp_pps                     : STD_LOGIC; 
+  SIGNAL dp_pps                     : STD_LOGIC;
+  
+  SIGNAL ddr_ref_rst                : STD_LOGIC; 
   
   SIGNAL this_chip_id               : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);  -- [2:0], so range 0-3 for FN and range 4-7 BN
   
@@ -155,12 +149,14 @@ ARCHITECTURE str OF unb1_ddr3 IS
   SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
   SIGNAL reg_unb_sens_miso          : t_mem_miso;
   
+  -- IO DDR register map 
+  SIGNAL reg_io_ddr_mosi            : t_mem_mosi;       
+  SIGNAL reg_io_ddr_miso            : t_mem_miso;       
+  
   -- MM registers
-  SIGNAL reg_diagnostics_mosi_arr   : t_mem_mosi_arr(0 TO g_nof_MB-1);
-  SIGNAL reg_diagnostics_miso_arr   : t_mem_miso_arr(0 TO g_nof_MB-1);
+  SIGNAL reg_diagnostics_mosi       : t_mem_mosi;
+  SIGNAL reg_diagnostics_miso       : t_mem_miso;
 
-  SIGNAL reg_ddr3_mosi_arr          : t_mem_mosi_arr(0 TO g_nof_MB-1);
-  SIGNAL reg_ddr3_miso_arr          : t_mem_miso_arr(0 TO g_nof_MB-1);
  
 BEGIN
 
@@ -170,19 +166,19 @@ BEGIN
   u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
   GENERIC MAP (
     -- General
-    g_sim                     => g_sim,
-    g_stamp_date              => g_stamp_date,
-    g_stamp_time              => g_stamp_time, 
-    g_stamp_svn               => g_stamp_svn,
-                              
-    g_design_name             => c_design_name,
-    g_design_note             => c_design_note, 
-    g_fw_version              => c_fw_version,
-    g_mm_clk_freq             => c_unb1_board_mm_clk_freq_50M,
-    g_app_led_red             => c_app_led_en,
-    g_app_led_green           => c_app_led_en,
-    g_use_phy                 => c_use_phy,
-    g_aux                     => c_aux
+    g_sim            => g_sim,
+    g_stamp_date     => g_stamp_date,
+    g_stamp_time     => g_stamp_time, 
+    g_stamp_svn      => g_stamp_svn,
+    g_design_name    => c_design_name,
+    g_design_note    => c_design_note, 
+    g_fw_version     => c_fw_version,
+    g_mm_clk_freq    => c_unb1_board_mm_clk_freq_50M,
+    g_dp_clk_use_pll => FALSE,
+    g_app_led_red    => c_app_led_en,
+    g_app_led_green  => c_app_led_en,
+    g_use_phy        => c_use_phy,
+    g_aux            => c_aux
   )
   PORT MAP (
     --
@@ -196,8 +192,8 @@ BEGIN
     mm_locked              => mm_locked,
     mm_rst                 => mm_rst,
     
-    dp_rst                 => dp_rst,
-    dp_clk                 => dp_clk,
+    dp_rst                 => OPEN,
+    dp_clk                 => OPEN,
     dp_pps                 => dp_pps,
     dp_rst_in              => dp_rst,
     dp_clk_in              => dp_clk,
@@ -216,6 +212,10 @@ BEGIN
     reg_wdi_mosi           => reg_wdi_mosi,
     reg_wdi_miso           => reg_wdi_miso,
 
+    -- . PPSH                                 
+    reg_ppsh_mosi          => reg_ppsh_mosi,
+    reg_ppsh_miso          => reg_ppsh_miso,    
+    
     -- system_info
     reg_unb_system_info_mosi => reg_unb_system_info_mosi,
     reg_unb_system_info_miso => reg_unb_system_info_miso, 
@@ -265,8 +265,7 @@ BEGIN
   GENERIC MAP(
     g_sim         => g_sim,         
     g_sim_unb_nr  => g_sim_unb_nr,  
-    g_sim_node_nr => g_sim_node_nr, 
-    g_nof_MB      => g_nof_MB
+    g_sim_node_nr => g_sim_node_nr
   )
   PORT MAP (
     -- GENERAL
@@ -284,6 +283,10 @@ BEGIN
     -- Manual WDI override                                
     reg_wdi_mosi             => reg_wdi_mosi,             
     reg_wdi_miso             => reg_wdi_miso,             
+    
+    -- . PPSH                                 
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso,    
                                                           
     -- system_info                                        
     reg_unb_system_info_mosi => reg_unb_system_info_mosi, 
@@ -296,12 +299,12 @@ BEGIN
     reg_unb_sens_miso        => reg_unb_sens_miso,        
 
     -- DDR3
-    reg_ddr3_mosi_arr        => reg_ddr3_mosi_arr, 
-    reg_ddr3_miso_arr        => reg_ddr3_miso_arr, 
+    reg_io_ddr_mosi          => reg_io_ddr_mosi, 
+    reg_io_ddr_miso          => reg_io_ddr_miso, 
                             
     -- Diagnostics          
-    reg_diagnostics_mosi_arr => reg_diagnostics_mosi_arr,
-    reg_diagnostics_miso_arr => reg_diagnostics_miso_arr,
+    reg_diagnostics_mosi     => reg_diagnostics_mosi,
+    reg_diagnostics_miso     => reg_diagnostics_miso,
 
     -- eth1g
     eth1g_tse_clk            => eth1g_tse_clk,      
@@ -315,40 +318,50 @@ BEGIN
     eth1g_ram_miso           => eth1g_ram_miso      
   );
   
-  u_node : ENTITY work.node_unb1_ddr3 
+  u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
   GENERIC MAP(
-    g_sim            => g_sim,       
-    g_nof_MB         => g_nof_MB,    
-    g_use_MB_I       => g_use_MB_I,  
-    g_use_MB_II      => g_use_MB_II, 
-    g_ddr            => g_ddr,       
-    g_mts            => g_mts,       
-    g_st_dat_w       => g_st_dat_w  
+    g_rst_level => '1',
+    g_delay_len => 40
   )
   PORT MAP(
+    clk     => CLK,
+    in_rst  => mm_rst,
+    out_rst => ddr_ref_rst
+  );    
+
+  u_node : ENTITY work.node_unb1_ddr3
+  GENERIC MAP (
+    g_sim        => g_sim, 
+    g_technology => c_technology,
+    g_tech_ddr   => c_tech_ddr,
+    g_st_dat_w   => g_st_dat_w  
+  )
+  PORT MAP (
     -- System
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => dp_rst,
-    dp_clk            => dp_clk,
+    mm_rst               => mm_rst,  
+    mm_clk               => mm_clk,  
+     
+    dp_rst               => dp_rst,  
+    dp_clk               => dp_clk,   
 
-    -- MM registers
-    reg_ddr3_mosi_arr => reg_ddr3_mosi_arr, 
-    reg_ddr3_miso_arr => reg_ddr3_miso_arr,  
-    
-    reg_diagnostics_mosi_arr => reg_diagnostics_mosi_arr,                    
-    reg_diagnostics_miso_arr => reg_diagnostics_miso_arr,  
+    ddr_ref_clk          => CLK,  
+    ddr_ref_rst          => ddr_ref_rst,  
                               
-    -- SO-DIMM Memory Bank I = ddr3_I
-    MB_I_in           =>  MB_I_IN, 
-    MB_I_io           =>  MB_I_IO, 
-    MB_I_ou           =>  MB_I_OU, 
-
-    -- SO-DIMM Memory Bank II = ddr3_II
-    MB_II_in          =>  MB_II_IN, 
-    MB_II_io          =>  MB_II_IO, 
-    MB_II_ou          =>  MB_II_OU 
-  );
+    -- Clock outputs          
+    ddr_out_clk          => dp_clk,  
+    ddr_out_rst          => dp_rst,  
+                             
+    -- MM interface     
+    reg_io_ddr_mosi      => reg_io_ddr_mosi,
+    reg_io_ddr_miso      => reg_io_ddr_miso,
     
+    reg_diagnostics_mosi => reg_diagnostics_mosi,
+    reg_diagnostics_miso => reg_diagnostics_miso,
+     
+    MB_I_IN              => MB_I_IN,     
+    MB_I_IO              => MB_I_IO, 
+    MB_I_OU              => MB_I_OU
+  );
+   
 END str;