diff --git a/libraries/technology/ip_stratixiv/phy_xaui/ip_stratixiv_phy_xaui_soft.qip b/libraries/technology/ip_stratixiv/phy_xaui/ip_stratixiv_phy_xaui_soft.qip
new file mode 100644
index 0000000000000000000000000000000000000000..6d73862e41aaa2f31c9ab144a9e25ddef22ea170
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/ip_stratixiv_phy_xaui_soft.qip
@@ -0,0 +1,72 @@
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_VERSION "11.1sp2"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_ENV "mwpim"
+
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VHDL_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft.vhd]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_xcvr_functions.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_functions.sv]
+#set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/hxaui_csr_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/hxaui_csr.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_phyreconfig.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_ch_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_lego.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_tgx_cdrauto.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_resync.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_selector.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_wait_generate.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_pcs.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_reset.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_8b10b_dec.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_channel_synch.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew_channel.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew_ram.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_invalid_code_det.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity_4b.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity_6b.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rate_match.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rate_match_ram.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rl_chk_6g.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_sm.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx_8b10b_enc.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx_idle_conv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/l_modules.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4_unit_lc_siv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4_unit_siv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4unit.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_pcs.ocp]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/sxaui.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/siv_xcvr_low_latency_phy_nr.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/siv_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name QIP_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xaui_phy_assignments.qip]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xaui_phy_top.sdc]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_siv.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_eyemon_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_dfe_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_basic_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_mutex_acq.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_dprio.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_arbiter.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_m2s.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/plain_files.txt]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/qencrypt_files.txt]
+
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_ENV "mwpim"