diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index f6fd854b56e7198a2197d8b247e73d66084324e8..d13cc53ef674de10e24ae66cbf38ab7a3f18e974 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = lofar2_unb2b_sdp_station_fsub
hdl_library_clause_name = lofar2_unb2b_sdp_station_fsub_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = eth
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -9,9 +9,11 @@ hdl_lib_technology = ip_arria10_e1sg
test_bench_files =
tb_lofar2_unb2b_sdp_station_fsub.vhd
+ tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
regression_test_vhdl =
tb_lofar2_unb2b_sdp_station_fsub.vhd
+ tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
[modelsim_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 71bdc1825f2cf5903367fa66df58739c4da2b886..44f22b5dbe0e4c6e6190adda0914f29621adfb2d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -107,19 +107,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub);
-- MM
- CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
- CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
- CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
- SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
-- WG
SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
@@ -144,8 +141,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
@@ -166,7 +163,6 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
@@ -180,7 +176,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
@@ -248,16 +244,17 @@ BEGIN
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
-
+
+ -- wait for pps
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
+
----------------------------------------------------------------------------
- -- Enable BS
+ -- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
----------------------------------------------------------------------------
-- Enable WG
@@ -280,20 +277,15 @@ BEGIN
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
- v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- Wait for enough WG data and start of sync interval
+
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
- ----------------------------------------------------------------------------
- -- Offload enable
- ----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
-
---------------------------------------------------------------------------
-- Read subband statistics
---------------------------------------------------------------------------
@@ -358,7 +350,7 @@ BEGIN
---------------------------------------------------------------------------
-- End Simulation
- ---------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ac3bffbe3e31ee2d4815f4d42c2d7bb2279103ec
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -0,0 +1,249 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_fsub capturing SST UDP offload packets.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable BSN source and enable UDP offload
+--
+-- 2) Verify ethernet statistics using eth_statistics, it checks the number of
+-- received packets and the total number of valid data. The content of the packets is not verified.
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_fsub_sst_offload IS
+END tb_lofar2_unb2b_sdp_station_fsub_sst_offload;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub_sst_offload IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 80; -- long enough to stream out udp data
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL eth_done : STD_LOGIC := '0';
+
+ -- . 1GbE output
+ CONSTANT c_eth_check_nof_packets : NATURAL := c_sdp_S_pn; -- received packets in 1 sync period
+ CONSTANT c_eth_header_size : NATURAL := 19; -- words
+ CONSTANT c_eth_crc_size : NATURAL := 1; -- word
+ CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w); -- 20 + 512 * 2 = 1044
+ CONSTANT c_eth_check_nof_valid : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;
+ CONSTANT c_eth_runtime_timeout : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done at the second sync interval
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_fsub : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+
+ ----------------------------------------------------------------------------
+ -- Offload enable
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+
+ -- wait for udp offload is done
+ proc_common_wait_until_high(ext_clk, eth_done);
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -------------------------------------------------------------------------
+ -- Verify proper DUT 1GbE offload output using Ethernet packet statistics
+ -------------------------------------------------------------------------
+ u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_valid
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index b39be046643051f7c1745c1ae6afb85c680caec1..d3198bf0d2b4db7888cd4efed534c3cdc08ca31d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -54,12 +54,13 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_nof_block_per_pps : NATURAL := 16;
- CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_pps);
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1) - 1); -- = full scale of WG
@@ -203,7 +204,7 @@ BEGIN
-- Enable BS
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_block_per_pps, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
-- Enable WG
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 1485e648eb28cfc11cd3a93743023ebd75e006f7..30ff635d11b41dea803c2aa1ce11dc937c199319 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -93,6 +93,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_bf_weight : NATURAL := 16;
CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
CONSTANT c_sdp_W_gn_id : NATURAL := 5;
+ CONSTANT c_sdp_W_statistic : NATURAL := 64;
CONSTANT c_sdp_W_sub_magnitude : NATURAL := 2;
CONSTANT c_sdp_W_sub_weight : NATURAL := 16;
CONSTANT c_sdp_W_subband : NATURAL := 18;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index 0856f4403c2e0b7ec01f825f9aa30ea6698d5f8a..ab23adb03f4bcb6c38f44f5a5d06e9f0e4e75275 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -43,7 +43,7 @@ ENTITY ctrl_unb2b_board IS
----------------------------------------------------------------------------
g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE;
- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
g_design_name : STRING := "UNUSED";
g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y