From 720496f7dc9967f05de751563cdee69944df1412 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Fri, 22 May 2015 15:58:07 +0000 Subject: [PATCH] Added fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL. --- .../technology/fractional_pll/hdllib.cfg | 12 ++++ .../tech_fractional_pll_clk200.vhd | 62 +++++++++++++++++++ .../tech_fractional_pll_component_pkg.vhd | 48 ++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 libraries/technology/fractional_pll/hdllib.cfg create mode 100644 libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd create mode 100644 libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg new file mode 100644 index 0000000000..6e2d1a2be2 --- /dev/null +++ b/libraries/technology/fractional_pll/hdllib.cfg @@ -0,0 +1,12 @@ +hdl_lib_name = tech_fractional_pll +hdl_library_clause_name = tech_fractional_pll_lib +hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 common +hdl_lib_uses_sim = + +hdl_lib_technology = + +synth_files = + tech_fractional_pll_component_pkg.vhd + tech_fractional_pll_clk200.vhd + +test_bench_files = diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd new file mode 100644 index 0000000000..b522e30977 --- /dev/null +++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY ieee, technology_lib; +USE ieee.std_logic_1164.all; +USE work.tech_fractional_pll_component_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; + +-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. +LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150; + +ENTITY tech_fractional_pll_clk200 IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default + ); + PORT ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; -- 200 MHz + c0 : OUT STD_LOGIC ; -- 200 MHz + c1 : OUT STD_LOGIC ; -- 200 MHz shifted 90 degrees + c2 : OUT STD_LOGIC ; -- 400 MHz + locked : OUT STD_LOGIC + ); +END tech_fractional_pll_clk200; + +ARCHITECTURE str OF tech_fractional_pll_clk200 IS + +BEGIN + + gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE + u0 : ip_arria10_fractional_pll_clk200 + PORT MAP ( + outclk0 => c0, -- outclk0.clk + outclk1 => c1, -- outclk1.clk + outclk2 => c2, -- outclk2.clk + pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy + pll_locked => locked, -- pll_locked.pll_locked + pll_powerdown => areset, -- pll_powerdown.pll_powerdown + pll_refclk0 => inclk0 -- pll_refclk0.clk + ); + END GENERATE; + +END ARCHITECTURE; diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd new file mode 100644 index 0000000000..d1c5fd2be3 --- /dev/null +++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: IP components declarations for various devices that get wrapped by the tech components + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE tech_fractional_pll_component_pkg IS + + ----------------------------------------------------------------------------- + -- ip_arria10 + ----------------------------------------------------------------------------- + + COMPONENT ip_arria10_fractional_pll_clk200 IS + PORT + ( + outclk0 : out std_logic; -- outclk0.clk + outclk1 : out std_logic; -- outclk1.clk + outclk2 : out std_logic; -- outclk2.clk + pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy + pll_locked : out std_logic; -- pll_locked.pll_locked + pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown + pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk + ); + END COMPONENT; + + +END tech_fractional_pll_component_pkg; + -- GitLab