diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 87ad9f4aa4f1d2d7fa917a208257c13f546f0779..a2de801831cbeb841c308ca7d2a6f12137cd2a8c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -204,13 +204,16 @@ BEGIN
-- . the input valid is always '1', even when there is no data
-----------------------------------------------------------------------------
- gen_force_valid : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
- p_sosi : PROCESS(rx_sosi_arr)
- BEGIN
- dp_shiftram_snk_in_arr(I) <= rx_sosi_arr(I);
- dp_shiftram_snk_in_arr(I).valid <= '1';
- END PROCESS;
- END GENERATE;
+ p_dp_shiftram_snk_in_arr : PROCESS(rx_sosi_arr)
+ BEGIN
+ dp_shiftram_snk_in_arr <= rx_sosi_arr;
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ -- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
+ dp_shiftram_snk_in_arr(I).data <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd-1 DOWNTO (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
+ -- Force valid.
+ dp_shiftram_snk_in_arr(I).valid <= '1';
+ END LOOP;
+ END PROCESS;
u_dp_shiftram : ENTITY dp_lib.dp_shiftram
diff --git a/boards/uniboard2c/designs/refdesigns/10G/README b/boards/uniboard2c/designs/refdesigns/10G/README
new file mode 100644
index 0000000000000000000000000000000000000000..800f85d01a48576fe3dd44b7a5b0271f30870258
--- /dev/null
+++ b/boards/uniboard2c/designs/refdesigns/10G/README
@@ -0,0 +1,10 @@
+These refdesigns are made with Quartus 15.1 Prime Standard Edition
+
+On dop428:
+
+Login as: hiemstra, select:
+UNB='1' (default), LOWCBF='2', newLOWCBF='3', LOWCBFprod='4', GIT='5', GITUNB='6', SKA='7', OPTANE='8' or GRATE='9': 1
+UNB is selected
+
+Then run as: run_quartus unb2
+
diff --git a/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.qar b/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.qar
new file mode 100644
index 0000000000000000000000000000000000000000..aae56faee9e299cac5f1c77e0e0fbc6716dd2c23
Binary files /dev/null and b/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.qar differ
diff --git a/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.sof.zip b/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.sof.zip
new file mode 100644
index 0000000000000000000000000000000000000000..5d0ef4181e9cc0aeaee1d71147eae4f84a22eebf
Binary files /dev/null and b/boards/uniboard2c/designs/refdesigns/10G/TTK_Arria10_10Gb_transceivers_24QSFP_24BCK.sof.zip differ
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index e95d804fc699c49196b5e95764f559a01854ca91..573c1a56f9f3c6b1f054c8b8d5af998d8b1ca4cc 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -227,7 +227,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_common_fanout_tree.vhd
tb/vhdl/tb_tb_common_multiplexer.vhd
tb/vhdl/tb_tb_common_operation_tree.vhd
- #tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd -- fails for unb2c
+ tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
tb/vhdl/tb_tb_common_reorder_symbol.vhd
tb/vhdl/tb_tb_common_rl.vhd
tb/vhdl/tb_tb_common_rl_register.vhd
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 0c4ce6f94ca7807fb3e5ce862cdc3210ba3efa8d..724281760afb7b26b69150853ab1ca7d9f862780 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -42,7 +42,7 @@ test_bench_files =
regression_test_vhdl =
tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
-# tb/vhdl/tb_tb_reorder_col.vhd -- fails in unb2c
+ tb/vhdl/tb_tb_reorder_col.vhd
[modelsim_project_file]
diff --git a/libraries/base/ss/hdllib.cfg b/libraries/base/ss/hdllib.cfg
index 5495225a46843b0bd87369f65a8c7a09676ad46b..9012550aa85e882e533a24727448e18ae6199a47 100644
--- a/libraries/base/ss/hdllib.cfg
+++ b/libraries/base/ss/hdllib.cfg
@@ -20,7 +20,7 @@ test_bench_files =
tb/vhdl/tb_tb_ss.vhd
regression_test_vhdl =
-# tb/vhdl/tb_tb_ss.vhd -- fails in unb2c
+ tb/vhdl/tb_tb_ss.vhd
[modelsim_project_file]
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index 0868b4a345d6c7658facb09bb30ed34fc25a07a4..fe84e21ca58d62cad52a94d62f450297d6ed2050 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -117,7 +117,7 @@ ENTITY tb_verify_pfb_wg IS
--g_sel_pfb : STRING := "PFB2";
-- WG
- g_subband_index_a : REAL := 61.1; -- 0:511
+ g_subband_index_a : REAL := 61.0; -- 0:511
g_subband_index_b : REAL := 61.0; -- 0:511
g_amplitude_a : REAL := 1.0; -- 1.0 is full scale
g_amplitude_b : REAL := 0.0; -- 1.0 is full scale
@@ -152,14 +152,14 @@ ENTITY tb_verify_pfb_wg IS
g_fil_backoff_w : NATURAL := 0; -- = 0, number of bits for input backoff to avoid output overflow
g_fil_in_dat_w : NATURAL := 14; -- = W_adc, number of input bits
- g_internal_dat_w : NATURAL := 17; -- = number of bits between fil and fft, use 0 to use maximum default:
+ g_internal_dat_w : NATURAL := 0; -- = number of bits between fil and fft, use 0 to use maximum default:
-- . WPFB : g_internal_dat_w <= g_fft_stage_dat_w - g_fft_guard_w in fft_r2_pipe
-- . PFB2 : g_internal_dat_w <= g_fft_stage_dat_w
-- FFT
g_fft_out_dat_w : NATURAL := 18; -- = W_subband, number of output bits
- g_fft_out_gain_w : NATURAL := 0; -- = 1, output gain factor applied after the last stage output, before requantization to out_dat_w
- g_fft_stage_dat_w : NATURAL := 18; -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
+ g_fft_out_gain_w : NATURAL := 1; -- = 1, output gain factor applied after the last stage output, before requantization to out_dat_w
+ g_fft_stage_dat_w : NATURAL := 27; -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
g_fft_guard_w : NATURAL := 1; -- = 2
g_switch_en : STD_LOGIC := '0'; -- two real input decorrelation option in PFB2
g_r2_mul_extra_w : NATURAL := 0; -- = 2, WPFB extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization in fft_r2_pipe in wpfb_unit_dev
@@ -246,8 +246,8 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
CONSTANT c_nof_channels : NATURAL := 2**c_wpfb.nof_chan; -- = 2**0 = 1, so no time multiplexing of inputs
CONSTANT c_nof_sync : NATURAL := 5; -- nof sync intervals to simulate
- CONSTANT c_pfb_sub_scaling : REAL := 2.0**REAL(g_fft_out_dat_w - g_fil_in_dat_w - 1); -- expected subband amplitude gain relative to input WG amplitude
- -- -1 for divide by 2 in two real input separate (Ampl --> Ampl/2)
+ CONSTANT c_pfb_sub_scaling : REAL := 2.0**REAL(g_fft_out_dat_w + g_fft_out_gain_w - g_fil_in_dat_w - 1); -- expected subband amplitude gain relative to input WG amplitude
+ -- -1 for divide by 2 in two real input separate (Ampl --> Ampl/2)
-- Subband at WG frequency
CONSTANT c_bin_a : NATURAL := NATURAL(FLOOR(g_subband_index_a));
CONSTANT c_bin_a_frac_en : BOOLEAN := g_subband_index_a > REAL(c_bin_a);
@@ -463,9 +463,13 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
SIGNAL sp_subband_powers_b : t_nat_real_arr(0 TO c_N_sub-1) := (OTHERS=>0.0);
SIGNAL sst_wg_power_a : REAL := 0.0; -- measured WG sine power at WG bin in SST
+ SIGNAL sst_wg_power_a_dB : REAL := 0.0; -- measured WG sine power at WG bin in SST in dB
SIGNAL sst_noise_a : REAL := 0.0; -- measured sum of noise power in all other bins in SST
+ SIGNAL sst_noise_a_dB : REAL := 0.0; -- measured sum of noise power in all other bins in SST in dB
SIGNAL sst_wg_power_b : REAL := 0.0; -- measured WG sine power at WG bin in SST
+ SIGNAL sst_wg_power_b_dB : REAL := 0.0; -- measured WG sine power at WG bin in SST in dB
SIGNAL sst_noise_b : REAL := 0.0; -- measured sum of noise power in all other bins in SST
+ SIGNAL sst_noise_b_dB : REAL := 0.0; -- measured sum of noise power in all other bins in SST in dB
-- SNR and WPFB processing gain
SIGNAL sst_measured_snr_a : REAL := 0.0;
@@ -938,6 +942,12 @@ BEGIN
END LOOP;
sst_noise_b <= v_sst_noise / REAL(c_N_sub - 1);
proc_common_wait_some_cycles(dp_clk, 1);
+
+ -- SST power in dB
+ sst_wg_power_a_dB <= 10.0 * LOG10(sst_wg_power_a + c_eps);
+ sst_wg_power_b_dB <= 10.0 * LOG10(sst_wg_power_b + c_eps);
+ sst_noise_a_dB <= 10.0 * LOG10(sst_noise_a + c_eps);
+ sst_noise_b_dB <= 10.0 * LOG10(sst_noise_b + c_eps);
-- Determine SNR in WG subband, using noise power in one subband
sst_measured_snr_a <= sst_wg_power_a / (sst_noise_a + c_eps); proc_common_wait_some_cycles(dp_clk, 1);
@@ -1025,9 +1035,9 @@ BEGIN
print_str(". fil_phase_Ts_a = " & real_to_str(fil_phase_Ts_a, 10, 3));
print_str("");
print_str("Powers:");
- print_str(". sst_wg_power_a = " & real_to_str(sst_wg_power_a, 15, 3));
- print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3));
- print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3)); -- FFT cross talk power from a to b (if g_amplitude_b = 0)
+ print_str(". sst_wg_power_a = " & real_to_str(sst_wg_power_a, 15, 3) & " = " & real_to_str(sst_wg_power_a_dB, 7, 2) & " [dB]");
+ print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]");
+ print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]"); -- FFT cross talk power from a to b (if g_amplitude_b = 0)
print_str("");
print_str("SNR and WPFB processing gain:");
print_str(". c_wg_snr_a_dB = " & real_to_str(c_wg_snr_a_dB, 7, 2) & " [dB]");
@@ -1067,9 +1077,9 @@ BEGIN
print_str(". cw_phase_Ts_b = " & real_to_str(cw_phase_Ts_b, 10, 3));
print_str(". fil_phase_Ts_b = " & real_to_str(fil_phase_Ts_b, 10, 3));
print_str("Powers:");
- print_str(". sst_wg_power_b = " & real_to_str(sst_wg_power_b, 15, 3));
- print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3));
- print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3)); -- FFT cross talk power from b to a (if g_amplitude_a = 0)
+ print_str(". sst_wg_power_b = " & real_to_str(sst_wg_power_b, 15, 3) & " = " & real_to_str(sst_wg_power_b_dB, 7, 2) & " [dB]");
+ print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]");
+ print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]"); -- FFT cross talk power from b to a (if g_amplitude_a = 0)
print_str("");
print_str("SNR and WPFB processing gain:");
print_str(". c_wg_snr_b_dB = " & real_to_str(c_wg_snr_b_dB, 7, 2) & " [dB]");
diff --git a/libraries/io/tr_10GbE/hdllib.cfg b/libraries/io/tr_10GbE/hdllib.cfg
index 54cb4c2231fd4901b47a77a0221911fe4da9391c..8030f1911dbc7862e363fd50b7588b8b5b833f29 100644
--- a/libraries/io/tr_10GbE/hdllib.cfg
+++ b/libraries/io/tr_10GbE/hdllib.cfg
@@ -14,7 +14,7 @@ test_bench_files =
tb/vhdl/tb_tb_tr_10GbE.vhd
regression_test_vhdl =
-# tb/vhdl/tb_tb_tr_10GbE.vhd -- fails in unb2c
+ tb/vhdl/tb_tb_tr_10GbE.vhd
[modelsim_project_file]
diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 2e4e4150d889ff951b799a0e470c39f3c70722cf..4c7a63445a617edfbe77926df45e4b1d38d32bba 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -26,7 +26,7 @@ test_bench_files =
tb_tb_tech_eth_10g.vhd
regression_test_vhdl =
-# tb_tb_tech_eth_10g.vhd -- fails in unb2c
+ tb_tb_tech_eth_10g.vhd
[modelsim_project_file]
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
index 7e4d82cefceacecd4814eb924098c5d4a2eea6a6..7ce0b6dba3b12c0443e089b4c50d445356b55c77 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -71,6 +71,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
+ read_during_write_mode_mixed_ports : string;
widthad_a : integer;
widthad_b : integer;
width_a : integer;
@@ -116,6 +117,7 @@ BEGIN
outdata_aclr_b => "NONE",
outdata_reg_b => c_outdata_reg_b,
power_up_uninitialized => "FALSE",
+ read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => g_adr_w,
widthad_b => g_adr_w,
width_a => g_dat_w,
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index 833ac0341320c43d29064b7ca3aac725d3c3bc49..caaf0ae91d4774cacc7096bbf23eec18cfacc121 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -80,6 +80,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crw_crw IS
power_up_uninitialized : string;
read_during_write_mode_port_a : string;
read_during_write_mode_port_b : string;
+ read_during_write_mode_mixed_ports : string;
widthad_a : integer;
widthad_b : integer;
width_a : integer;
@@ -137,6 +138,7 @@ BEGIN
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => g_adr_w,
widthad_b => g_adr_w,
width_a => g_dat_w,