diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd new file mode 100644 index 0000000000000000000000000000000000000000..206ac21148fb5f91d55e9a59a48f785dd29ca2ec --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_cr_cw IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + -- Write port clock domain + wr_rst : IN STD_LOGIC := '0'; + wr_clk : IN STD_LOGIC; + wr_clken : IN STD_LOGIC := '1'; + wr_en : IN STD_LOGIC := '0'; + wr_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + -- Read port clock domain + rd_rst : IN STD_LOGIC := '0'; + rd_clk : IN STD_LOGIC; + rd_clken : IN STD_LOGIC := '1'; + rd_en : IN STD_LOGIC := '1'; + rd_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + rd_val : OUT STD_LOGIC + ); +END common_ram_cr_cw; + + +ARCHITECTURE str OF common_ram_cr_cw IS + +BEGIN + + -- Dual clock domain + -- Use port a only for write in write clock domain + -- Use port b only for read in read clock domain + + u_cr_cw : ENTITY work.common_ram_crw_crw + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst_a => wr_rst, + rst_b => rd_rst, + clk_a => wr_clk, + clk_b => rd_clk, + clken_a => wr_clken, + clken_b => rd_clken, + wr_en_a => wr_en, + wr_en_b => '0', + wr_dat_a => wr_dat, + wr_dat_b => (OTHERS=>'0'), + adr_a => wr_adr, + adr_b => rd_adr, + rd_en_a => '0', + rd_en_b => rd_en, + rd_dat_a => OPEN, + rd_dat_b => rd_dat, + rd_val_a => OPEN, + rd_val_b => rd_val + ); + +END str; diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd new file mode 100644 index 0000000000000000000000000000000000000000..df83587f661939496435e6daf166de308c79cad4 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_cr_cw_ratio IS + GENERIC ( + g_ram_wr : t_c_mem := c_mem_ram; -- settings for port a + g_ram_rd : t_c_mem := c_mem_ram; -- data width and address range for port b + g_init_file : STRING := "UNUSED" + ); + PORT ( + -- Write port clock domain + wr_rst : IN STD_LOGIC := '0'; + wr_clk : IN STD_LOGIC; + wr_clken : IN STD_LOGIC := '1'; + wr_en : IN STD_LOGIC := '0'; + wr_adr : IN STD_LOGIC_VECTOR(g_ram_wr.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + wr_dat : IN STD_LOGIC_VECTOR(g_ram_wr.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + -- Read port clock domain + rd_rst : IN STD_LOGIC := '0'; + rd_clk : IN STD_LOGIC; + rd_clken : IN STD_LOGIC := '1'; + rd_en : IN STD_LOGIC := '1'; + rd_adr : IN STD_LOGIC_VECTOR(g_ram_rd.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_dat : OUT STD_LOGIC_VECTOR(g_ram_rd.dat_w-1 DOWNTO 0); + rd_val : OUT STD_LOGIC + ); +END common_ram_cr_cw_ratio; + + +ARCHITECTURE str OF common_ram_cr_cw_ratio IS + +BEGIN + + -- Dual clock domain + -- Use port a only for write in write clock domain + -- Use port b only for read in read clock domain + + u_cr_cw : ENTITY work.common_ram_crw_crw_ratio + GENERIC MAP ( + g_ram_a => g_ram_wr, + g_ram_b => g_ram_rd, + g_init_file => g_init_file + ) + PORT MAP ( + rst_a => wr_rst, + rst_b => rd_rst, + clk_a => wr_clk, + clk_b => rd_clk, + clken_a => wr_clken, + clken_b => rd_clken, + wr_en_a => wr_en, + wr_en_b => '0', + wr_dat_a => wr_dat, + wr_dat_b => (OTHERS=>'0'), + adr_a => wr_adr, + adr_b => rd_adr, + rd_en_a => '0', + rd_en_b => rd_en, + rd_dat_a => OPEN, + rd_dat_b => rd_dat, + rd_val_a => OPEN, + rd_val_b => rd_val + ); + +END str; \ No newline at end of file diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c33a799c8371f54c67f51416403d063b3ccc1314 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd @@ -0,0 +1,89 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_crw_cr IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + -- MM read/write port clock domain + mm_rst : IN STD_LOGIC := '0'; + mm_clk : IN STD_LOGIC; + mm_clken : IN STD_LOGIC := '1'; + mm_wr_en : IN STD_LOGIC := '0'; + mm_wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + mm_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + mm_rd_en : IN STD_LOGIC := '1'; + mm_rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + mm_rd_val : OUT STD_LOGIC; + + -- ST read only port clock domain + st_rst : IN STD_LOGIC := '0'; + st_clk : IN STD_LOGIC; + st_clken : IN STD_LOGIC := '1'; + st_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + st_rd_en : IN STD_LOGIC := '1'; + st_rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + st_rd_val : OUT STD_LOGIC + ); +END common_ram_crw_cr; + + +ARCHITECTURE str OF common_ram_crw_cr IS + +BEGIN + + -- Dual clock domain + -- Use port a for read/write in MM clock domain + -- Use port b for read only in ST clock domain + + u_crw_cr : ENTITY work.common_ram_crw_crw + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst_a => mm_rst, + rst_b => st_rst, + clk_a => mm_clk, + clk_b => st_clk, + clken_a => mm_clken, + clken_b => st_clken, + wr_en_a => mm_wr_en, + wr_en_b => '0', + wr_dat_a => mm_wr_dat, + wr_dat_b => (OTHERS=>'0'), + adr_a => mm_adr, + adr_b => st_adr, + rd_en_a => mm_rd_en, + rd_en_b => st_rd_en, + rd_dat_a => mm_rd_dat, + rd_dat_b => st_rd_dat, + rd_val_a => mm_rd_val, + rd_val_b => st_rd_val + ); + +END str; diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd new file mode 100644 index 0000000000000000000000000000000000000000..aa1d5ca6612227d6920de33bb1ebb8f458f17db4 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_pkg.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_crw_crw_ratio IS + GENERIC ( + g_ram_a : t_c_mem := c_mem_ram; -- settings for port a + g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b + g_init_file : STRING := "UNUSED" + ); + PORT ( + rst_a : IN STD_LOGIC := '0'; + rst_b : IN STD_LOGIC := '0'; + clk_a : IN STD_LOGIC; + clk_b : IN STD_LOGIC; + clken_a : IN STD_LOGIC := '1'; + clken_b : IN STD_LOGIC := '1'; + wr_en_a : IN STD_LOGIC := '0'; + wr_en_b : IN STD_LOGIC := '0'; + wr_dat_a : IN STD_LOGIC_VECTOR(g_ram_a.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + wr_dat_b : IN STD_LOGIC_VECTOR(g_ram_b.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + adr_a : IN STD_LOGIC_VECTOR(g_ram_a.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + adr_b : IN STD_LOGIC_VECTOR(g_ram_b.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_en_a : IN STD_LOGIC := '1'; + rd_en_b : IN STD_LOGIC := '1'; + rd_dat_a : OUT STD_LOGIC_VECTOR(g_ram_a.dat_w-1 DOWNTO 0); + rd_dat_b : OUT STD_LOGIC_VECTOR(g_ram_b.dat_w-1 DOWNTO 0); + rd_val_a : OUT STD_LOGIC; + rd_val_b : OUT STD_LOGIC + ); +END common_ram_crw_crw_ratio; + + +ARCHITECTURE str OF common_ram_crw_crw_ratio IS + + CONSTANT c_ram : t_c_mem := g_ram_a; -- use shared parameters from port a parameter + + CONSTANT c_rd_latency : NATURAL := sel_a_b(c_ram.latency<2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM + CONSTANT c_pipeline : NATURAL := sel_a_b(c_ram.latency>c_rd_latency, c_ram.latency-c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline + + -- Intermediate signal for extra pipelining + SIGNAL ram_rd_dat_a : STD_LOGIC_VECTOR(rd_dat_a'RANGE); + SIGNAL ram_rd_dat_b : STD_LOGIC_VECTOR(rd_dat_b'RANGE); + + -- Map sl to single bit slv for rd_val pipelining + SIGNAL ram_rd_en_a : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL ram_rd_en_b : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL ram_rd_val_a : STD_LOGIC_VECTOR(0 DOWNTO 0); + SIGNAL ram_rd_val_b : STD_LOGIC_VECTOR(0 DOWNTO 0); + +BEGIN + + ASSERT c_ram.latency >= 1 + REPORT "common_ram_crw_crw_ratio : only support read latency >= 1" + SEVERITY FAILURE; + + ASSERT g_ram_a.latency = g_ram_b.latency + REPORT "common_ram_crw_crw_ratio : only support same read latency for both ports" + SEVERITY FAILURE; + + -- memory access + u_ramk : ENTITY work.ram_crwk_crw + GENERIC MAP ( + g_adr_a_w => g_ram_a.adr_w, + g_adr_b_w => g_ram_b.adr_w, + g_dat_a_w => g_ram_a.dat_w, + g_dat_b_w => g_ram_b.dat_w, + g_nof_words_a => g_ram_a.nof_dat, + g_nof_words_b => g_ram_b.nof_dat, + g_rd_latency => c_rd_latency, + g_init_file => g_init_file + ) + PORT MAP ( + clock_a => clk_a, + clock_b => clk_b, + enable_a => clken_a, + enable_b => clken_b, + wren_a => wr_en_a, + wren_b => wr_en_b, + data_a => wr_dat_a, + data_b => wr_dat_b, + address_a => adr_a, + address_b => adr_b, + q_a => ram_rd_dat_a, + q_b => ram_rd_dat_b + ); + + -- read output + u_pipe_a : ENTITY work.common_pipeline + GENERIC MAP ( + g_pipeline => c_pipeline, + g_in_dat_w => g_ram_a.dat_w, + g_out_dat_w => g_ram_a.dat_w + ) + PORT MAP ( + clk => clk_a, + clken => clken_a, + in_dat => ram_rd_dat_a, + out_dat => rd_dat_a + ); + + u_pipe_b : ENTITY work.common_pipeline + GENERIC MAP ( + g_pipeline => c_pipeline, + g_in_dat_w => g_ram_b.dat_w, + g_out_dat_w => g_ram_b.dat_w + ) + PORT MAP ( + clk => clk_b, + clken => clken_b, + in_dat => ram_rd_dat_b, + out_dat => rd_dat_b + ); + + -- rd_val control + ram_rd_en_a(0) <= rd_en_a; + ram_rd_en_b(0) <= rd_en_b; + + rd_val_a <= ram_rd_val_a(0); + rd_val_b <= ram_rd_val_b(0); + + u_rd_val_a : ENTITY work.common_pipeline + GENERIC MAP ( + g_pipeline => c_ram.latency, + g_in_dat_w => 1, + g_out_dat_w => 1 + ) + PORT MAP ( + clk => clk_a, + clken => clken_a, + in_dat => ram_rd_en_a, + out_dat => ram_rd_val_a + ); + + u_rd_val_b : ENTITY work.common_pipeline + GENERIC MAP ( + g_pipeline => c_ram.latency, + g_in_dat_w => 1, + g_out_dat_w => 1 + ) + PORT MAP ( + clk => clk_b, + clken => clken_b, + in_dat => ram_rd_en_b, + out_dat => ram_rd_val_b + ); + +END str; diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd new file mode 100644 index 0000000000000000000000000000000000000000..642f43ba4db5467ea99384cf459270b8556ce7bd --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_crw_cw IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + -- MM read/write port clock domain + mm_rst : IN STD_LOGIC := '0'; + mm_clk : IN STD_LOGIC; + mm_clken : IN STD_LOGIC := '1'; + mm_wr_en : IN STD_LOGIC := '0'; + mm_wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + mm_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + mm_rd_en : IN STD_LOGIC := '1'; + mm_rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + mm_rd_val : OUT STD_LOGIC; + + -- ST write only port clock domain + st_rst : IN STD_LOGIC := '0'; + st_clk : IN STD_LOGIC; + st_clken : IN STD_LOGIC := '1'; + st_wr_en : IN STD_LOGIC := '0'; + st_wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + st_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0') + ); +END common_ram_crw_cw; + + +ARCHITECTURE str OF common_ram_crw_cw IS + +BEGIN + + -- Dual clock domain + -- Use port a for read/write in MM clock domain + -- Use port b for write only in ST clock domain + + u_crw_cw : ENTITY work.common_ram_crw_crw + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst_a => mm_rst, + rst_b => st_rst, + clk_a => mm_clk, + clk_b => st_clk, + clken_a => mm_clken, + clken_b => st_clken, + wr_en_a => mm_wr_en, + wr_en_b => st_wr_en, + wr_dat_a => mm_wr_dat, + wr_dat_b => st_wr_dat, + adr_a => mm_adr, + adr_b => st_adr, + rd_en_a => mm_rd_en, + rd_en_b => '0', + rd_dat_a => mm_rd_dat, + rd_dat_b => OPEN, + rd_val_a => mm_rd_val, + rd_val_b => OPEN + ); + +END str; diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd new file mode 100644 index 0000000000000000000000000000000000000000..3d4b75d0d3361f85f9bee04d611b827d550b2dc4 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd @@ -0,0 +1,77 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_r_w IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + rst : IN STD_LOGIC := '0'; + clk : IN STD_LOGIC; + clken : IN STD_LOGIC := '1'; + wr_en : IN STD_LOGIC := '0'; + wr_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + wr_dat : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_en : IN STD_LOGIC := '1'; + rd_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0); + rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + rd_val : OUT STD_LOGIC + ); +END common_ram_r_w; + + +ARCHITECTURE str OF common_ram_r_w IS + +BEGIN + + -- Use port a only for write + -- Use port b only for read + + u_rw_rw : ENTITY work.common_ram_rw_rw + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst => rst, + clk => clk, + clken => clken, + wr_en_a => wr_en, + wr_en_b => '0', + wr_dat_a => wr_dat, + --wr_dat_b => (OTHERS=>'0'), + adr_a => wr_adr, + adr_b => rd_adr, + rd_en_a => '0', + rd_en_b => rd_en, + rd_dat_a => OPEN, + rd_dat_b => rd_dat, + rd_val_a => OPEN, + rd_val_b => rd_val + ); + +END str; + diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d862e49090330e1852e045d350fdef266e61dbb8 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd @@ -0,0 +1,83 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_ram_rw_rw IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + rst : IN STD_LOGIC := '0'; + clk : IN STD_LOGIC; + clken : IN STD_LOGIC := '1'; + wr_en_a : IN STD_LOGIC := '0'; + wr_en_b : IN STD_LOGIC := '0'; + wr_dat_a : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + wr_dat_b : IN STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + adr_a : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + adr_b : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_en_a : IN STD_LOGIC := '1'; + rd_en_b : IN STD_LOGIC := '1'; + rd_dat_a : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + rd_dat_b : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0); + rd_val_a : OUT STD_LOGIC; + rd_val_b : OUT STD_LOGIC + ); +END common_ram_rw_rw; + + +ARCHITECTURE str OF common_ram_rw_rw IS + +BEGIN + + -- Use only one clock domain + + u_crw_crw : ENTITY work.common_ram_crw_crw + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst_a => rst, + rst_b => rst, + clk_a => clk, + clk_b => clk, + clken_a => clken, + clken_b => clken, + wr_en_a => wr_en_a, + wr_en_b => wr_en_b, + wr_dat_a => wr_dat_a, + wr_dat_b => wr_dat_b, + adr_a => adr_a, + adr_b => adr_b, + rd_en_a => rd_en_a, + rd_en_b => rd_en_b, + rd_dat_a => rd_dat_a, + rd_dat_b => rd_dat_b, + rd_val_a => rd_val_a, + rd_val_b => rd_val_b + ); + +END str; diff --git a/libraries/base/common/src/vhdl/common_rom.vhd b/libraries/base/common/src/vhdl/common_rom.vhd new file mode 100644 index 0000000000000000000000000000000000000000..5552272fbe57387897d2292a64f8df25c715f259 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_rom.vhd @@ -0,0 +1,67 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE work.common_mem_pkg.ALL; + +ENTITY common_rom IS + GENERIC ( + g_ram : t_c_mem := c_mem_ram; + g_init_file : STRING := "UNUSED" + ); + PORT ( + rst : IN STD_LOGIC := '0'; + clk : IN STD_LOGIC; + clken : IN STD_LOGIC := '1'; + rd_en : IN STD_LOGIC := '1'; + rd_adr : IN STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_dat : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0'); + rd_val : OUT STD_LOGIC + ); +END common_rom; + + +ARCHITECTURE str OF common_rom IS + +BEGIN + + -- Only use the read port + + u_r_w : ENTITY work.common_ram_r_w + GENERIC MAP ( + g_ram => g_ram, + g_init_file => g_init_file + ) + PORT MAP ( + rst => rst, + clk => clk, + clken => clken, + wr_en => '0', + --wr_adr => (OTHERS=>'0'), + --wr_dat => (OTHERS=>'0'), + rd_en => rd_en, + rd_adr => rd_adr, + rd_dat => rd_dat, + rd_val => rd_val + ); + +END str;