From 71e68eabfb951aaf99f54f7e158c0fd25373b521 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 26 Oct 2021 14:50:23 +0200
Subject: [PATCH] Updated pinning for jesd on unb2c and corrected qsys
---
.../qsys_lofar2_unb2c_sdp_station_cpu_0.ip | 4 +-
...sys_lofar2_unb2c_sdp_station_ram_st_xsq.ip | 18 +-
.../quartus/lofar2_unb2c_sdp_station_pins.tcl | 412 +++++-------------
.../qsys_lofar2_unb2c_sdp_station.qsys | 199 +++++----
.../lofar2_unb2c_sdp_station_adc.vhd | 25 +-
.../lofar2_unb2c_sdp_station_bf.vhd | 30 +-
.../lofar2_unb2c_sdp_station_fsub.vhd | 26 +-
.../lofar2_unb2c_sdp_station_full.vhd | 31 +-
.../lofar2_unb2c_sdp_station_xsub_one.vhd | 26 +-
.../unb2c_board/src/vhdl/unb2c_board_pkg.vhd | 6 +-
.../jesd204b/tech_jesd204b_component_pkg.vhd | 4 +-
11 files changed, 260 insertions(+), 521 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index 7e4aa9b512..85640f63d7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC000' end='0xBC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC008' end='0xBC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC010' end='0xBC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC018' end='0xBC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3600' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xBC000' end='0xBC008' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xBC008' end='0xBC010' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xBC010' end='0xBC018' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC018' end='0xBC020' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
index 248f1a7ef8..7d833a9272 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>65536</ipxact:value>
+ <ipxact:value>262144</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>15</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>14</ipxact:value>
+ <ipxact:value>16</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index 6f4cc22060..6cedc04415 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -98,139 +98,114 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
-#set_location_assignment PIN_B9 -to BCK_RX[0]
-set_location_assignment PIN_D9 -to BCK_RX[1]
-set_location_assignment PIN_C11 -to BCK_RX[2]
-set_location_assignment PIN_F9 -to BCK_RX[3]
-set_location_assignment PIN_C7 -to BCK_RX[4]
-set_location_assignment PIN_E11 -to BCK_RX[5]
-set_location_assignment PIN_E7 -to BCK_RX[6]
-set_location_assignment PIN_D5 -to BCK_RX[7]
-set_location_assignment PIN_G7 -to BCK_RX[8]
-set_location_assignment PIN_F5 -to BCK_RX[9]
-set_location_assignment PIN_J7 -to BCK_RX[10]
-set_location_assignment PIN_H5 -to BCK_RX[11]
-set_location_assignment PIN_L7 -to BCK_RX[12]
-set_location_assignment PIN_K5 -to BCK_RX[13]
-set_location_assignment PIN_N7 -to BCK_RX[14]
-set_location_assignment PIN_M5 -to BCK_RX[15]
-set_location_assignment PIN_R7 -to BCK_RX[16]
-set_location_assignment PIN_P5 -to BCK_RX[17]
-set_location_assignment PIN_U7 -to BCK_RX[18]
-set_location_assignment PIN_T5 -to BCK_RX[19]
-set_location_assignment PIN_W7 -to BCK_RX[20]
-set_location_assignment PIN_V5 -to BCK_RX[21]
-set_location_assignment PIN_AA7 -to BCK_RX[22]
-set_location_assignment PIN_Y5 -to BCK_RX[23]
-set_location_assignment PIN_AC7 -to BCK_RX[24]
-set_location_assignment PIN_AB5 -to BCK_RX[25]
-set_location_assignment PIN_AE7 -to BCK_RX[26]
-set_location_assignment PIN_AD5 -to BCK_RX[27]
-set_location_assignment PIN_AG7 -to BCK_RX[28]
-set_location_assignment PIN_AF5 -to BCK_RX[29]
-set_location_assignment PIN_AJ7 -to BCK_RX[30]
-set_location_assignment PIN_AH5 -to BCK_RX[31]
-set_location_assignment PIN_AL7 -to BCK_RX[32]
-set_location_assignment PIN_AK5 -to BCK_RX[33]
-set_location_assignment PIN_AN7 -to BCK_RX[34]
-set_location_assignment PIN_AM5 -to BCK_RX[35]
-set_location_assignment PIN_AR7 -to BCK_RX[36]
-set_location_assignment PIN_AP5 -to BCK_RX[37]
-set_location_assignment PIN_AU7 -to BCK_RX[38]
-set_location_assignment PIN_AT5 -to BCK_RX[39]
-set_location_assignment PIN_AW7 -to BCK_RX[40]
-set_location_assignment PIN_AV5 -to BCK_RX[41]
-set_location_assignment PIN_BA7 -to BCK_RX[42]
-set_location_assignment PIN_AY5 -to BCK_RX[43]
-set_location_assignment PIN_BC7 -to BCK_RX[44]
-set_location_assignment PIN_BB5 -to BCK_RX[45]
-set_location_assignment PIN_AY9 -to BCK_RX[46]
-set_location_assignment PIN_BB9 -to BCK_RX[47]
-
-
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
+#set_location_assignment PIN_AC7 -to BCK_RX[23]
+#set_location_assignment PIN_AB5 -to BCK_RX[22]
+#set_location_assignment PIN_AE7 -to BCK_RX[21]
+#set_location_assignment PIN_AD5 -to BCK_RX[20]
+#set_location_assignment PIN_AG7 -to BCK_RX[19]
+#set_location_assignment PIN_AF5 -to BCK_RX[18]
+#set_location_assignment PIN_AJ7 -to BCK_RX[17]
+#set_location_assignment PIN_AH5 -to BCK_RX[16]
+#set_location_assignment PIN_AL7 -to BCK_RX[15]
+#set_location_assignment PIN_AK5 -to BCK_RX[14]
+#set_location_assignment PIN_AN7 -to BCK_RX[13]
+#set_location_assignment PIN_AM5 -to BCK_RX[12]
+set_location_assignment PIN_AR7 -to BCK_RX[11]
+set_location_assignment PIN_AP5 -to BCK_RX[10]
+set_location_assignment PIN_AU7 -to BCK_RX[9]
+set_location_assignment PIN_AT5 -to BCK_RX[8]
+set_location_assignment PIN_AW7 -to BCK_RX[7]
+set_location_assignment PIN_AV5 -to BCK_RX[6]
+set_location_assignment PIN_BA7 -to BCK_RX[5]
+set_location_assignment PIN_AY5 -to BCK_RX[4]
+set_location_assignment PIN_BC7 -to BCK_RX[3]
+set_location_assignment PIN_BB5 -to BCK_RX[2]
+set_location_assignment PIN_AY9 -to BCK_RX[1]
+set_location_assignment PIN_BB9 -to BCK_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
@@ -316,178 +291,7 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47]
-
-
# Substitute new signal names from the jesd_simple design
-#set_location_assignment PIN_BA7 -to BCK_RX[0]
-
set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 3a03b8bb8d..3b4e2f6bc3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "13824";
+ value = "12352";
type = "String";
}
}
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "753664";
+ value = "950272";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "770072";
+ value = "966680";
type = "String";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "262144";
+ value = "524288";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "720896";
+ value = "917504";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "786432";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "655360";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "851968";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "262144";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "720896";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "13824";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "770064";
+ value = "966672";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "770056";
+ value = "966664";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "770048";
+ value = "966656";
type = "String";
}
}
@@ -7324,7 +7324,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xB0000' end='0xB8000' datawidth='32' /><slave name='jesd204b.mem' start='0xB8000' end='0xBC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xBC000' end='0xBC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xBC008' end='0xBC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xBC010' end='0xBC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xBC018' end='0xBC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3600' end='0x3640' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3640' end='0x3680' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3680' end='0x36C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x36C0' end='0x3700' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3700' end='0x3720' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3720' end='0x3740' datawidth='32' /><slave name='reg_epcs.mem' start='0x3740' end='0x3760' datawidth='32' /><slave name='reg_remu.mem' start='0x3760' end='0x3780' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x3780' end='0x3790' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3790' end='0x37A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x37A0' end='0x37B0' datawidth='32' /><slave name='pio_pps.mem' start='0x37B0' end='0x37C0' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x37C0' end='0x37C8' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x37C8' end='0x37D0' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x37D0' end='0x37D8' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x37D8' end='0x37E0' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x37E0' end='0x37E8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x37E8' end='0x37F0' datawidth='32' /><slave name='reg_si.mem' start='0x37F0' end='0x37F8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x37F8' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='ram_wg.mem' start='0xB0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xE0000' end='0xE8000' datawidth='32' /><slave name='jesd204b.mem' start='0xE8000' end='0xEC000' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xEC000' end='0xEC008' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xEC008' end='0xEC010' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xEC010' end='0xEC018' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xEC018' end='0xEC020' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -26308,7 +26308,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26372,7 +26372,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26441,7 +26441,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26847,11 +26847,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26888,7 +26888,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26952,7 +26952,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27021,7 +27021,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63392,17 +63392,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>6</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -63411,27 +63411,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -63444,13 +63445,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -63503,21 +63502,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -63557,7 +63552,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -63690,12 +63684,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -63722,17 +63716,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -63754,17 +63748,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -63786,14 +63780,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -63805,31 +63799,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -63839,22 +63832,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -63881,14 +63876,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -68677,7 +68672,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000bc018" />
+ <parameter name="baseAddress" value="0x000ec018" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68837,7 +68832,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000bc010" />
+ <parameter name="baseAddress" value="0x000ec010" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68857,7 +68852,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000bc008" />
+ <parameter name="baseAddress" value="0x000ec008" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68877,7 +68872,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000bc000" />
+ <parameter name="baseAddress" value="0x000ec000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68957,7 +68952,7 @@
start="cpu_0.data_master"
end="ram_st_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x000d0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -68997,7 +68992,7 @@
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x000c0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69057,7 +69052,7 @@
start="cpu_0.data_master"
end="ram_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x000b0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69177,7 +69172,7 @@
start="cpu_0.data_master"
end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000b8000" />
+ <parameter name="baseAddress" value="0x000e8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69217,7 +69212,7 @@
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000b0000" />
+ <parameter name="baseAddress" value="0x000e0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69237,7 +69232,7 @@
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x000a0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69257,7 +69252,7 @@
start="cpu_0.data_master"
end="ram_bf_weights.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0x00080000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69577,7 +69572,7 @@
start="cpu_0.data_master"
end="ram_st_xsq.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69637,7 +69632,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x3600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -69717,7 +69712,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 1205e0b452..c7ace4c1d3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_adc IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,27 +80,16 @@ END lofar2_unb2c_sdp_station_adc;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_adc IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 3076d33960..a24859007b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -69,17 +69,17 @@ ENTITY lofar2_unb2c_sdp_station_bf IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -87,30 +87,18 @@ END lofar2_unb2c_sdp_station_bf;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_bf IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index d293a305d7..a6e729e54b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_fsub IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,29 +80,17 @@ END lofar2_unb2c_sdp_station_fsub;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_fsub IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index c16a176dcd..25983bb3e1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -69,17 +69,17 @@ ENTITY lofar2_unb2c_sdp_station_full IS
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-- front transceivers
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -87,30 +87,17 @@ END lofar2_unb2c_sdp_station_full;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_full IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
-
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index 0d792d0d60..76b86a18a3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -68,11 +68,11 @@ ENTITY lofar2_unb2c_sdp_station_xsub_one IS
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
- -- back transceivers (note only 6 are used in unb2c)
- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b-1 downto c_unb2c_board_nof_tr_jesd204b);
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
- -- jesd204b syncronization signals (2 syncs)
+ -- jesd204b syncronization signals (4 syncs)
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0)
);
@@ -80,29 +80,17 @@ END lofar2_unb2c_sdp_station_xsub_one;
ARCHITECTURE str OF lofar2_unb2c_sdp_station_xsub_one IS
- SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
SIGNAL JESD204B_REFCLK : STD_LOGIC;
BEGIN
-- Mapping between JESD signal names and UNB2B pin/schematic names
- JESD204B_REFCLK <= BCK_REF_CLK;
- JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
- JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
- JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
- JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
- JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
- JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
- JESD204B_SERIAL_DATA(6) <= '0';
- JESD204B_SERIAL_DATA(7) <= '0';
- JESD204B_SERIAL_DATA(8) <= '0';
- JESD204B_SERIAL_DATA(9) <= '0';
- JESD204B_SERIAL_DATA(10) <= '0';
- JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
-
u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
GENERIC MAP (
g_design_name => g_design_name,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index a6334d61cb..ba8c6191dd 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -75,9 +75,9 @@ PACKAGE unb2c_board_pkg IS
CONSTANT c_unb2c_board_tr_ring : t_c_unb2c_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
CONSTANT c_unb2c_board_tr_qsfp : t_c_unb2c_board_tr := (6, 4, 0); -- per node: 6 buses with 4 channels
CONSTANT c_unb2c_board_tr_jesd204b : t_c_unb2c_board_tr := (1, 12, 0); -- per node: 1 buses with 12 channels
- CONSTANT c_unb2c_board_nof_tr_jesd204b : NATURAL := 6; --Only 6 channels used in unb2b lab tests
- CONSTANT c_unb2c_board_start_tr_jesd204b : NATURAL := 42; --First transceiver used in unb2b lab tests
- CONSTANT c_unb2c_board_nof_sync_jesd204b : NATURAL := 2; --Only 6 channels used in unb2b lab tests
+ CONSTANT c_unb2c_board_nof_tr_jesd204b : NATURAL := 12; -- 12 channels used in unb2c lab tests
+ CONSTANT c_unb2c_board_start_tr_jesd204b : NATURAL := 0; -- First BCK transceiver used for jesd in unb2c lab tests
+ CONSTANT c_unb2c_board_nof_sync_jesd204b : NATURAL := 4; -- 4 channels used in unb2c lab tests, 1 for each RCU.
CONSTANT c_unb2c_board_tr_qsfp_nof_leds : NATURAL := c_unb2c_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 27cee6e928..7b109077f7 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -47,7 +47,7 @@ PACKAGE tech_jesd204b_component_pkg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
@@ -85,7 +85,7 @@ PACKAGE tech_jesd204b_component_pkg IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
--
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