diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 7c28e89185fa788775c0e85bb2f5bea4923a3e22..d6d7e396408e2915242cd0ae69c7e308ba2fe32b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -193,27 +193,27 @@ peripherals:
mm_port_names:
- REG_STAT_HDR_DAT_SST
- #############################################################################
- # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
- #############################################################################
-
- - peripheral_name: dp/dp_bsn_scheduler
- peripheral_group: xsub
- mm_port_names:
- - REG_BSN_SCHEDULER_XSUB
-
- - peripheral_name: dp/dp_sync_insert_v2
- mm_port_names:
- - REG_DP_SYNC_INSERT_V2
-
- - peripheral_name: st/st_xst
- mm_port_names:
- - RAM_ST_XSQ
-
- - peripheral_name: sdp/sdp_crosslets_subband_select
- mm_port_names:
- - REG_CROSSLETS_INFO
-
+# #############################################################################
+# # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
+# #############################################################################
+#
+# - peripheral_name: dp/dp_bsn_scheduler
+# peripheral_group: xsub
+# mm_port_names:
+# - REG_BSN_SCHEDULER_XSUB
+#
+# - peripheral_name: dp/dp_sync_insert_v2
+# mm_port_names:
+# - REG_DP_SYNC_INSERT_V2
+#
+# - peripheral_name: st/st_xst
+# mm_port_names:
+# - RAM_ST_XSQ
+#
+# - peripheral_name: sdp/sdp_crosslets_subband_select
+# mm_port_names:
+# - REG_CROSSLETS_INFO
+#
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index e0f6d1e47b28eb08d2bc7def60bca290646ad92c..1954ada2da8d21ff022af1e496c848e1127d920e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_crosslets_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='jesd204b.mem' start='0xA8000' end='0xAC000' datawidth='32' /><slave name='reg_epcs.mem' start='0xAC000' end='0xAC020' datawidth='32' /><slave name='reg_remu.mem' start='0xAC020' end='0xAC040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xAC040' end='0xAC050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xAC050' end='0xAC060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xAC060' end='0xAC068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xAC068' end='0xAC070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xAC070' end='0xAC078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xAC078' end='0xAC080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xAC080' end='0xAC088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xAC088' end='0xAC090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xAC090' end='0xAC098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xAC098' end='0xAC0A0' datawidth='32' /><slave name='reg_si.mem' start='0xAC0A0' end='0xAC0A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xAC0A8' end='0xAC0B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xAC0B0' end='0xAC0B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xAC0B8' end='0xAC0C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xAC0C0' end='0xAC0C8' datawidth='32' /><slave name='pio_pps.mem' start='0xAC0C8' end='0xAC0D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xAC0D0' end='0xAC0D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_crosslets_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='jesd204b.mem' start='0xA8000' end='0xAC000' datawidth='32' /><slave name='reg_epcs.mem' start='0xAC000' end='0xAC020' datawidth='32' /><slave name='reg_remu.mem' start='0xAC020' end='0xAC040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xAC040' end='0xAC050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xAC050' end='0xAC060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xAC060' end='0xAC068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xAC068' end='0xAC070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xAC070' end='0xAC078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xAC078' end='0xAC080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xAC080' end='0xAC088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xAC088' end='0xAC090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xAC090' end='0xAC098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xAC098' end='0xAC0A0' datawidth='32' /><slave name='reg_si.mem' start='0xAC0A0' end='0xAC0A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xAC0A8' end='0xAC0B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xAC0B0' end='0xAC0B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xAC0B8' end='0xAC0C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xAC0C0' end='0xAC0C8' datawidth='32' /><slave name='pio_pps.mem' start='0xAC0C8' end='0xAC0D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xAC0D0' end='0xAC0D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
index 4fdf1ab86cd5e07cd1d25bc45a86e90ad404e3c3..058e6e8b5e0d547b5ee4c124f36c45a1c76b2ec4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
+ <spirit:right>13</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
+ <spirit:right>13</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 7f67a7f1add560ef4f48e429e7c5da30e3376b73..be5dfd5d030c5ed716ccaa7bcdc9b7c268d38019 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "14080";
+ value = "12352";
type = "String";
}
}
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "688128";
+ value = "720896";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "704720";
+ value = "737488";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "704640";
+ value = "737408";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "704712";
+ value = "737480";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "98304";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "589824";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "458752";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "655360";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "393216";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "524288";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "704592";
+ value = "737360";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "704664";
+ value = "737432";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "14080";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "704656";
+ value = "737424";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "704608";
+ value = "737376";
type = "String";
}
}
@@ -554,7 +554,7 @@
{
datum baseAddress
{
- value = "704576";
+ value = "737344";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "704704";
+ value = "737472";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "704696";
+ value = "737464";
type = "String";
}
}
@@ -617,7 +617,7 @@
{
datum baseAddress
{
- value = "704512";
+ value = "737280";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "704688";
+ value = "737456";
type = "String";
}
}
@@ -712,7 +712,7 @@
{
datum baseAddress
{
- value = "704680";
+ value = "737448";
type = "String";
}
}
@@ -728,7 +728,7 @@
{
datum baseAddress
{
- value = "704648";
+ value = "737416";
type = "String";
}
}
@@ -744,7 +744,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "32768";
type = "String";
}
}
@@ -765,7 +765,7 @@
{
datum baseAddress
{
- value = "704544";
+ value = "737312";
type = "String";
}
}
@@ -797,7 +797,7 @@
{
datum baseAddress
{
- value = "704672";
+ value = "737440";
type = "String";
}
}
@@ -813,7 +813,7 @@
{
datum baseAddress
{
- value = "704624";
+ value = "737392";
type = "String";
}
}
@@ -829,7 +829,7 @@
{
datum baseAddress
{
- value = "704616";
+ value = "737384";
type = "String";
}
}
@@ -845,7 +845,7 @@
{
datum baseAddress
{
- value = "704632";
+ value = "737400";
type = "String";
}
}
@@ -5805,7 +5805,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_crosslets_info.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0xA0000' end='0xA8000' datawidth='32' /><slave name='jesd204b.mem' start='0xA8000' end='0xAC000' datawidth='32' /><slave name='reg_epcs.mem' start='0xAC000' end='0xAC020' datawidth='32' /><slave name='reg_remu.mem' start='0xAC020' end='0xAC040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xAC040' end='0xAC050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xAC050' end='0xAC060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xAC060' end='0xAC068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xAC068' end='0xAC070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xAC070' end='0xAC078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xAC078' end='0xAC080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xAC080' end='0xAC088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xAC088' end='0xAC090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xAC090' end='0xAC098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xAC098' end='0xAC0A0' datawidth='32' /><slave name='reg_si.mem' start='0xAC0A0' end='0xAC0A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xAC0A8' end='0xAC0B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xAC0B0' end='0xAC0B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xAC0B8' end='0xAC0C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xAC0C0' end='0xAC0C8' datawidth='32' /><slave name='pio_pps.mem' start='0xAC0C8' end='0xAC0D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xAC0D0' end='0xAC0D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4060' end='0xB4068' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0xB4068' end='0xB4070' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -15236,7 +15236,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15300,7 +15300,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15369,7 +15369,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15775,11 +15775,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39356,7 +39356,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000ac0d0" />
+ <parameter name="baseAddress" value="0x000b40d0" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +39391,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000ac0c8" />
+ <parameter name="baseAddress" value="0x000b40c8" />
</connection>
<connection
kind="avalon"
@@ -39405,42 +39405,42 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000ac020" />
+ <parameter name="baseAddress" value="0x000b4020" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000ac000" />
+ <parameter name="baseAddress" value="0x000b4000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000ac0c0" />
+ <parameter name="baseAddress" value="0x000b40c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000ac0b8" />
+ <parameter name="baseAddress" value="0x000b40b8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000ac0b0" />
+ <parameter name="baseAddress" value="0x000b40b0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000ac0a8" />
+ <parameter name="baseAddress" value="0x000b40a8" />
</connection>
<connection
kind="avalon"
@@ -39468,21 +39468,21 @@
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x000a0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000ac0a0" />
+ <parameter name="baseAddress" value="0x000b40a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x00090000" />
</connection>
<connection
kind="avalon"
@@ -39503,7 +39503,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
@@ -39517,7 +39517,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000ac098" />
+ <parameter name="baseAddress" value="0x000b4098" />
</connection>
<connection
kind="avalon"
@@ -39545,28 +39545,28 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000a8000" />
+ <parameter name="baseAddress" value="0x000b0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000ac090" />
+ <parameter name="baseAddress" value="0x000b4090" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00070000" />
</connection>
<connection
kind="avalon"
@@ -39580,7 +39580,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000ac050" />
+ <parameter name="baseAddress" value="0x000b4050" />
</connection>
<connection
kind="avalon"
@@ -39594,7 +39594,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000ac040" />
+ <parameter name="baseAddress" value="0x000b4040" />
</connection>
<connection
kind="avalon"
@@ -39615,14 +39615,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000ac088" />
+ <parameter name="baseAddress" value="0x000b4088" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
@@ -39643,14 +39643,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000ac080" />
+ <parameter name="baseAddress" value="0x000b4080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000ac078" />
+ <parameter name="baseAddress" value="0x000b4078" />
</connection>
<connection
kind="avalon"
@@ -39664,14 +39664,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst_0.mem">
- <parameter name="baseAddress" value="0x000ac070" />
+ <parameter name="baseAddress" value="0x000b4070" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst_1.mem">
- <parameter name="baseAddress" value="0x000ac068" />
+ <parameter name="baseAddress" value="0x000b4068" />
</connection>
<connection
kind="avalon"
@@ -39692,14 +39692,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_sync_insert_v2.mem">
- <parameter name="baseAddress" value="0x000ac060" />
+ <parameter name="baseAddress" value="0x000b4060" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x3700" />
</connection>
<connection
kind="avalon"
@@ -39713,7 +39713,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_st_xsq.mem">
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00060000" />
</connection>
<connection
kind="avalon"
@@ -39727,7 +39727,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="baseAddress" value="0x3700" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 409aaeb380a0b8e09fcd0b72c0248590fd7a9320..260e3eba61fa9c481ca3e7302206ec3866d5f8e3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -20,10 +20,10 @@
-- Author : R. van der Walle
-- Purpose:
--- Wrapper for Lofar2 SDP Station filterbank design
+-- Wrapper for Lofar2 SDP Station subband correlator design
-- Description:
-- Unb2b version for lab testing
--- Contains complete AIT input stage with 12 ADC streams and FSUB
+-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
@@ -39,7 +39,7 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_sdp_station_xsub_one IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_sdp_station_xsub_one";
- g_design_note : STRING := "Lofar2 SDP station filterbank design";
+ g_design_note : STRING := "Lofar2 SDP station subband correlator design";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 54c38eeba048167511998e269bb29cabfa1ad421..a8e0635b63a96c82458a3f1efcd46c679643a3af 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -27,16 +27,16 @@
-- MM control actions:
--
-- 1) Enable calc mode for WG via reg_diag_wg with:
--- freq = 19.921875MHz
--- ampl = 0.5 * 2**13
+-- freq = 19.921875MHz = subband index 102
+-- ampl = 0.5 * 2**13, full scale amplitude is 2**13
--
-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
-- to trigger start of WG at BSN.
--
--- 3) Read subband statistics (SST) via ram_st_sst and verify with
--- c_exp_subband_power_sp_0 at c_subband_sp_0.
--- View sp_subband_power_0 in Wave window
---
+-- 3) Read crosslets statistics (XST) via ram_st_xsq and verify that the values
+-- are as expected. This is done by comparing the values in the outgoing square
+-- correlation matrix.
+--
--
-- Usage:
-- > as 7 # default
@@ -87,13 +87,13 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
- CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
+ CONSTANT c_FS_adc : REAL := REAL(c_sdp_FS_adc); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_FS_adc; -- amplitude in number of LSbit resolution steps
CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
-- WPFB
@@ -124,7 +124,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- WPFB
- SIGNAL xsub_stats_arr : t_slv_64_arr(0 TO c_nof_complex * c_sdp_S_pn**2 -1);
+ SIGNAL xsub_stats_arr : t_slv_64_arr(0 TO c_nof_complex * c_sdp_X_sq -1);
-- DUT
@@ -297,7 +297,7 @@ BEGIN
---------------------------------------------------------------------------
-- Read crosslet statistics
---------------------------------------------------------------------------
- FOR I IN 0 TO c_nof_complex * 144 * 2 -1 LOOP
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq * (c_longword_sz/c_word_sz) -1 LOOP
v_W := I MOD 2;
v_B := I / 2;
IF v_W=0 THEN
@@ -317,12 +317,12 @@ BEGIN
---------------------------------------------------------------------------
-- Verify crosslet statistics
---------------------------------------------------------------------------
- -- With all WGs having the same input all crosslets should be identical. Due to the filterbank
- -- the two signals in the output pairs per P_pfb differ slightly, therefore 3 slightly different
- -- correlation values are expected. 1 for each correlation between even indexed signals, 1 for
- -- odd indexed signals and 1 for correlations between even and odd indexed signals. This is verified by
- -- checking if these values are the same.
- FOR I IN 0 TO c_nof_complex * c_sdp_S_pn **2 -1 LOOP
+ -- With all WGs having the same input all crosslets should be identical. Due to quantization cross talk
+ -- between the two real inputs of the filterbank the two signals in the output pairs per P_pfb differ
+ -- slightly, therefore 3 slightly different correlation values are expected. 1 for each correlation
+ -- between even indexed signals, 1 for odd indexed signals and 1 for correlations between even and odd
+ -- indexed signals. This is verified by checking if these values are the same.
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq -1 LOOP
v_C := I MOD 2;
v_X := I /c_nof_complex;
v_A := v_X MOD c_sdp_S_pn;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 0a35a58be6f9fa1c4c6aea50c36021a2ada706e3..5de02153d5ac44c33052e7b95cdc3f3b8a08f4fb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -350,7 +350,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index cdeb290bef11bc5446e7225bc071794d900562f3..47b5fe4db662beeb34011a709bb341c35c57a558 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -75,7 +75,10 @@ ENTITY node_sdp_correlator IS
END node_sdp_correlator;
ARCHITECTURE str OF node_sdp_correlator IS
-
+
+ CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
+ CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
+
-- CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
@@ -126,8 +129,8 @@ BEGIN
u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
GENERIC MAP (
g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => c_sdp_dp_sync_insert_nof_blk_per_sync,
- g_nof_blk_per_sync_min => c_sdp_dp_sync_insert_nof_blk_per_sync_min
+ g_nof_blk_per_sync => c_nof_blk_per_sync_max,
+ g_nof_blk_per_sync_min => c_nof_blk_per_sync_min
)
PORT MAP (
dp_rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 72ad02ab1f2e6885fd13c8bebf27ce84a77d7807..1dcc7eb6199edd935626e70b344c926d1072a927 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -100,12 +100,14 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_subband : NATURAL := 18;
-- Derived constants
+ CONSTANT c_sdp_FS_adc : NATURAL := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft;
CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc;
CONSTANT c_sdp_W_bf_fraction : NATURAL := c_sdp_W_bf_weight - c_sdp_W_bf_magnitude -1;
CONSTANT c_sdp_W_bf_product : NATURAL := c_sdp_W_subband + c_sdp_W_bf_weight -1;
CONSTANT c_sdp_W_sub_fraction : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_magnitude -1;
+ CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn;
--
CONSTANT c_sdp_marker_sst : NATURAL := 83; -- = 0x53 = 'S'
@@ -185,14 +187,14 @@ PACKAGE sdp_pkg is
init_sl => '0');
CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
- CONSTANT c_sdp_dp_sync_insert_nof_blk_per_sync : NATURAL := 200000;
- CONSTANT c_sdp_dp_sync_insert_nof_blk_per_sync_min : NATURAL := 19530;
+ CONSTANT c_sdp_xst_nof_blk_per_sync_max : NATURAL := 200000;
+ CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
- -- XSUB MM adderss widths
+ -- XSUB MM address widths
CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_S_pn**2 * 2);
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
-- 10GbE offload (cep = central processor)
CONSTANT c_sdp_cep_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index ba841158b07c5399cc8468ae5a96089e98ef9742..6a03cbdc49a6395e090e4222ad068707e7ecdf5b 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -65,11 +65,6 @@ END st_xst;
ARCHITECTURE str OF st_xst IS
- CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
- CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
- CONSTANT c_nof_word : NATURAL := g_stat_data_sz*c_nof_statistics*c_nof_complex;
- CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
-
TYPE t_reg IS RECORD
busy : STD_LOGIC;
in_a_index : NATURAL;