From 70e234863703fc8ef153eeba27d397f875bcda13 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Thu, 17 Sep 2020 09:44:33 +0200 Subject: [PATCH] Initial commit of lofar2_unb2b_filterbank --- .../src/vhdl/lofar2_unb2b_filterbank.vhd | 1099 +++++++++-------- 1 file changed, 551 insertions(+), 548 deletions(-) diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd index e078f23fa3..dc35d01678 100644 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd @@ -1,548 +1,551 @@ -------------------------------------------------------------------------------- --- --- Copyright 2020 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- -------------------------------------------------------------------------------- - - --- Author : R vd Walle --- Purpose: --- Core design for Lofar2 Filterbank stage --- Description: --- Unb2b version for lab testing --- Use revisions to select one_node or full versions - -LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, lofar2_sdp_lib; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE common_lib.common_pkg.ALL; -USE common_lib.common_mem_pkg.ALL; -USE technology_lib.technology_pkg.ALL; -USE unb2b_board_lib.unb2b_board_pkg.ALL; -USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL; -USE diag_lib.diag_pkg.ALL; -USE dp_lib.dp_stream_pkg.ALL; -USE work.lofar2_unb2b_filterbank_pkg.ALL; -USE lofar2_sdp_lib.sdp_pkg.ALL; - -ENTITY lofar2_unb2b_filterbank IS - GENERIC ( - g_design_name : STRING := "lofar2_unb2b_filterbank"; - g_design_note : STRING := "UNUSED"; - g_technology : NATURAL := c_tech_arria10_e1sg; - g_buf_nof_data : NATURAL := 1024; - g_sim : BOOLEAN := FALSE; --Overridden by TB - g_sim_unb_nr : NATURAL := 0; - g_sim_node_nr : NATURAL := 0; - g_sim_model_ddr : BOOLEAN := FALSE; - g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF - g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF - g_revision_id : STRING := ""; -- revision ID -- set by QSF - g_factory_image : BOOLEAN := FALSE; - g_protect_addr_range: BOOLEAN := FALSE; - g_scope_selected_subband : NATURAL := 0 - ); - PORT ( - -- GENERAL - CLK : IN STD_LOGIC; -- System Clock - PPS : IN STD_LOGIC; -- System Sync - WDI : OUT STD_LOGIC; -- Watchdog Clear - INTA : INOUT STD_LOGIC; -- FPGA interconnect line - INTB : INOUT STD_LOGIC; -- FPGA interconnect line - - -- Others - VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); - ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); - TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); - - -- I2C Interface to Sensors - SENS_SC : INOUT STD_LOGIC; - SENS_SD : INOUT STD_LOGIC; - - PMBUS_SC : INOUT STD_LOGIC; - PMBUS_SD : INOUT STD_LOGIC; - PMBUS_ALERT : IN STD_LOGIC := '0'; - - -- 1GbE Control Interface - ETH_CLK : IN STD_LOGIC; - ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); - ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); - - -- LEDs - QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0); - - -- back transceivers (Note: numbered from 0) - JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); - -- Connect to the BCK_RX pins in the top wrapper - JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper - - -- jesd204b syncronization signals - JESD204B_SYSREF : IN STD_LOGIC; - JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0) - ); -END lofar2_unb2b_filterbank; - - -ARCHITECTURE str OF lofar2_unb2b_filterbank IS - - -- Revision parameters - CONSTANT c_revision_select : t_lofar2_unb2b_filterbank_config := func_sel_revision_rec(g_design_name); - CONSTANT c_nof_streams : NATURAL := c_revision_select.nof_streams_input; -- Streams actually passed through for processing - - -- Firmware version x.y - CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); - CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M; - CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS - - -- System - SIGNAL cs_sim : STD_LOGIC; - SIGNAL xo_ethclk : STD_LOGIC; - SIGNAL xo_rst : STD_LOGIC; - SIGNAL xo_rst_n : STD_LOGIC; - SIGNAL mm_clk : STD_LOGIC; - SIGNAL mm_rst : STD_LOGIC := '0'; - - SIGNAL dp_pps : STD_LOGIC; - SIGNAL dp_rst : STD_LOGIC; - SIGNAL dp_clk : STD_LOGIC; - - -- PIOs - SIGNAL pout_wdi : STD_LOGIC; - - -- WDI override - SIGNAL reg_wdi_mosi : t_mem_mosi; - SIGNAL reg_wdi_miso : t_mem_miso; - - -- PPSH - SIGNAL reg_ppsh_mosi : t_mem_mosi; - SIGNAL reg_ppsh_miso : t_mem_miso; - - -- UniBoard system info - SIGNAL reg_unb_system_info_mosi : t_mem_mosi; - SIGNAL reg_unb_system_info_miso : t_mem_miso; - SIGNAL rom_unb_system_info_mosi : t_mem_mosi; - SIGNAL rom_unb_system_info_miso : t_mem_miso; - - -- UniBoard I2C sens - SIGNAL reg_unb_sens_mosi : t_mem_mosi; - SIGNAL reg_unb_sens_miso : t_mem_miso; - - -- pm bus - SIGNAL reg_unb_pmbus_mosi : t_mem_mosi; - SIGNAL reg_unb_pmbus_miso : t_mem_miso; - - -- FPGA sensors - SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi; - SIGNAL reg_fpga_temp_sens_miso : t_mem_miso; - SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi; - SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso; - - -- eth1g - SIGNAL eth1g_mm_rst : STD_LOGIC; - SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers - SIGNAL eth1g_tse_miso : t_mem_miso; - SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers - SIGNAL eth1g_reg_miso : t_mem_miso; - SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt - SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory - SIGNAL eth1g_ram_miso : t_mem_miso; - - -- EPCS read - SIGNAL reg_dpmm_data_mosi : t_mem_mosi; - SIGNAL reg_dpmm_data_miso : t_mem_miso; - SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi; - SIGNAL reg_dpmm_ctrl_miso : t_mem_miso; - - -- EPCS write - SIGNAL reg_mmdp_data_mosi : t_mem_mosi; - SIGNAL reg_mmdp_data_miso : t_mem_miso; - SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi; - SIGNAL reg_mmdp_ctrl_miso : t_mem_miso; - - -- EPCS status/control - SIGNAL reg_epcs_mosi : t_mem_mosi; - SIGNAL reg_epcs_miso : t_mem_miso; - - -- Remote Update - SIGNAL reg_remu_mosi : t_mem_mosi; - SIGNAL reg_remu_miso : t_mem_miso; - - -- JESD - SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst; - - -- Shiftram (applies per-antenna delay) - SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst; - - -- bsn source - SIGNAL reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL reg_bsn_source_miso : t_mem_miso := c_mem_miso_rst; - - -- bsn scheduler - SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst; - - -- WG - SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst; - SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst; - SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst; - - -- BSN MONITOR - SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi; - SIGNAL reg_bsn_monitor_input_miso : t_mem_miso; - - -- Data buffer raw - SIGNAL ram_diag_data_buf_jesd_mosi: t_mem_mosi; - SIGNAL ram_diag_data_buf_jesd_miso: t_mem_miso; - SIGNAL reg_diag_data_buf_jesd_mosi: t_mem_mosi; - SIGNAL reg_diag_data_buf_jesd_miso: t_mem_miso; - - -- Data buffer bsn - SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi; - SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso; - SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi; - SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso; - - -- Aduh statistics monitor - SIGNAL ram_aduh_monitor_mosi : t_mem_mosi; - SIGNAL ram_aduh_monitor_miso : t_mem_miso; - SIGNAL reg_aduh_monitor_mosi : t_mem_mosi; - SIGNAL reg_aduh_monitor_miso : t_mem_miso; - - -- Subband statistics - SIGNAL ram_st_sst_mosi : t_mem_mosi; - SIGNAL ram_st_sst_miso : t_mem_miso; - - -- Spectral Inversion - SIGNAL reg_si_mosi : t_mem_mosi; - SIGNAL reg_si_miso : t_mem_miso; - - -- Filter coefficients - SIGNAL ram_fil_coefs_mosi : t_mem_mosi; - SIGNAL ram_fil_coefs_miso : t_mem_miso; - - -- QSFP leds - SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); - SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); - - SIGNAL alt_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); - SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); - - - -BEGIN - - ----------------------------------------------------------------------------- - -- General control function - ----------------------------------------------------------------------------- - u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board - GENERIC MAP ( - g_sim => g_sim, - g_technology => g_technology, - g_design_name => g_design_name, - g_design_note => g_design_note, - g_stamp_date => g_stamp_date, - g_stamp_time => g_stamp_time, - g_revision_id => g_revision_id, - g_fw_version => c_fw_version, - g_mm_clk_freq => c_mm_clk_freq, - g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, - g_aux => c_unb2b_board_aux, - g_factory_image => g_factory_image, - g_protect_addr_range => g_protect_addr_range, - g_dp_clk_use_pll => FALSE - ) - PORT MAP ( - -- Clock an reset signals - cs_sim => cs_sim, - xo_ethclk => xo_ethclk, - xo_rst => xo_rst, - xo_rst_n => xo_rst_n, - - mm_clk => mm_clk, - mm_rst => mm_rst, - - dp_rst => dp_rst, - dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated - dp_pps => dp_pps, - dp_rst_in => dp_rst, - dp_clk_in => dp_clk, - - -- Toggle WDI - pout_wdi => pout_wdi, - - -- MM buses - -- REMU - reg_remu_mosi => reg_remu_mosi, - reg_remu_miso => reg_remu_miso, - - -- EPCS read - reg_dpmm_data_mosi => reg_dpmm_data_mosi, - reg_dpmm_data_miso => reg_dpmm_data_miso, - reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, - reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, - - -- EPCS write - reg_mmdp_data_mosi => reg_mmdp_data_mosi, - reg_mmdp_data_miso => reg_mmdp_data_miso, - reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, - reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, - - -- EPCS status/control - reg_epcs_mosi => reg_epcs_mosi, - reg_epcs_miso => reg_epcs_miso, - - -- . Manual WDI override - reg_wdi_mosi => reg_wdi_mosi, - reg_wdi_miso => reg_wdi_miso, - - -- . System_info - reg_unb_system_info_mosi => reg_unb_system_info_mosi, - reg_unb_system_info_miso => reg_unb_system_info_miso, - rom_unb_system_info_mosi => rom_unb_system_info_mosi, - rom_unb_system_info_miso => rom_unb_system_info_miso, - - -- . UniBoard I2C sensors - reg_unb_sens_mosi => reg_unb_sens_mosi, - reg_unb_sens_miso => reg_unb_sens_miso, - - -- . FPGA sensors - reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, - reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, - reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, - reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, - - reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, - reg_unb_pmbus_miso => reg_unb_pmbus_miso, - - -- . PPSH - reg_ppsh_mosi => reg_ppsh_mosi, - reg_ppsh_miso => reg_ppsh_miso, - - -- eth1g - eth1g_mm_rst => eth1g_mm_rst, - eth1g_tse_mosi => eth1g_tse_mosi, - eth1g_tse_miso => eth1g_tse_miso, - eth1g_reg_mosi => eth1g_reg_mosi, - eth1g_reg_miso => eth1g_reg_miso, - eth1g_reg_interrupt => eth1g_reg_interrupt, - eth1g_ram_mosi => eth1g_ram_mosi, - eth1g_ram_miso => eth1g_ram_miso, - - ram_scrap_mosi => c_mem_mosi_rst, - ram_scrap_miso => open, - - -- FPGA pins - -- . General - CLK => CLK, - PPS => PPS, - WDI => WDI, - INTA => INTA, - INTB => INTB, - -- . Others - VERSION => VERSION, - ID => ID, - TESTIO => TESTIO, - -- . I2C Interface to Sensors - SENS_SC => SENS_SC, - SENS_SD => SENS_SD, - -- PM bus - PMBUS_SC => PMBUS_SC, - PMBUS_SD => PMBUS_SD, - PMBUS_ALERT => PMBUS_ALERT, - - -- . 1GbE Control Interface - ETH_clk => ETH_CLK, - ETH_SGIN => ETH_SGIN, - ETH_SGOUT => ETH_SGOUT - ); - - ----------------------------------------------------------------------------- - -- MM master - ----------------------------------------------------------------------------- - u_mmm : ENTITY work.mmm_lofar2_unb2b_filterbank - GENERIC MAP ( - g_sim => g_sim, - g_sim_unb_nr => g_sim_unb_nr, - g_sim_node_nr => g_sim_node_nr - ) - PORT MAP( - mm_rst => mm_rst, - mm_clk => mm_clk, - - -- PIOs - pout_wdi => pout_wdi, - - -- mm interfaces for control - reg_wdi_mosi => reg_wdi_mosi, - reg_wdi_miso => reg_wdi_miso, - reg_unb_system_info_mosi => reg_unb_system_info_mosi, - reg_unb_system_info_miso => reg_unb_system_info_miso, - rom_unb_system_info_mosi => rom_unb_system_info_mosi, - rom_unb_system_info_miso => rom_unb_system_info_miso, - reg_unb_sens_mosi => reg_unb_sens_mosi, - reg_unb_sens_miso => reg_unb_sens_miso, - reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, - reg_unb_pmbus_miso => reg_unb_pmbus_miso, - reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, - reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, - reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, - reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, - reg_ppsh_mosi => reg_ppsh_mosi, - reg_ppsh_miso => reg_ppsh_miso, - eth1g_mm_rst => eth1g_mm_rst, - eth1g_tse_mosi => eth1g_tse_mosi, - eth1g_tse_miso => eth1g_tse_miso, - eth1g_reg_mosi => eth1g_reg_mosi, - eth1g_reg_miso => eth1g_reg_miso, - eth1g_reg_interrupt => eth1g_reg_interrupt, - eth1g_ram_mosi => eth1g_ram_mosi, - eth1g_ram_miso => eth1g_ram_miso, - reg_dpmm_data_mosi => reg_dpmm_data_mosi, - reg_dpmm_data_miso => reg_dpmm_data_miso, - reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, - reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, - reg_mmdp_data_mosi => reg_mmdp_data_mosi, - reg_mmdp_data_miso => reg_mmdp_data_miso, - reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, - reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, - reg_epcs_mosi => reg_epcs_mosi, - reg_epcs_miso => reg_epcs_miso, - reg_remu_mosi => reg_remu_mosi, - reg_remu_miso => reg_remu_miso, - - -- mm buses for signal flow blocks - -- Jesd ip status/control - jesd204b_mosi => jesd204b_mosi, - jesd204b_miso => jesd204b_miso, - reg_dp_shiftram_mosi => reg_dp_shiftram_mosi, - reg_dp_shiftram_miso => reg_dp_shiftram_miso, - reg_bsn_source_mosi => reg_bsn_source_mosi, - reg_bsn_source_miso => reg_bsn_source_miso, - reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi, - reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso, - reg_wg_mosi => reg_wg_mosi, - reg_wg_miso => reg_wg_miso, - ram_wg_mosi => ram_wg_mosi, - ram_wg_miso => ram_wg_miso, - reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi, - reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso, - ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi, - ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso, - reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi, - reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso, - ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi, - ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso, - reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi, - reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso, - ram_aduh_monitor_mosi => ram_aduh_monitor_mosi, - ram_aduh_monitor_miso => ram_aduh_monitor_miso, - reg_aduh_monitor_mosi => reg_aduh_monitor_mosi, - reg_aduh_monitor_miso => reg_aduh_monitor_miso, - ram_st_sst_mosi => ram_st_sst_mosi, - ram_st_sst_miso => ram_st_sst_miso, - ram_fil_coefs_mosi => ram_fil_coefs_mosi, - ram_fil_coefs_miso => ram_fil_coefs_miso, - reg_si_mosi => reg_si_mosi, - reg_si_miso => reg_si_miso - - ); - - - ----------------------------------------------------------------------------- - -- node_adc_input_and_timing (AIT) - -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics - ----------------------------------------------------------------------------- - - u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing - GENERIC MAP( - g_technology => g_technology, - g_nof_streams => c_nof_streams, - g_sim => g_sim - ) - PORT MAP( - -- clocks and resets - mm_clk => mm_clk, - mm_rst => mm_rst, - dp_clk => dp_clk, - dp_rst => dp_rst, - - -- mm control buses - jesd204b_mosi => jesd204b_mosi, - jesd204b_miso => jesd204b_miso, - reg_dp_shiftram_mosi => reg_dp_shiftram_mosi, - reg_dp_shiftram_miso => reg_dp_shiftram_miso, - reg_bsn_source_mosi => reg_bsn_source_mosi, - reg_bsn_source_miso => reg_bsn_source_miso, - reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi, - reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso, - reg_wg_mosi => reg_wg_mosi, - reg_wg_miso => reg_wg_miso, - ram_wg_mosi => ram_wg_mosi, - ram_wg_miso => ram_wg_miso, - reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi, - reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso, - ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi, - ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso, - reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi, - reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso, - ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi, - ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso, - reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi, - reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso, - ram_aduh_monitor_mosi => ram_aduh_monitor_mosi, - ram_aduh_monitor_miso => ram_aduh_monitor_miso, - reg_aduh_monitor_mosi => reg_aduh_monitor_mosi, - reg_aduh_monitor_miso => reg_aduh_monitor_miso, - - -- Jesd external IOs - jesd204b_serial_data => JESD204B_SERIAL_DATA, - jesd204b_refclk => JESD204B_REFCLK, - jesd204b_sysref => JESD204B_SYSREF, - jesd204b_sync_n => JESD204B_SYNC_N, - - -- Streaming data output - out_sosi_arr => alt_sosi_arr - ); - - - u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank - GENERIC MAP( - g_sim => g_sim, - g_scope_selected_subband => g_scope_selected_subband - ) - PORT MAP( - dp_clk => dp_clk, - dp_rst => dp_rst, - - in_sosi_arr => alt_sosi_arr, - pfb_sosi_arr => pfb_sosi_arr, - - mm_rst => mm_rst, - mm_clk => mm_clk, - - reg_si_mosi => reg_si_mosi, - reg_si_miso => reg_si_miso, - ram_st_sst_mosi => ram_st_sst_mosi, - ram_st_sst_miso => ram_st_sst_miso, - ram_fil_coefs_mosi => ram_fil_coefs_mosi, - ram_fil_coefs_miso => ram_fil_coefs_miso - ); - -END str; +------------------------------------------------------------------------------- +-- +-- Copyright 2020 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Author : R vd Walle +-- Purpose: +-- Core design for Lofar2 Filterbank stage +-- Description: +-- Unb2b version for lab testing +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE unb2b_board_lib.unb2b_board_pkg.ALL; +USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL; +USE diag_lib.diag_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE wpfb_lib.wpfb_pkg.ALL; +USE lofar2_sdp_lib.sdp_pkg.ALL; +USE work.lofar2_unb2b_filterbank_pkg.ALL; + +ENTITY lofar2_unb2b_filterbank IS + GENERIC ( + g_design_name : STRING := "lofar2_unb2b_filterbank"; + g_design_note : STRING := "UNUSED"; + g_technology : NATURAL := c_tech_arria10_e1sg; + g_buf_nof_data : NATURAL := 1024; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_sim_model_ddr : BOOLEAN := FALSE; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_revision_id : STRING := ""; -- revision ID -- set by QSF + g_factory_image : BOOLEAN := FALSE; + g_protect_addr_range : BOOLEAN := FALSE; + g_wpfb : t_wpfb := c_sdp_wpfb_subbands; + g_scope_selected_subband : NATURAL := 0 + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + SENS_SC : INOUT STD_LOGIC; + SENS_SD : INOUT STD_LOGIC; + + PMBUS_SC : INOUT STD_LOGIC; + PMBUS_SD : INOUT STD_LOGIC; + PMBUS_ALERT : IN STD_LOGIC := '0'; + + -- 1GbE Control Interface + ETH_CLK : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0); + + -- LEDs + QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0); + + -- back transceivers (Note: numbered from 0) + JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); + -- Connect to the BCK_RX pins in the top wrapper + JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper + + -- jesd204b syncronization signals + JESD204B_SYSREF : IN STD_LOGIC; + JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0) + ); +END lofar2_unb2b_filterbank; + + +ARCHITECTURE str OF lofar2_unb2b_filterbank IS + + -- Revision parameters + CONSTANT c_revision_select : t_lofar2_unb2b_filterbank_config := func_sel_revision_rec(g_design_name); + CONSTANT c_nof_streams : NATURAL := c_revision_select.nof_streams_input; -- Streams actually passed through for processing + + -- Firmware version x.y + CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); + CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M; + CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS + + -- System + SIGNAL cs_sim : STD_LOGIC; + SIGNAL xo_ethclk : STD_LOGIC; + SIGNAL xo_rst : STD_LOGIC; + SIGNAL xo_rst_n : STD_LOGIC; + SIGNAL mm_clk : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC := '0'; + + SIGNAL dp_pps : STD_LOGIC; + SIGNAL dp_rst : STD_LOGIC; + SIGNAL dp_clk : STD_LOGIC; + + -- PIOs + SIGNAL pout_wdi : STD_LOGIC; + + -- WDI override + SIGNAL reg_wdi_mosi : t_mem_mosi; + SIGNAL reg_wdi_miso : t_mem_miso; + + -- PPSH + SIGNAL reg_ppsh_mosi : t_mem_mosi; + SIGNAL reg_ppsh_miso : t_mem_miso; + + -- UniBoard system info + SIGNAL reg_unb_system_info_mosi : t_mem_mosi; + SIGNAL reg_unb_system_info_miso : t_mem_miso; + SIGNAL rom_unb_system_info_mosi : t_mem_mosi; + SIGNAL rom_unb_system_info_miso : t_mem_miso; + + -- UniBoard I2C sens + SIGNAL reg_unb_sens_mosi : t_mem_mosi; + SIGNAL reg_unb_sens_miso : t_mem_miso; + + -- pm bus + SIGNAL reg_unb_pmbus_mosi : t_mem_mosi; + SIGNAL reg_unb_pmbus_miso : t_mem_miso; + + -- FPGA sensors + SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi; + SIGNAL reg_fpga_temp_sens_miso : t_mem_miso; + SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi; + SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso; + + -- eth1g + SIGNAL eth1g_mm_rst : STD_LOGIC; + SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers + SIGNAL eth1g_tse_miso : t_mem_miso; + SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers + SIGNAL eth1g_reg_miso : t_mem_miso; + SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt + SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory + SIGNAL eth1g_ram_miso : t_mem_miso; + + -- EPCS read + SIGNAL reg_dpmm_data_mosi : t_mem_mosi; + SIGNAL reg_dpmm_data_miso : t_mem_miso; + SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi; + SIGNAL reg_dpmm_ctrl_miso : t_mem_miso; + + -- EPCS write + SIGNAL reg_mmdp_data_mosi : t_mem_mosi; + SIGNAL reg_mmdp_data_miso : t_mem_miso; + SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi; + SIGNAL reg_mmdp_ctrl_miso : t_mem_miso; + + -- EPCS status/control + SIGNAL reg_epcs_mosi : t_mem_mosi; + SIGNAL reg_epcs_miso : t_mem_miso; + + -- Remote Update + SIGNAL reg_remu_mosi : t_mem_mosi; + SIGNAL reg_remu_miso : t_mem_miso; + + -- JESD + SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst; + + -- Shiftram (applies per-antenna delay) + SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst; + + -- bsn source + SIGNAL reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_bsn_source_miso : t_mem_miso := c_mem_miso_rst; + + -- bsn scheduler + SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst; + + -- WG + SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst; + SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst; + + -- BSN MONITOR + SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi; + SIGNAL reg_bsn_monitor_input_miso : t_mem_miso; + + -- Data buffer raw + SIGNAL ram_diag_data_buf_jesd_mosi: t_mem_mosi; + SIGNAL ram_diag_data_buf_jesd_miso: t_mem_miso; + SIGNAL reg_diag_data_buf_jesd_mosi: t_mem_mosi; + SIGNAL reg_diag_data_buf_jesd_miso: t_mem_miso; + + -- Data buffer bsn + SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi; + SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso; + SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi; + SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso; + + -- Aduh statistics monitor + SIGNAL ram_aduh_monitor_mosi : t_mem_mosi; + SIGNAL ram_aduh_monitor_miso : t_mem_miso; + SIGNAL reg_aduh_monitor_mosi : t_mem_mosi; + SIGNAL reg_aduh_monitor_miso : t_mem_miso; + + -- Subband statistics + SIGNAL ram_st_sst_mosi : t_mem_mosi; + SIGNAL ram_st_sst_miso : t_mem_miso; + + -- Spectral Inversion + SIGNAL reg_si_mosi : t_mem_mosi; + SIGNAL reg_si_miso : t_mem_miso; + + -- Filter coefficients + SIGNAL ram_fil_coefs_mosi : t_mem_mosi; + SIGNAL ram_fil_coefs_miso : t_mem_miso; + + -- QSFP leds + SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0); + + SIGNAL alt_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); + SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); + + + +BEGIN + + ----------------------------------------------------------------------------- + -- General control function + ----------------------------------------------------------------------------- + u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board + GENERIC MAP ( + g_sim => g_sim, + g_technology => g_technology, + g_design_name => g_design_name, + g_design_note => g_design_note, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_revision_id => g_revision_id, + g_fw_version => c_fw_version, + g_mm_clk_freq => c_mm_clk_freq, + g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, + g_aux => c_unb2b_board_aux, + g_factory_image => g_factory_image, + g_protect_addr_range => g_protect_addr_range, + g_dp_clk_use_pll => FALSE + ) + PORT MAP ( + -- Clock an reset signals + cs_sim => cs_sim, + xo_ethclk => xo_ethclk, + xo_rst => xo_rst, + xo_rst_n => xo_rst_n, + + mm_clk => mm_clk, + mm_rst => mm_rst, + + dp_rst => dp_rst, + dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated + dp_pps => dp_pps, + dp_rst_in => dp_rst, + dp_clk_in => dp_clk, + + -- Toggle WDI + pout_wdi => pout_wdi, + + -- MM buses + -- REMU + reg_remu_mosi => reg_remu_mosi, + reg_remu_miso => reg_remu_miso, + + -- EPCS read + reg_dpmm_data_mosi => reg_dpmm_data_mosi, + reg_dpmm_data_miso => reg_dpmm_data_miso, + reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, + reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, + + -- EPCS write + reg_mmdp_data_mosi => reg_mmdp_data_mosi, + reg_mmdp_data_miso => reg_mmdp_data_miso, + reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, + reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, + + -- EPCS status/control + reg_epcs_mosi => reg_epcs_mosi, + reg_epcs_miso => reg_epcs_miso, + + -- . Manual WDI override + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + + -- . System_info + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + + -- . UniBoard I2C sensors + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + + -- . FPGA sensors + reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, + reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, + reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, + reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, + + reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, + reg_unb_pmbus_miso => reg_unb_pmbus_miso, + + -- . PPSH + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + + -- eth1g + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + + ram_scrap_mosi => c_mem_mosi_rst, + ram_scrap_miso => open, + + -- FPGA pins + -- . General + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + -- . Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + -- . I2C Interface to Sensors + SENS_SC => SENS_SC, + SENS_SD => SENS_SD, + -- PM bus + PMBUS_SC => PMBUS_SC, + PMBUS_SD => PMBUS_SD, + PMBUS_ALERT => PMBUS_ALERT, + + -- . 1GbE Control Interface + ETH_clk => ETH_CLK, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT + ); + + ----------------------------------------------------------------------------- + -- MM master + ----------------------------------------------------------------------------- + u_mmm : ENTITY work.mmm_lofar2_unb2b_filterbank + GENERIC MAP ( + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr + ) + PORT MAP( + mm_rst => mm_rst, + mm_clk => mm_clk, + + -- PIOs + pout_wdi => pout_wdi, + + -- mm interfaces for control + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + reg_unb_pmbus_mosi => reg_unb_pmbus_mosi, + reg_unb_pmbus_miso => reg_unb_pmbus_miso, + reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi, + reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso, + reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi, + reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso, + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + reg_dpmm_data_mosi => reg_dpmm_data_mosi, + reg_dpmm_data_miso => reg_dpmm_data_miso, + reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi, + reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso, + reg_mmdp_data_mosi => reg_mmdp_data_mosi, + reg_mmdp_data_miso => reg_mmdp_data_miso, + reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi, + reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso, + reg_epcs_mosi => reg_epcs_mosi, + reg_epcs_miso => reg_epcs_miso, + reg_remu_mosi => reg_remu_mosi, + reg_remu_miso => reg_remu_miso, + + -- mm buses for signal flow blocks + -- Jesd ip status/control + jesd204b_mosi => jesd204b_mosi, + jesd204b_miso => jesd204b_miso, + reg_dp_shiftram_mosi => reg_dp_shiftram_mosi, + reg_dp_shiftram_miso => reg_dp_shiftram_miso, + reg_bsn_source_mosi => reg_bsn_source_mosi, + reg_bsn_source_miso => reg_bsn_source_miso, + reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi, + reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso, + reg_wg_mosi => reg_wg_mosi, + reg_wg_miso => reg_wg_miso, + ram_wg_mosi => ram_wg_mosi, + ram_wg_miso => ram_wg_miso, + reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi, + reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso, + ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi, + ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso, + reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi, + reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso, + ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi, + ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso, + reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi, + reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso, + ram_aduh_monitor_mosi => ram_aduh_monitor_mosi, + ram_aduh_monitor_miso => ram_aduh_monitor_miso, + reg_aduh_monitor_mosi => reg_aduh_monitor_mosi, + reg_aduh_monitor_miso => reg_aduh_monitor_miso, + ram_st_sst_mosi => ram_st_sst_mosi, + ram_st_sst_miso => ram_st_sst_miso, + ram_fil_coefs_mosi => ram_fil_coefs_mosi, + ram_fil_coefs_miso => ram_fil_coefs_miso, + reg_si_mosi => reg_si_mosi, + reg_si_miso => reg_si_miso + + ); + + + ----------------------------------------------------------------------------- + -- node_adc_input_and_timing (AIT) + -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics + ----------------------------------------------------------------------------- + + u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing + GENERIC MAP( + g_technology => g_technology, + g_nof_streams => c_nof_streams, + g_sim => g_sim + ) + PORT MAP( + -- clocks and resets + mm_clk => mm_clk, + mm_rst => mm_rst, + dp_clk => dp_clk, + dp_rst => dp_rst, + + -- mm control buses + jesd204b_mosi => jesd204b_mosi, + jesd204b_miso => jesd204b_miso, + reg_dp_shiftram_mosi => reg_dp_shiftram_mosi, + reg_dp_shiftram_miso => reg_dp_shiftram_miso, + reg_bsn_source_mosi => reg_bsn_source_mosi, + reg_bsn_source_miso => reg_bsn_source_miso, + reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi, + reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso, + reg_wg_mosi => reg_wg_mosi, + reg_wg_miso => reg_wg_miso, + ram_wg_mosi => ram_wg_mosi, + ram_wg_miso => ram_wg_miso, + reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi, + reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso, + ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi, + ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso, + reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi, + reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso, + ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi, + ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso, + reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi, + reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso, + ram_aduh_monitor_mosi => ram_aduh_monitor_mosi, + ram_aduh_monitor_miso => ram_aduh_monitor_miso, + reg_aduh_monitor_mosi => reg_aduh_monitor_mosi, + reg_aduh_monitor_miso => reg_aduh_monitor_miso, + + -- Jesd external IOs + jesd204b_serial_data => JESD204B_SERIAL_DATA, + jesd204b_refclk => JESD204B_REFCLK, + jesd204b_sysref => JESD204B_SYSREF, + jesd204b_sync_n => JESD204B_SYNC_N, + + -- Streaming data output + out_sosi_arr => alt_sosi_arr + ); + + + u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank + GENERIC MAP( + g_sim => g_sim, + g_wpfb => g_wpfb, + g_scope_selected_subband => g_scope_selected_subband + ) + PORT MAP( + dp_clk => dp_clk, + dp_rst => dp_rst, + + in_sosi_arr => alt_sosi_arr, + pfb_sosi_arr => pfb_sosi_arr, + + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_si_mosi => reg_si_mosi, + reg_si_miso => reg_si_miso, + ram_st_sst_mosi => ram_st_sst_mosi, + ram_st_sst_miso => ram_st_sst_miso, + ram_fil_coefs_mosi => ram_fil_coefs_mosi, + ram_fil_coefs_miso => ram_fil_coefs_miso + ); + +END str; -- GitLab