diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index a0b631478170270ef273984a45003e2bb0fc17ea..8b6e2a19186c5671df11a252320d40ad877dcd7c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -95,6 +95,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
CONSTANT c_mm_file_reg_bsn_buf : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_BUF";
CONSTANT c_mm_file_ram_bsn_buf : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BSN_BUF";
CONSTANT c_mm_file_reg_rx_seq_bsn : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RX_SEQ_BSN";
+ CONSTANT c_mm_file_reg_ddrctrl_ctrl_state : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DDRCTRL_CTRL_STATE";
-- c_check_vector
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
@@ -137,6 +138,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
SIGNAL sosi_out_data_sin : STD_LOGIC_VECTOR( c_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sosi_out_not_bsn : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ SIGNAL out_ddrctrl_ctrl_state : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
+
+
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
@@ -277,6 +282,7 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
WAIT FOR c_mm_clk_period*50000;
+ mmf_mm_bus_rd(c_mm_file_reg_ddrctrl_ctrl_state, 0, out_ddrctrl_ctrl_state, tb_clk);
FOR I IN 0 TO c_bim-1 LOOP
FOR J IN 0 TO c_nof_streams-1 LOOP
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 7dd206f9186d5010e0f2f3c0d6c16406a8432055..47c2d2c826d8e00239a2d7c17a9e3d17c3236620 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -139,10 +139,16 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL data_stopped : STD_LOGIC;
+ SIGNAL state_vec : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL ddrctrl_ctrl_state_local : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+
BEGIN
rd_siso.ready <= rd_ready;
rd_siso.xon <= '1';
+ ddrctrl_ctrl_state(5 DOWNTO 0) <= ddrctrl_ctrl_state_local(5 DOWNTO 0);
+ ddrctrl_ctrl_state(7 DOWNTO 6) <= state_vec(1 DOWNTO 0);
+ ddrctrl_ctrl_state(32-1 DOWNTO 8) <= ddrctrl_ctrl_state_local(32-1 DOWNTO 8);
-- input to io_ddr
u_ddrctrl_input : ENTITY work.ddrctrl_input
@@ -203,6 +209,7 @@ BEGIN
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
+ state_vec => state_vec,
-- Driver clock domain
dvr_clk => clk,
@@ -309,7 +316,7 @@ BEGIN
-- ddrctrl_controller
stop_in => stop_in,
stop_out => stop,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index c6ccdf9715f260b4ec2d2e3ac6949cd0a7e764b0..2ef30499d20dda8f4a1016aaad784968df3f1d4f 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_bitshift_w : NATURAL := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- CONSTANT c_pof_ma : NATURAL := NATURAL((((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/REAL(g_adr_per_b))*REAL(g_adr_per_b)); --percentage of max address.
+ CONSTANT c_pof_ma : NATURAL := ((NATURAL((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/g_adr_per_b)*g_adr_per_b); --percentage of max address.
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
@@ -98,6 +98,13 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
+ -- constant for debugging
+ CONSTANT c_always_one_ndx : NATURAL := 0;
+ CONSTANT c_rst_ndx : NATURAL := 1;
+ CONSTANT c_low_state_ndx : NATURAL := 2;
+ CONSTANT c_high_state_ndx : NATURAL := 5;
+ CONSTANT c_state_ndx_w : NATURAL := c_high_state_ndx-c_low_state_ndx+1;
+
-- type for statemachine
TYPE t_state IS (RESET, STOP_READING, WAIT_FOR_SOP, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING);
@@ -155,12 +162,13 @@ BEGIN
CASE q_reg.state IS
WHEN RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
- v.dvr_mosi.wr := '1';
- v.wr_sosi.valid := '1';
- v.ddrctrl_ctrl_state(32-1) := rst;
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
+ v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+ v.ddrctrl_ctrl_state(c_rst_ndx) := rst;
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
IF rst = '0' THEN
v.state := STOP_READING;
@@ -168,7 +176,7 @@ BEGIN
WHEN STOP_READING =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(1, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
-- this is the last read burst, this make sure every data containing word in the memory has been read.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
@@ -191,7 +199,7 @@ BEGIN
WHEN WAIT_FOR_SOP =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(2, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
v.dvr_mosi.burstbegin := '0';
v.rst_ddrctrl_input_ac := '0';
IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
@@ -204,7 +212,7 @@ BEGIN
WHEN WRITING =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(3, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
-- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF q_reg.wr_bursts_ready >= 1 AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
@@ -242,7 +250,7 @@ BEGIN
WHEN SET_STOP =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(4, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
-- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr-c_pof_ma >= 0 THEN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w);
@@ -292,7 +300,7 @@ BEGIN
WHEN STOP_WRITING =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(5, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
-- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
@@ -329,7 +337,7 @@ BEGIN
WHEN LAST_WRITE_BURST =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(6, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
v.wr_sosi.valid := '0';
IF dvr_miso.done = '1' THEN
@@ -351,7 +359,7 @@ BEGIN
WHEN START_READING =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(7, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0';
v.outp_bsn := INCR_UVEC(inp_sosi.bsn,-1*g_bim);
@@ -381,7 +389,7 @@ BEGIN
WHEN READING =>
- v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(8, 32);
+ v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
v.wr_sosi.valid := '0';
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
@@ -424,6 +432,8 @@ BEGIN
v.started := '1';
END IF;
+ v.ddrctrl_ctrl_state(c_always_one_ndx) := '1';
+
d_reg <= v;
END PROCESS;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 853199c9c07570a6fe52ae9b34caffc9a0717105..1c9f5effb8ebcd447806fc3e44b69113220974af 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -186,6 +186,7 @@ ENTITY io_ddr IS
-- MM interface
reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- register for DDR controller status info
reg_io_ddr_miso : OUT t_mem_miso;
+ state_vec : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-- Driver clock domain
dvr_clk : IN STD_LOGIC;
@@ -398,7 +399,8 @@ BEGIN
ctlr_wr_sosi => ctlr_wr_flush_snk_in,
-- Output
- ctlr_wr_flush_en => ctlr_wr_flush_en
+ ctlr_wr_flush_en => ctlr_wr_flush_en,
+ state_vec => state_vec
);
ASSERT g_rd_fifo_depth>c_rd_fifo_af_margin REPORT "io_ddr: rd FIFO depth must be > almost full margin." SEVERITY FAILURE;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index 1c0eee46482f16d29dbddf2bf343abd9de9ba9aa..455b4d2315fc388cbf41fdccccfa8abeec2e1e0e 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -60,7 +60,8 @@ ENTITY io_ddr_driver_flush_ctrl IS
ctlr_wr_sosi : IN t_dp_sosi;
-- Output
- ctlr_wr_flush_en : OUT STD_LOGIC
+ ctlr_wr_flush_en : OUT STD_LOGIC;
+ state_vec : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END io_ddr_driver_flush_ctrl;
@@ -114,16 +115,19 @@ BEGIN
nxt_ctlr_wr_flush_en <= '0';
CASE state IS
WHEN s_idle =>
+ state_vec <= TO_UVEC(1, 2);
IF dvr_wr_flush_en='1' AND dvr_done='1' THEN
nxt_ctlr_wr_flush_en <= '1';
nxt_state <= s_flush;
END IF;
WHEN s_flush =>
+ state_vec <= TO_UVEC(2, 2);
nxt_ctlr_wr_flush_en <= '1';
IF dvr_en='1' AND dvr_wr_not_rd='1' THEN
nxt_state <= s_stop;
END IF;
WHEN OTHERS => -- s_stop
+ state_vec <= TO_UVEC(3, 2);
nxt_ctlr_wr_flush_en <= '1';
IF flush_dis = '1' THEN -- flush_dis comes from sosi control (valid, sop or sync) from look ahead (RL=0) write FIFO
nxt_ctlr_wr_flush_en <= '0';