From 70c040a8536ae4a9dfdc597fe4e755bd9d5decb9 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Fri, 8 Mar 2024 07:45:44 +0100
Subject: [PATCH] Use sdp_beamformer_remote.vhd
---
applications/lofar2/libraries/sdp/hdllib.cfg | 3 +
.../sdp/src/vhdl/node_sdp_correlator.vhd | 211 +++---------------
2 files changed, 29 insertions(+), 185 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 7ad34980c3..f9d9833330 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -22,6 +22,7 @@ synth_files =
src/vhdl/sdp_beamformer_output.vhd
src/vhdl/sdp_statistics_offload.vhd
src/vhdl/sdp_crosslets_subband_select.vhd
+ src/vhdl/sdp_crosslets_remote.vhd
src/vhdl/node_sdp_adc_input_and_timing.vhd
src/vhdl/node_sdp_filterbank.vhd
src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -38,6 +39,7 @@ test_bench_files =
tb/vhdl/tb_sdp_beamformer_output.vhd
tb/vhdl/tb_tb_sdp_beamformer_output.vhd
tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+ tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
regression_test_vhdl =
tb/vhdl/tb_sdp_info.vhd
@@ -46,6 +48,7 @@ regression_test_vhdl =
tb/vhdl/tb_sdp_crosslets_subband_select.vhd
tb/vhdl/tb_tb_sdp_beamformer_output.vhd
tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+ tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
[modelsim_project_file]
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index d5c96ea99d..9a1d0fe6f2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -94,20 +94,8 @@ end node_sdp_correlator;
architecture str of node_sdp_correlator is
constant c_nof_controllers : positive := 2;
- constant c_block_size : natural := c_sdp_N_crosslets_max * c_sdp_S_pn;
- constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
- constant c_data_w : natural := c_sdp_W_crosslet * c_nof_complex;
-
--- The size for 1 block is probably already enough as the number of blocks received
--- on the remote input of the mux probably have enough gap time in between. Just
--- to be sure to not run into issues in the future, the fifo size is increased to
--- buffer the maximum nof blocks per block period.
- constant c_mux_fifo_size : natural := 2**ceil_log2(g_P_sq * c_block_size_longwords);
--- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
--- repacks from 64bit to 32bit. Chosing 3x to have some room.
- constant c_fifo_fill_size : natural := 2**ceil_log2(3 * c_block_size_longwords);
-
--- crosslet statistics offload
+
+ -- crosslet statistics offload
signal ram_st_offload_copi : t_mem_copi := c_mem_copi_rst;
signal ram_st_offload_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -117,21 +105,9 @@ architecture str of node_sdp_correlator is
signal controller_cipo_arr : t_mem_cipo_arr(0 to c_nof_controllers - 1) := (others => c_mem_cipo_rst);
signal quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
signal xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal xsel_data_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
-
signal new_interval : std_logic;
- signal ring_mux_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal ring_mux_siso : t_dp_siso := c_dp_siso_rdy;
- signal dp_fifo_fill_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal dp_fifo_fill_siso : t_dp_siso := c_dp_siso_rdy;
- signal rx_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal dispatch_invert_sosi_arr : t_dp_sosi_arr(0 to g_P_sq - 1) := (others => c_dp_sosi_rst);
- signal dispatch_sosi_arr : t_dp_sosi_arr(g_P_sq - 1 downto 0) := (others => c_dp_sosi_rst);
-
signal crosslets_sosi : t_dp_sosi := c_dp_sosi_rst;
signal crosslets_copi : t_mem_copi := c_mem_copi_rst;
signal crosslets_cipo_arr : t_mem_cipo_arr(g_P_sq - 1 downto 0) := (others => c_mem_cipo_rst);
@@ -203,168 +179,33 @@ begin
xst_bs_sosi <= xsel_sosi;
---------------------------------------------------------------
- -- Repack 32b to 64b
- ---------------------------------------------------------------
- -- repacking xsel re/im to data field.
- p_wire_xsel_sosi : process(xsel_sosi)
- begin
- xsel_data_sosi <= xsel_sosi;
- xsel_data_sosi.data( c_sdp_W_crosslet - 1 downto 0) <= xsel_sosi.re(c_sdp_W_crosslet - 1 downto 0);
- xsel_data_sosi.data(c_nof_complex * c_sdp_W_crosslet - 1 downto c_sdp_W_crosslet) <= xsel_sosi.im(c_sdp_W_crosslet - 1 downto 0);
- end process;
-
- u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => c_longword_w / c_data_w,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => xsel_data_sosi,
- src_out => local_sosi
- );
-
- ---------------------------------------------------------------
- -- ring_mux
- ---------------------------------------------------------------
- u_ring_mux : entity ring_lib.ring_mux
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_data_w => c_longword_w,
- g_channel_w => c_word_w,
- g_use_error => false,
- g_fifo_size => array_init(c_mux_fifo_size, 2)
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- remote_sosi => from_ri_sosi,
- local_sosi => local_sosi,
- mux_sosi => ring_mux_sosi,
- mux_siso => ring_mux_siso
- );
-
- to_ri_sosi <= ring_mux_sosi;
-
- -- fill fifo to remove gaps
- u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_fifo_fill => c_block_size_longwords,
- g_fifo_size => c_fifo_fill_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => ring_mux_siso,
- snk_in => ring_mux_sosi,
-
- src_in => dp_fifo_fill_siso,
- src_out => dp_fifo_fill_sosi
- );
-
- ---------------------------------------------------------------
- -- Repack 64b to 32b
+ -- Local and remote crosslets
---------------------------------------------------------------
- u_dp_repack_data_rx : entity dp_lib.dp_repack_data
+ u_sdp_crosslets_remote : entity work.sdp_crosslets_remote
generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 1,
- g_out_dat_w => c_data_w,
- g_out_nof_words => c_longword_w / c_data_w,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ g_P_sq => g_P_sq
)
port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_fill_sosi,
- snk_out => dp_fifo_fill_siso,
- src_out => rx_sosi
- );
-
- ---------------------------------------------------------------
- -- dp_demux
- ---------------------------------------------------------------
- u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_mode => 0,
- g_nof_output => g_P_sq,
- g_remove_channel_lo => false,
- g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => rx_sosi,
- src_out_arr => dispatch_invert_sosi_arr
- );
-
- dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
-
- ---------------------------------------------------------------
- -- dp_bsn_aligner_v2
- ---------------------------------------------------------------
- u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => g_P_sq,
- g_bsn_latency_max => 2,
- g_nof_aligners_max => 1, -- 1 for Access scheme 3.
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => true,
- g_rd_latency => 1, -- Required for st_xst
- -- for mms_dp_bsn_monitor_v2
- -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub,
- g_nof_input_bsn_monitors => g_P_sq,
- g_use_bsn_output_monitor => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
-
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
-
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
-
- -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi => crosslets_sosi,
- mm_copi => crosslets_copi,
- mm_cipo_arr => crosslets_cipo_arr
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ xsel_sosi => xsel_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+
+ crosslets_sosi => crosslets_sosi,
+ crosslets_copi => crosslets_copi,
+ crosslets_cipo_arr => crosslets_cipo_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
);
---------------------------------------------------------------
@@ -397,8 +238,8 @@ begin
---------------------------------------------------------------
-- Connect 2 mm_controllers to the common_mem_mux output
controller_copi_arr(0) <= ram_st_xsq_copi; -- MM access via QSYS MM bus
- ram_st_xsq_cipo <= controller_cipo_arr(0);
controller_copi_arr(1) <= ram_st_offload_copi; -- MM access by UDP offload
+ ram_st_xsq_cipo <= controller_cipo_arr(0);
ram_st_offload_cipo <= controller_cipo_arr(1);
u_mem_controller_mux : entity mm_lib.mm_master_mux
--
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