diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
index 60bb845baf348fbeefcb0704998ac2a64bd5a70c..7ef229d574c85c043e1f0528c95ab3febdd60889 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd
@@ -129,7 +129,7 @@ ARCHITECTURE str OF arts_unb1_sc1_bg_single_pol IS
-------------------------------------------------------------------------------
-- ctrl_unb1_board
-------------------------------------------------------------------------------
- CONSTANT c_ctrl_unb1_board_design_name : STRING := "NONE"; --FIXME
+ CONSTANT c_ctrl_unb1_board_design_name : STRING := "DESIGN_NAME"; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_date : NATURAL := 0; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_time : NATURAL := 0; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_svn : NATURAL := 0; --FIXME
@@ -149,22 +149,22 @@ ARCHITECTURE str OF arts_unb1_sc1_bg_single_pol IS
-- Pulse Per Second Handler
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL pio_system_info_mosi : t_mem_mosi; --FIXME C-app forces name to be pio_
+ SIGNAL pio_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- 1GbE
- SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi;
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi;
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC;
- SIGNAL eth1g_ram_mosi : t_mem_mosi;
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_irq : STD_LOGIC;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_ram_miso : t_mem_miso;
-- EPCS status/control
SIGNAL reg_epcs_mosi : t_mem_mosi;
SIGNAL reg_epcs_miso : t_mem_miso;
@@ -299,8 +299,8 @@ BEGIN
reg_wdi_miso => reg_wdi_miso,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
+ reg_unb_system_info_mosi => pio_system_info_mosi,
+ reg_unb_system_info_miso => pio_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
@@ -313,13 +313,14 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_reg_interrupt => eth1g_irq,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
@@ -338,7 +339,7 @@ BEGIN
sens_sc => sens_sc,
sens_sd => sens_sd,
-- . 1GbE Control Interface
- ETH_clk => ETH_clk,
+ ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
@@ -354,7 +355,7 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_irq => eth1g_irq,
pout_wdi => pout_wdi,
bf_unit_ram_ss_ss_wide_mosi => bf_unit_ram_ss_ss_wide_mosi,
bf_unit_ram_ss_ss_wide_miso => bf_unit_ram_ss_ss_wide_miso,
@@ -378,8 +379,8 @@ BEGIN
reg_remu_miso => reg_remu_miso,
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
+ pio_system_info_mosi => pio_system_info_mosi,
+ pio_system_info_miso => pio_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
reg_wdi_mosi => reg_wdi_mosi,
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
index 13b21548415ff4ae64c82f1e5ad2d6029cd15f24..4ae8e583dc32a451d9e5061580d6f8c6598693d3 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
@@ -6,6 +6,7 @@ synth_files =
../arts_unb1_sc1_offload.vhd
../generated/mm_master.vhd
../generated/arts_unb1_sc1_bg_single_pol.vhd
+synth_top_level_entity =
test_bench_files =
tb_arts_unb1_sc1_bg_single_pol.vhd
quartus_copy_files =
@@ -15,6 +16,6 @@ quartus_qsf_files =
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_qip_files =
- $HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bg_single_pol/synthesis/qsys_mm_master.qip
+ $HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
quartus_tcl_files =
arts_unb1_sc1_bg_single_pol_pins.tcl
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd b/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd
index ed864d7b3b35fbf45771f7cd73680e7d326671e9..e72a500f8f678a07088d911a52f0b6949074ed40 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/mm_master.vhd
@@ -40,7 +40,7 @@ ENTITY mm_master IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_irq : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_mosi : OUT t_mem_mosi;
bf_unit_ram_ss_ss_wide_miso : IN t_mem_miso;
@@ -64,8 +64,8 @@ ENTITY mm_master IS
reg_remu_miso : IN t_mem_miso;
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
+ pio_system_info_mosi : OUT t_mem_mosi;
+ pio_system_info_miso : IN t_mem_miso;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
reg_wdi_mosi : OUT t_mem_mosi;
@@ -77,124 +77,124 @@ ARCHITECTURE str OF mm_master IS
COMPONENT QSYS_MM_MASTER IS
PORT (
- clk_0 : IN STD_LOGIC;
- reset_n : IN STD_LOGIC;
+ clk_in_clk : IN STD_LOGIC;
+ reset_in_reset_n : IN STD_LOGIC;
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_irq : IN STD_LOGIC;
+ eth1g_mm_rst_export : OUT STD_LOGIC;
+ eth1g_irq_export : IN STD_LOGIC;
out_port_from_the_pio_wdi : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
- bf_unit_ram_ss_ss_wide_clk_export : OUT STD_LOGIC;
+-- bf_unit_ram_ss_ss_wide_clk_export : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_read_export : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- bf_unit_ram_ss_ss_wide_reset_export : OUT STD_LOGIC;
+-- bf_unit_ram_ss_ss_wide_reset_export : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_write_export : OUT STD_LOGIC;
bf_unit_ram_ss_ss_wide_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
bf_unit_ram_bf_weights_address_export : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
- bf_unit_ram_bf_weights_clk_export : OUT STD_LOGIC;
+-- bf_unit_ram_bf_weights_clk_export : OUT STD_LOGIC;
bf_unit_ram_bf_weights_read_export : OUT STD_LOGIC;
bf_unit_ram_bf_weights_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- bf_unit_ram_bf_weights_reset_export : OUT STD_LOGIC;
+-- bf_unit_ram_bf_weights_reset_export : OUT STD_LOGIC;
bf_unit_ram_bf_weights_write_export : OUT STD_LOGIC;
bf_unit_ram_bf_weights_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
bf_unit_ram_st_sst_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
- bf_unit_ram_st_sst_clk_export : OUT STD_LOGIC;
+-- bf_unit_ram_st_sst_clk_export : OUT STD_LOGIC;
bf_unit_ram_st_sst_read_export : OUT STD_LOGIC;
bf_unit_ram_st_sst_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- bf_unit_ram_st_sst_reset_export : OUT STD_LOGIC;
+-- bf_unit_ram_st_sst_reset_export : OUT STD_LOGIC;
bf_unit_ram_st_sst_write_export : OUT STD_LOGIC;
bf_unit_ram_st_sst_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
bf_unit_reg_st_sst_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
- bf_unit_reg_st_sst_clk_export : OUT STD_LOGIC;
+-- bf_unit_reg_st_sst_clk_export : OUT STD_LOGIC;
bf_unit_reg_st_sst_read_export : OUT STD_LOGIC;
bf_unit_reg_st_sst_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- bf_unit_reg_st_sst_reset_export : OUT STD_LOGIC;
+-- bf_unit_reg_st_sst_reset_export : OUT STD_LOGIC;
bf_unit_reg_st_sst_write_export : OUT STD_LOGIC;
bf_unit_reg_st_sst_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
eth1g_tse_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
- eth1g_tse_clk_export : OUT STD_LOGIC;
+-- eth1g_tse_clk_export : OUT STD_LOGIC;
eth1g_tse_read_export : OUT STD_LOGIC;
eth1g_tse_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- eth1g_tse_reset_export : OUT STD_LOGIC;
+-- eth1g_tse_reset_export : OUT STD_LOGIC;
eth1g_tse_write_export : OUT STD_LOGIC;
eth1g_tse_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- eth1g_tse_waitrequest : IN STD_LOGIC;
+ eth1g_tse_waitrequest_export : IN STD_LOGIC;
eth1g_reg_address_export : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
- eth1g_reg_clk_export : OUT STD_LOGIC;
+-- eth1g_reg_clk_export : OUT STD_LOGIC;
eth1g_reg_read_export : OUT STD_LOGIC;
eth1g_reg_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- eth1g_reg_reset_export : OUT STD_LOGIC;
+-- eth1g_reg_reset_export : OUT STD_LOGIC;
eth1g_reg_write_export : OUT STD_LOGIC;
eth1g_reg_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
eth1g_ram_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
- eth1g_ram_clk_export : OUT STD_LOGIC;
+-- eth1g_ram_clk_export : OUT STD_LOGIC;
eth1g_ram_read_export : OUT STD_LOGIC;
eth1g_ram_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- eth1g_ram_reset_export : OUT STD_LOGIC;
+-- eth1g_ram_reset_export : OUT STD_LOGIC;
eth1g_ram_write_export : OUT STD_LOGIC;
eth1g_ram_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_unb_sens_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
- reg_unb_sens_clk_export : OUT STD_LOGIC;
+-- reg_unb_sens_clk_export : OUT STD_LOGIC;
reg_unb_sens_read_export : OUT STD_LOGIC;
reg_unb_sens_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_unb_sens_reset_export : OUT STD_LOGIC;
+-- reg_unb_sens_reset_export : OUT STD_LOGIC;
reg_unb_sens_write_export : OUT STD_LOGIC;
reg_unb_sens_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_epcs_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
- reg_epcs_clk_export : OUT STD_LOGIC;
+-- reg_epcs_clk_export : OUT STD_LOGIC;
reg_epcs_read_export : OUT STD_LOGIC;
reg_epcs_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_epcs_reset_export : OUT STD_LOGIC;
+-- reg_epcs_reset_export : OUT STD_LOGIC;
reg_epcs_write_export : OUT STD_LOGIC;
reg_epcs_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_remu_address_export : OUT STD_LOGIC_VECTOR(3-1 DOWNTO 0);
- reg_remu_clk_export : OUT STD_LOGIC;
+-- reg_remu_clk_export : OUT STD_LOGIC;
reg_remu_read_export : OUT STD_LOGIC;
reg_remu_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_remu_reset_export : OUT STD_LOGIC;
+-- reg_remu_reset_export : OUT STD_LOGIC;
reg_remu_write_export : OUT STD_LOGIC;
reg_remu_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_ppsh_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
- reg_ppsh_clk_export : OUT STD_LOGIC;
+-- reg_ppsh_clk_export : OUT STD_LOGIC;
reg_ppsh_read_export : OUT STD_LOGIC;
reg_ppsh_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_ppsh_reset_export : OUT STD_LOGIC;
+-- reg_ppsh_reset_export : OUT STD_LOGIC;
reg_ppsh_write_export : OUT STD_LOGIC;
reg_ppsh_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_unb_system_info_address_export : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
- reg_unb_system_info_clk_export : OUT STD_LOGIC;
- reg_unb_system_info_read_export : OUT STD_LOGIC;
- reg_unb_system_info_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_unb_system_info_reset_export : OUT STD_LOGIC;
- reg_unb_system_info_write_export : OUT STD_LOGIC;
- reg_unb_system_info_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ pio_system_info_address_export : OUT STD_LOGIC_VECTOR(5-1 DOWNTO 0);
+-- pio_system_info_clk_export : OUT STD_LOGIC;
+ pio_system_info_read_export : OUT STD_LOGIC;
+ pio_system_info_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+-- pio_system_info_reset_export : OUT STD_LOGIC;
+ pio_system_info_write_export : OUT STD_LOGIC;
+ pio_system_info_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
rom_unb_system_info_address_export : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0);
- rom_unb_system_info_clk_export : OUT STD_LOGIC;
+-- rom_unb_system_info_clk_export : OUT STD_LOGIC;
rom_unb_system_info_read_export : OUT STD_LOGIC;
rom_unb_system_info_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- rom_unb_system_info_reset_export : OUT STD_LOGIC;
+-- rom_unb_system_info_reset_export : OUT STD_LOGIC;
rom_unb_system_info_write_export : OUT STD_LOGIC;
rom_unb_system_info_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_wdi_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
- reg_wdi_clk_export : OUT STD_LOGIC;
+-- reg_wdi_clk_export : OUT STD_LOGIC;
reg_wdi_read_export : OUT STD_LOGIC;
reg_wdi_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- reg_wdi_reset_export : OUT STD_LOGIC;
+-- reg_wdi_reset_export : OUT STD_LOGIC;
reg_wdi_write_export : OUT STD_LOGIC;
reg_wdi_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
);
@@ -207,124 +207,124 @@ BEGIN
gen_qsys_mm_master : IF g_sim = FALSE GENERATE
u_qsys_mm_master : qsys_mm_master
PORT MAP (
- clk_0 => mm_clk,
- reset_n => mm_rst_n,
+ clk_in_clk => mm_clk,
+ reset_in_reset_n => mm_rst_n,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_irq => eth1g_reg_interrupt,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_irq_export => eth1g_irq,
out_port_from_the_pio_wdi => pout_wdi,
bf_unit_ram_ss_ss_wide_address_export => bf_unit_ram_ss_ss_wide_mosi.address(4-1 DOWNTO 0),
- bf_unit_ram_ss_ss_wide_clk_export => OPEN,
+-- bf_unit_ram_ss_ss_wide_clk_export => OPEN,
bf_unit_ram_ss_ss_wide_read_export => bf_unit_ram_ss_ss_wide_mosi.rd,
bf_unit_ram_ss_ss_wide_readdata_export => bf_unit_ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
- bf_unit_ram_ss_ss_wide_reset_export => OPEN,
+-- bf_unit_ram_ss_ss_wide_reset_export => OPEN,
bf_unit_ram_ss_ss_wide_write_export => bf_unit_ram_ss_ss_wide_mosi.wr,
bf_unit_ram_ss_ss_wide_writedata_export => bf_unit_ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
bf_unit_ram_bf_weights_address_export => bf_unit_ram_bf_weights_mosi.address(5-1 DOWNTO 0),
- bf_unit_ram_bf_weights_clk_export => OPEN,
+-- bf_unit_ram_bf_weights_clk_export => OPEN,
bf_unit_ram_bf_weights_read_export => bf_unit_ram_bf_weights_mosi.rd,
bf_unit_ram_bf_weights_readdata_export => bf_unit_ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
- bf_unit_ram_bf_weights_reset_export => OPEN,
+-- bf_unit_ram_bf_weights_reset_export => OPEN,
bf_unit_ram_bf_weights_write_export => bf_unit_ram_bf_weights_mosi.wr,
bf_unit_ram_bf_weights_writedata_export => bf_unit_ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
bf_unit_ram_st_sst_address_export => bf_unit_ram_st_sst_mosi.address(3-1 DOWNTO 0),
- bf_unit_ram_st_sst_clk_export => OPEN,
+-- bf_unit_ram_st_sst_clk_export => OPEN,
bf_unit_ram_st_sst_read_export => bf_unit_ram_st_sst_mosi.rd,
bf_unit_ram_st_sst_readdata_export => bf_unit_ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
- bf_unit_ram_st_sst_reset_export => OPEN,
+-- bf_unit_ram_st_sst_reset_export => OPEN,
bf_unit_ram_st_sst_write_export => bf_unit_ram_st_sst_mosi.wr,
bf_unit_ram_st_sst_writedata_export => bf_unit_ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
bf_unit_reg_st_sst_address_export => bf_unit_reg_st_sst_mosi.address(6-1 DOWNTO 0),
- bf_unit_reg_st_sst_clk_export => OPEN,
+-- bf_unit_reg_st_sst_clk_export => OPEN,
bf_unit_reg_st_sst_read_export => bf_unit_reg_st_sst_mosi.rd,
bf_unit_reg_st_sst_readdata_export => bf_unit_reg_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
- bf_unit_reg_st_sst_reset_export => OPEN,
+-- bf_unit_reg_st_sst_reset_export => OPEN,
bf_unit_reg_st_sst_write_export => bf_unit_reg_st_sst_mosi.wr,
bf_unit_reg_st_sst_writedata_export => bf_unit_reg_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_tse_address_export => eth1g_tse_mosi.address(10-1 DOWNTO 0),
- eth1g_tse_clk_export => OPEN,
+-- eth1g_tse_clk_export => OPEN,
eth1g_tse_read_export => eth1g_tse_mosi.rd,
eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- eth1g_tse_reset_export => OPEN,
+-- eth1g_tse_reset_export => OPEN,
eth1g_tse_write_export => eth1g_tse_mosi.wr,
eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- eth1g_tse_waitrequest => eth1g_tse_miso.waitrequest,
+ eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
eth1g_reg_address_export => eth1g_reg_mosi.address(4-1 DOWNTO 0),
- eth1g_reg_clk_export => OPEN,
+-- eth1g_reg_clk_export => OPEN,
eth1g_reg_read_export => eth1g_reg_mosi.rd,
eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- eth1g_reg_reset_export => OPEN,
+-- eth1g_reg_reset_export => OPEN,
eth1g_reg_write_export => eth1g_reg_mosi.wr,
eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_ram_address_export => eth1g_ram_mosi.address(10-1 DOWNTO 0),
- eth1g_ram_clk_export => OPEN,
+-- eth1g_ram_clk_export => OPEN,
eth1g_ram_read_export => eth1g_ram_mosi.rd,
eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- eth1g_ram_reset_export => OPEN,
+-- eth1g_ram_reset_export => OPEN,
eth1g_ram_write_export => eth1g_ram_mosi.wr,
eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_address_export => reg_unb_sens_mosi.address(3-1 DOWNTO 0),
- reg_unb_sens_clk_export => OPEN,
+-- reg_unb_sens_clk_export => OPEN,
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_unb_sens_reset_export => OPEN,
+-- reg_unb_sens_reset_export => OPEN,
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_address_export => reg_epcs_mosi.address(3-1 DOWNTO 0),
- reg_epcs_clk_export => OPEN,
+-- reg_epcs_clk_export => OPEN,
reg_epcs_read_export => reg_epcs_mosi.rd,
reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_epcs_reset_export => OPEN,
+-- reg_epcs_reset_export => OPEN,
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_address_export => reg_remu_mosi.address(3-1 DOWNTO 0),
- reg_remu_clk_export => OPEN,
+-- reg_remu_clk_export => OPEN,
reg_remu_read_export => reg_remu_mosi.rd,
reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_remu_reset_export => OPEN,
+-- reg_remu_reset_export => OPEN,
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_ppsh_address_export => reg_ppsh_mosi.address(1-1 DOWNTO 0),
- reg_ppsh_clk_export => OPEN,
+-- reg_ppsh_clk_export => OPEN,
reg_ppsh_read_export => reg_ppsh_mosi.rd,
reg_ppsh_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_ppsh_reset_export => OPEN,
+-- reg_ppsh_reset_export => OPEN,
reg_ppsh_write_export => reg_ppsh_mosi.wr,
reg_ppsh_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_unb_system_info_address_export => reg_unb_system_info_mosi.address(5-1 DOWNTO 0),
- reg_unb_system_info_clk_export => OPEN,
- reg_unb_system_info_read_export => reg_unb_system_info_mosi.rd,
- reg_unb_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_unb_system_info_reset_export => OPEN,
- reg_unb_system_info_write_export => reg_unb_system_info_mosi.wr,
- reg_unb_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => pio_system_info_mosi.address(5-1 DOWNTO 0),
+-- pio_system_info_clk_export => OPEN,
+ pio_system_info_read_export => pio_system_info_mosi.rd,
+ pio_system_info_readdata_export => pio_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+-- pio_system_info_reset_export => OPEN,
+ pio_system_info_write_export => pio_system_info_mosi.wr,
+ pio_system_info_writedata_export => pio_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_unb_system_info_address_export => rom_unb_system_info_mosi.address(10-1 DOWNTO 0),
- rom_unb_system_info_clk_export => OPEN,
+-- rom_unb_system_info_clk_export => OPEN,
rom_unb_system_info_read_export => rom_unb_system_info_mosi.rd,
rom_unb_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- rom_unb_system_info_reset_export => OPEN,
+-- rom_unb_system_info_reset_export => OPEN,
rom_unb_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_unb_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_wdi_address_export => reg_wdi_mosi.address(1-1 DOWNTO 0),
- reg_wdi_clk_export => OPEN,
+-- reg_wdi_clk_export => OPEN,
reg_wdi_read_export => reg_wdi_mosi.rd,
reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_wdi_reset_export => OPEN,
+-- reg_wdi_reset_export => OPEN,
reg_wdi_write_export => reg_wdi_mosi.wr,
reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys b/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
index e304e1cf68c4d3ce0e11d7ccf95364d32700f5c3..109b792978bc386affdbe014a76751af81173282 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/qsys_mm_master.qsys
@@ -29,7 +29,7 @@
}
datum sopceditor_expanded
{
- value = "1";
+ value = "0";
type = "boolean";
}
}
@@ -37,7 +37,7 @@
{
datum _sortIndex
{
- value = "11";
+ value = "6";
type = "int";
}
datum sopceditor_expanded
@@ -50,7 +50,7 @@
{
datum _sortIndex
{
- value = "2";
+ value = "1";
type = "int";
}
datum sopceditor_expanded
@@ -71,7 +71,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "3";
type = "int";
}
datum megawizard_uipreferences
@@ -85,61 +85,6 @@
type = "boolean";
}
}
- element reg_unb_sens.mem
- {
- datum baseAddress
- {
- value = "224";
- type = "long";
- }
- }
- element pio_system_info.mem
- {
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
- datum baseAddress
- {
- value = "0";
- type = "long";
- }
- }
- element pio_pps.mem
- {
- datum baseAddress
- {
- value = "280";
- type = "long";
- }
- }
- element rom_system_info.mem
- {
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
- datum baseAddress
- {
- value = "4096";
- type = "long";
- }
- }
- element reg_wdi.mem
- {
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
- datum baseAddress
- {
- value = "12288";
- type = "long";
- }
- }
element avs_eth_0.mms_ram
{
datum baseAddress
@@ -168,7 +113,7 @@
{
datum _sortIndex
{
- value = "3";
+ value = "2";
type = "int";
}
datum megawizard_uipreferences
@@ -182,37 +127,11 @@
type = "boolean";
}
}
- element pio_pps
- {
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
- element pio_system_info
- {
- datum _sortIndex
- {
- value = "1";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
element pio_wdi
{
datum _sortIndex
{
- value = "5";
+ value = "4";
type = "int";
}
datum megawizard_uipreferences
@@ -234,45 +153,6 @@
type = "String";
}
}
- element reg_unb_sens
- {
- datum _sortIndex
- {
- value = "7";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
- element reg_wdi
- {
- datum _sortIndex
- {
- value = "9";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
- element rom_system_info
- {
- datum _sortIndex
- {
- value = "10";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
element onchip_memory2_0.s1
{
datum _lockedAddress
@@ -286,14 +166,6 @@
type = "long";
}
}
- element timer_0.s1
- {
- datum baseAddress
- {
- value = "192";
- type = "long";
- }
- }
element pio_wdi.s1
{
datum baseAddress
@@ -302,19 +174,19 @@
type = "long";
}
}
- element reg_wdi.system_reset
+ element timer_0.s1
{
- datum _tags
+ datum baseAddress
{
- value = "";
- type = "String";
+ value = "192";
+ type = "long";
}
}
element timer_0
{
datum _sortIndex
{
- value = "6";
+ value = "5";
type = "int";
}
datum sopceditor_expanded
@@ -323,14 +195,6 @@
type = "boolean";
}
}
- element reg_wdi.writedata
- {
- datum _tags
- {
- value = "";
- type = "String";
- }
- }
}
element bf_unit_ram_ss_ss_wide.mem
@@ -409,63 +273,6 @@
}
}
- element eth1g_tse.mem
- {
- datum baseAddress
- {
- value = 24576;
- type = "long";
- }
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
-
- element eth1g_reg.mem
- {
- datum baseAddress
- {
- value = 28672;
- type = "long";
- }
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
-
- element eth1g_ram.mem
- {
- datum baseAddress
- {
- value = 32768;
- type = "long";
- }
- datum _sortIndex
- {
- value = "8";
- type = "int";
- }
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
- }
-
element reg_unb_sens.mem
{
datum baseAddress
@@ -542,11 +349,11 @@
}
}
- element reg_unb_system_info.mem
+ element pio_system_info.mem
{
datum baseAddress
{
- value = 36992;
+ value = 0;
type = "long";
}
datum _sortIndex
@@ -565,7 +372,7 @@
{
datum baseAddress
{
- value = 40960;
+ value = 4096;
type = "long";
}
datum _sortIndex
@@ -584,7 +391,7 @@
{
datum baseAddress
{
- value = 45056;
+ value = 12288;
type = "long";
}
datum _sortIndex
@@ -613,7 +420,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1447406179912" />
+ <parameter name="timeStamp" value="1447482363453" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
@@ -711,165 +518,6 @@
type="conduit"
dir="end" />
<interface name="eth1g_irq" internal="avs_eth_0.irq" type="conduit" dir="end" />
- <interface
- name="reg_unb_sens_reset"
- internal="reg_unb_sens.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_clk"
- internal="reg_unb_sens.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_address"
- internal="reg_unb_sens.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_write"
- internal="reg_unb_sens.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_writedata"
- internal="reg_unb_sens.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_read"
- internal="reg_unb_sens.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_unb_sens_readdata"
- internal="reg_unb_sens.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_reset"
- internal="pio_system_info.reset"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_clk"
- internal="pio_system_info.clk"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_address"
- internal="pio_system_info.address"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_write"
- internal="pio_system_info.write"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_writedata"
- internal="pio_system_info.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_read"
- internal="pio_system_info.read"
- type="conduit"
- dir="end" />
- <interface
- name="pio_system_info_readdata"
- internal="pio_system_info.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="pio_pps_reset"
- internal="pio_pps.reset"
- type="conduit"
- dir="end" />
- <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
- <interface
- name="pio_pps_address"
- internal="pio_pps.address"
- type="conduit"
- dir="end" />
- <interface
- name="pio_pps_write"
- internal="pio_pps.write"
- type="conduit"
- dir="end" />
- <interface
- name="pio_pps_writedata"
- internal="pio_pps.writedata"
- type="conduit"
- dir="end" />
- <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
- <interface
- name="pio_pps_readdata"
- internal="pio_pps.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_wdi_reset"
- internal="reg_wdi.reset"
- type="conduit"
- dir="end" />
- <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
- <interface
- name="reg_wdi_address"
- internal="reg_wdi.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_wdi_write"
- internal="reg_wdi.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_wdi_writedata"
- internal="reg_wdi.writedata"
- type="conduit"
- dir="end" />
- <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
- <interface
- name="reg_wdi_readdata"
- internal="reg_wdi.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_reset"
- internal="rom_system_info.reset"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_clk"
- internal="rom_system_info.clk"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_address"
- internal="rom_system_info.address"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_write"
- internal="rom_system_info.write"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_writedata"
- internal="rom_system_info.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_read"
- internal="rom_system_info.read"
- type="conduit"
- dir="end" />
- <interface
- name="rom_system_info_readdata"
- internal="rom_system_info.readdata"
- type="conduit"
- dir="end" />
<interface name="clk_in" internal="clk_input.clk_in" type="clock" dir="end" />
<interface
name="reset_in"
@@ -951,181 +599,73 @@
<interface
name="bf_unit_ram_st_sst_reset"
- internal="bf_unit_ram_st_sst.reset"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_clk"
- internal="bf_unit_ram_st_sst.clk"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_address"
- internal="bf_unit_ram_st_sst.address"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_write"
- internal="bf_unit_ram_st_sst.write"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_writedata"
- internal="bf_unit_ram_st_sst.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_read"
- internal="bf_unit_ram_st_sst.read"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_ram_st_sst_readdata"
- internal="bf_unit_ram_st_sst.readdata"
- type="conduit"
- dir="end" />
-
- <interface
- name="bf_unit_reg_st_sst_reset"
- internal="bf_unit_reg_st_sst.reset"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_clk"
- internal="bf_unit_reg_st_sst.clk"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_address"
- internal="bf_unit_reg_st_sst.address"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_write"
- internal="bf_unit_reg_st_sst.write"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_writedata"
- internal="bf_unit_reg_st_sst.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_read"
- internal="bf_unit_reg_st_sst.read"
- type="conduit"
- dir="end" />
- <interface
- name="bf_unit_reg_st_sst_readdata"
- internal="bf_unit_reg_st_sst.readdata"
- type="conduit"
- dir="end" />
-
- <interface
- name="eth1g_tse_reset"
- internal="eth1g_tse.reset"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_clk"
- internal="eth1g_tse.clk"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_address"
- internal="eth1g_tse.address"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_write"
- internal="eth1g_tse.write"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_writedata"
- internal="eth1g_tse.writedata"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_read"
- internal="eth1g_tse.read"
- type="conduit"
- dir="end" />
- <interface
- name="eth1g_tse_readdata"
- internal="eth1g_tse.readdata"
- type="conduit"
- dir="end" />
-
- <interface
- name="eth1g_reg_reset"
- internal="eth1g_reg.reset"
+ internal="bf_unit_ram_st_sst.reset"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_clk"
- internal="eth1g_reg.clk"
+ name="bf_unit_ram_st_sst_clk"
+ internal="bf_unit_ram_st_sst.clk"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_address"
- internal="eth1g_reg.address"
+ name="bf_unit_ram_st_sst_address"
+ internal="bf_unit_ram_st_sst.address"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_write"
- internal="eth1g_reg.write"
+ name="bf_unit_ram_st_sst_write"
+ internal="bf_unit_ram_st_sst.write"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_writedata"
- internal="eth1g_reg.writedata"
+ name="bf_unit_ram_st_sst_writedata"
+ internal="bf_unit_ram_st_sst.writedata"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_read"
- internal="eth1g_reg.read"
+ name="bf_unit_ram_st_sst_read"
+ internal="bf_unit_ram_st_sst.read"
type="conduit"
dir="end" />
<interface
- name="eth1g_reg_readdata"
- internal="eth1g_reg.readdata"
+ name="bf_unit_ram_st_sst_readdata"
+ internal="bf_unit_ram_st_sst.readdata"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_reset"
- internal="eth1g_ram.reset"
+ name="bf_unit_reg_st_sst_reset"
+ internal="bf_unit_reg_st_sst.reset"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_clk"
- internal="eth1g_ram.clk"
+ name="bf_unit_reg_st_sst_clk"
+ internal="bf_unit_reg_st_sst.clk"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_address"
- internal="eth1g_ram.address"
+ name="bf_unit_reg_st_sst_address"
+ internal="bf_unit_reg_st_sst.address"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_write"
- internal="eth1g_ram.write"
+ name="bf_unit_reg_st_sst_write"
+ internal="bf_unit_reg_st_sst.write"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_writedata"
- internal="eth1g_ram.writedata"
+ name="bf_unit_reg_st_sst_writedata"
+ internal="bf_unit_reg_st_sst.writedata"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_read"
- internal="eth1g_ram.read"
+ name="bf_unit_reg_st_sst_read"
+ internal="bf_unit_reg_st_sst.read"
type="conduit"
dir="end" />
<interface
- name="eth1g_ram_readdata"
- internal="eth1g_ram.readdata"
+ name="bf_unit_reg_st_sst_readdata"
+ internal="bf_unit_reg_st_sst.readdata"
type="conduit"
dir="end" />
@@ -1274,38 +814,38 @@
dir="end" />
<interface
- name="reg_unb_system_info_reset"
- internal="reg_unb_system_info.reset"
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_clk"
- internal="reg_unb_system_info.clk"
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_address"
- internal="reg_unb_system_info.address"
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_write"
- internal="reg_unb_system_info.write"
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_writedata"
- internal="reg_unb_system_info.writedata"
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_read"
- internal="reg_unb_system_info.read"
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
type="conduit"
dir="end" />
<interface
- name="reg_unb_system_info_readdata"
- internal="reg_unb_system_info.readdata"
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
type="conduit"
dir="end" />
@@ -1539,7 +1079,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='pio_wdi.s1' start='0x100' end='0x110' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x110' end='0x118' /><slave name='pio_pps.mem' start='0x118' end='0x120' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='bf_unit_ram_ss_ss_wide.mem' start='20480' end='20482' /><slave name='bf_unit_ram_bf_weights.mem' start='20608' end='20611' /><slave name='bf_unit_ram_st_sst.mem' start='20736' end='20738' /><slave name='bf_unit_reg_st_sst.mem' start='20992' end='20995' /><slave name='eth1g_tse.mem' start='24576' end='24580' /><slave name='eth1g_reg.mem' start='28672' end='28674' /><slave name='eth1g_ram.mem' start='32768' end='32772' /><slave name='reg_unb_sens.mem' start='36864' end='36866' /><slave name='reg_epcs.mem' start='36896' end='36898' /><slave name='reg_remu.mem' start='36928' end='36930' /><slave name='reg_ppsh.mem' start='36960' end='36960' /><slave name='reg_unb_system_info.mem' start='36992' end='36995' /><slave name='rom_unb_system_info.mem' start='40960' end='40964' /><slave name='reg_wdi.mem' start='45056' end='45056' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='pio_wdi.s1' start='0x100' end='0x110' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x110' end='0x118' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='bf_unit_ram_ss_ss_wide.mem' start='20480' end='20482' /><slave name='bf_unit_ram_bf_weights.mem' start='20608' end='20611' /><slave name='bf_unit_ram_st_sst.mem' start='20736' end='20738' /><slave name='bf_unit_reg_st_sst.mem' start='20992' end='20995' /><slave name='reg_unb_sens.mem' start='36864' end='36866' /><slave name='reg_epcs.mem' start='36896' end='36898' /><slave name='reg_remu.mem' start='36928' end='36930' /><slave name='reg_ppsh.mem' start='36960' end='36960' /><slave name='pio_system_info.mem' start='0' end='3' /><slave name='rom_unb_system_info.mem' start='4096' end='4100' /><slave name='reg_wdi.mem' start='12288' end='12288' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
@@ -1558,31 +1098,6 @@ q]]></parameter>
<module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
<parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
- <parameter name="g_adr_w" value="3" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
- <parameter name="g_adr_w" value="5" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
- <parameter name="g_adr_w" value="1" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
- <parameter name="g_adr_w" value="10" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
<module kind="clock_source" version="11.1" enabled="1" name="clk_input">
<parameter name="clockFrequency" value="25000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -1618,27 +1133,6 @@ q]]></parameter>
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_tse">
- <parameter name="g_adr_w" value="10" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
-
-
- <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_reg">
- <parameter name="g_adr_w" value="4" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
-
-
- <module kind="avs_common_mm" version="1.0" enabled="1" name="eth1g_ram">
- <parameter name="g_adr_w" value="10" />
- <parameter name="g_dat_w" value="32" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
- </module>
-
-
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
@@ -1667,7 +1161,7 @@ q]]></parameter>
</module>
- <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_system_info">
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
@@ -1803,71 +1297,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" />
</connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_unb_sens.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_unb_sens.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00e0" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="pio_system_info.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="pio_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="pio_pps.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="pio_pps.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0118" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="reg_wdi.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="reg_wdi.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3000" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="rom_system_info.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="rom_system_info.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x1000" />
- </connection>
<connection
kind="interrupt"
version="11.1"
@@ -1880,26 +1309,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="avs_eth_0.mm_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="reg_unb_sens.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="pio_pps.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="reg_wdi.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="rom_system_info.system_reset" />
<connection
kind="reset"
version="11.1"
@@ -1925,36 +1334,11 @@ q]]></parameter>
version="11.1"
start="clk_input.clk_reset"
end="cpu_0.reset_n" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="pio_system_info.system_reset" />
<connection
kind="reset"
version="11.1"
start="clk_input.clk_reset"
end="avs_eth_0.mm_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="rom_system_info.system" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="reg_wdi.system" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="pio_pps.system" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="reg_unb_sens.system" />
<connection kind="clock" version="11.1" start="clk_input.clk" end="timer_0.clk" />
<connection kind="clock" version="11.1" start="clk_input.clk" end="pio_wdi.clk" />
<connection
@@ -1968,11 +1352,6 @@ q]]></parameter>
start="clk_input.clk"
end="onchip_memory2_0.clk1" />
<connection kind="clock" version="11.1" start="clk_input.clk" end="cpu_0.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="pio_system_info.system" />
<connection kind="clock" version="11.1" start="clk_input.clk" end="avs_eth_0.mm" />
<connection
@@ -2071,78 +1450,6 @@ q]]></parameter>
start="clk_input.clk"
end="bf_unit_reg_st_sst.system" />
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="eth1g_tse.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="eth1g_tse.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="24576" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="eth1g_tse.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="eth1g_tse.system" />
-
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="eth1g_reg.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="eth1g_reg.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="28672" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="eth1g_reg.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="eth1g_reg.system" />
-
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="eth1g_ram.system_reset" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="eth1g_ram.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="32768" />
- </connection>
- <connection
- kind="reset"
- version="11.1"
- start="clk_input.clk_reset"
- end="eth1g_ram.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_input.clk"
- end="eth1g_ram.system" />
-
<connection
kind="reset"
version="11.1"
@@ -2243,25 +1550,25 @@ q]]></parameter>
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
- end="reg_unb_system_info.system_reset" />
+ end="pio_system_info.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
- end="reg_unb_system_info.mem">
+ end="pio_system_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="36992" />
+ <parameter name="baseAddress" value="0" />
</connection>
<connection
kind="reset"
version="11.1"
start="clk_input.clk_reset"
- end="reg_unb_system_info.system_reset" />
+ end="pio_system_info.system_reset" />
<connection
kind="clock"
version="11.1"
start="clk_input.clk"
- end="reg_unb_system_info.system" />
+ end="pio_system_info.system" />
<connection
kind="reset"
@@ -2274,7 +1581,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="rom_unb_system_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="40960" />
+ <parameter name="baseAddress" value="4096" />
</connection>
<connection
kind="reset"
@@ -2298,7 +1605,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_wdi.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="45056" />
+ <parameter name="baseAddress" value="12288" />
</connection>
<connection
kind="reset"
diff --git a/tools/oneclick/components/component.py b/tools/oneclick/components/component.py
index 37acdd2ba3f26037e1f32924a721f8ab35f95498..7f1a7eb6fe1e497d353afed8326769a8c9a327a1 100644
--- a/tools/oneclick/components/component.py
+++ b/tools/oneclick/components/component.py
@@ -465,6 +465,9 @@ class Component(mp.Process):
if component.vhdl_file_name != None:
hdllib_file.write(' ../%s\n' %component.vhdl_file_name)
hdllib_file.write(' ../%s\n' %self.vhdl_file_name)
+
+ hdllib_file.write('synth_top_level_entity =\n')
+
hdllib_file.write('test_bench_files =\n')
hdllib_file.write(' tb_%s.vhd\n' %self.name)
@@ -478,7 +481,7 @@ class Component(mp.Process):
hdllib_file.write(' $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc\n')
hdllib_file.write('quartus_qip_files =\n')
- hdllib_file.write(' $HDL_BUILD_DIR/unb1/quartus/%s/synthesis/qsys_mm_master.qip\n' %self.name)
+ hdllib_file.write(' $HDL_BUILD_DIR/unb1/quartus/%s/qsys_mm_master/synthesis/qsys_mm_master.qip\n' %self.name)
hdllib_file.write('quartus_tcl_files =\n')
hdllib_file.write(' %s_pins.tcl\n' %self.name)
diff --git a/tools/oneclick/components/ctrl_unb1_board.py b/tools/oneclick/components/ctrl_unb1_board.py
index fea59af5579bfcf532571d09797d390aa03a93c4..0844bd5d20dff2dc3d4406621213c07902ed2c92 100644
--- a/tools/oneclick/components/ctrl_unb1_board.py
+++ b/tools/oneclick/components/ctrl_unb1_board.py
@@ -44,8 +44,8 @@ VHDL_INST = """ u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
reg_wdi_miso => reg_wdi_miso,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
+ reg_unb_system_info_mosi => pio_system_info_mosi,
+ reg_unb_system_info_miso => pio_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
@@ -58,13 +58,14 @@ VHDL_INST = """ u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_reg_interrupt => eth1g_irq,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
@@ -83,7 +84,7 @@ VHDL_INST = """ u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
sens_sc => sens_sc,
sens_sd => sens_sd,
-- . 1GbE Control Interface
- ETH_clk => ETH_clk,
+ ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
@@ -105,22 +106,22 @@ VHDL_SIGNALS = """
-- Pulse Per Second Handler
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL pio_system_info_mosi : t_mem_mosi; --FIXME C-app forces name to be pio_
+ SIGNAL pio_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- 1GbE
- SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi;
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi;
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC;
- SIGNAL eth1g_ram_mosi : t_mem_mosi;
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_irq : STD_LOGIC;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_ram_miso : t_mem_miso;
-- EPCS status/control
SIGNAL reg_epcs_mosi : t_mem_mosi;
SIGNAL reg_epcs_miso : t_mem_miso;
@@ -130,7 +131,7 @@ VHDL_SIGNALS = """
"""
-VHDL_CONSTANTS = """ CONSTANT c_ctrl_unb1_board_design_name : STRING := "NONE"; --FIXME
+VHDL_CONSTANTS = """ CONSTANT c_ctrl_unb1_board_design_name : STRING := "DESIGN_NAME"; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_date : NATURAL := 0; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_time : NATURAL := 0; --FIXME
CONSTANT c_ctrl_unb1_board_stamp_svn : NATURAL := 0; --FIXME
@@ -178,9 +179,11 @@ class ctrl_unb1_board(Component):
('reg_epcs', 3, 1, None), \
('reg_remu', 3, 1, None), \
('reg_ppsh', 1, 1, None), \
- ('reg_unb_system_info', 5, 1, 0x0), \
+ ('pio_system_info', 5, 1, 0x0), \
('rom_unb_system_info', 10, 1, 0x1000), \
- ('reg_wdi', 1, 1, None)]
+ ('reg_wdi', 1, 1, 0x3000)] #FIXME Bus name mismatches for pio_system_info
+ #(should be reg_unb_system_info) and avs_eth0_*
+ #(should be eth1g_*). These names are forced by unb_common.c and used base QSYS.
# self.set_output('snk_in_arr', (nof_streams, data_width)) # UDP offload
# self.set_output('src_out_arr', (data_width)) # UDP offload
diff --git a/tools/oneclick/components/mm_master.py b/tools/oneclick/components/mm_master.py
index 4dc2844ef4ac9ca38cf88b5e53af625f5e0477dc..0b39626f2eaaf65aa51257297d84acebf80da49a 100644
--- a/tools/oneclick/components/mm_master.py
+++ b/tools/oneclick/components/mm_master.py
@@ -10,7 +10,7 @@ VHDL_INST_TOP = """ u_mm_master : ENTITY work.mm_master
mm_rst => mm_rst,
mm_clk => mm_clk,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_irq => eth1g_irq,
pout_wdi => pout_wdi"""
VHDL_INST_BOTTOM = """
@@ -28,7 +28,7 @@ ENTITY DESIGN_NAME IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_irq : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC"""
VHDL_ENTITY_BOTTOM = """
@@ -43,18 +43,18 @@ QSYS_INST_BEGIN = """
gen_qsys_mm_master : IF g_sim = FALSE GENERATE
u_qsys_mm_master : qsys_mm_master
PORT MAP (
- clk_0 => mm_clk,
- reset_n => mm_rst_n,
+ clk_in_clk => mm_clk,
+ reset_in_reset_n => mm_rst_n,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_irq => eth1g_reg_interrupt,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_irq_export => eth1g_irq,
out_port_from_the_pio_wdi => pout_wdi"""
QSYS_EXPORT_PORT_MAP = """ $name_address_export => $name_mosi.address($addr_width-1 DOWNTO 0),
- $name_clk_export => OPEN,
+-- $name_clk_export => OPEN,
$name_read_export => $name_mosi.rd,
$name_readdata_export => $name_miso.rddata(c_word_w-1 DOWNTO 0),
- $name_reset_export => OPEN,
+-- $name_reset_export => OPEN,
$name_write_export => $name_mosi.wr,
$name_writedata_export => $name_mosi.wrdata(c_word_w-1 DOWNTO 0)"""
@@ -67,18 +67,18 @@ QSYS_INST_END = """
QSYS_COMPONENT_DECLARATION_BEGIN = """
COMPONENT QSYS_MM_MASTER IS
PORT (
- clk_0 : IN STD_LOGIC;
- reset_n : IN STD_LOGIC;
+ clk_in_clk : IN STD_LOGIC;
+ reset_in_reset_n : IN STD_LOGIC;
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_irq : IN STD_LOGIC;
+ eth1g_mm_rst_export : OUT STD_LOGIC;
+ eth1g_irq_export : IN STD_LOGIC;
out_port_from_the_pio_wdi : OUT STD_LOGIC"""
QSYS_COMPONENT_DECLARATION_PORT_MAP = """ $name_address_export : OUT STD_LOGIC_VECTOR($addr_width-1 DOWNTO 0);
- $name_clk_export : OUT STD_LOGIC;
+-- $name_clk_export : OUT STD_LOGIC;
$name_read_export : OUT STD_LOGIC;
$name_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- $name_reset_export : OUT STD_LOGIC;
+-- $name_reset_export : OUT STD_LOGIC;
$name_write_export : OUT STD_LOGIC;
$name_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)"""
@@ -100,28 +100,40 @@ class mm_master(Component):
# Create a list of peripherals to pass to QSYS generator
peripheral_list = []
- base_address = 0x5000
+ auto_base_address = 0x5000
for slave_component in slave_components:
for mm_reg in slave_component.mm_regs:
name = mm_reg[0]
word_addr_w = mm_reg[1]
- byte_span = (2**word_addr_w)*4 # *4 because QSYS uses byte addressing
+ fixed_base_address = mm_reg[3]
+ base_address = fixed_base_address
+
+ if fixed_base_address==None:
+ byte_span = (2**word_addr_w)*4 # *4 because QSYS uses byte addressing
+
+ # QSYS wants the base address to be a multiple of the byte span,
+ # fine tune the rough base address to exact, correct address here:
+ auto_base_address = ceil_div(auto_base_address, byte_span) * byte_span
+
+ # Append this peripheral at this base address to the list to be generated
+ base_address = auto_base_address
+
+ # Prepare the next base_address (*roughly*)
+ auto_base_address = auto_base_address+byte_span
- # QSYS wants the base address to be a multiple of the byte span,
- # fine tune the rough base address to exact, correct address here:
- base_address = ceil_div(base_address, byte_span) * byte_span
-
- # Append this peripheral at this base address to the list to be generated
peripheral_list.append( (name, base_address, word_addr_w) )
- # Prepare the next base_address (*roughly*)
- base_address = base_address+byte_span
# Use the base QSYS file
input_qsys = os.environ['RADIOHDL']+'/tools/oneclick/base/qsys_input.qsys'
# Create the QSYS file
- generate_qsys(input_qsys, peripheral_list, 'generated/qsys_mm_master.qsys')
+ # FIXME - Workaround: we need eth1g buses everywhere but in the QSYS itself - dedicated component is already there.
+ peripheral_list_minus_eth1g = []
+ for periph in peripheral_list:
+ if 'eth1g' not in periph[0]:
+ peripheral_list_minus_eth1g.append(periph)
+ generate_qsys(input_qsys, peripheral_list_minus_eth1g, 'generated/qsys_mm_master.qsys')
# Create MMM wrapper for the generated QSYS
# . No Python function to call, so we need to execute the mmm_gen.py script on the command line?
@@ -186,7 +198,16 @@ class mm_master(Component):
rl=mm_reg[2]
qsys_comp_decl+=';\n\n'+QSYS_COMPONENT_DECLARATION_PORT_MAP.replace('$name', name).replace('$addr_width', str(addr_width))
if rl==0:
- qsys_comp_decl+=';\n\n %s_waitrequest : IN STD_LOGIC' %(name)
+ qsys_comp_decl+=';\n\n %s_waitrequest_export : IN STD_LOGIC' %(name)
+
+ #FIXME: workaround; eth1g MM regs do not export clk, reset like all others MM regs.
+# qsys_comp_decl.replace('eth1g_ram_clk_export : OUT STD_LOGIC;\n', '')
+# qsys_comp_decl.replace('eth1g_reg_clk_export : OUT STD_LOGIC;\n', '')
+# qsys_comp_decl.replace('eth1g_tse_clk_export : OUT STD_LOGIC;\n', '')
+# qsys_comp_decl.replace('eth1g_ram_reset_export : OUT STD_LOGIC\n', '')
+# qsys_comp_decl.replace('eth1g_reg_reset_export : OUT STD_LOGIC\n', '')
+# qsys_comp_decl.replace('eth1g_tse_reset_export : OUT STD_LOGIC\n', '')
+
target_vhdl_file.write(qsys_comp_decl)
target_vhdl_file.write(QSYS_COMPONENT_DECLARATION_END)
@@ -212,7 +233,7 @@ class mm_master(Component):
rl=mm_reg[2]
qsys_inst_mid+=',\n\n'+QSYS_EXPORT_PORT_MAP.replace('$name', name).replace('$addr_width', str(addr_width))
if rl==0:
- qsys_inst_mid+=',\n\n %s_waitrequest => %s_miso.waitrequest' %(name,name)
+ qsys_inst_mid+=',\n\n %s_waitrequest_export => %s_miso.waitrequest' %(name,name)
target_vhdl_file.write(qsys_inst_mid)
target_vhdl_file.write(QSYS_INST_END)