From 706199a83adb0538e99b9e03b397c2d2ef1ab857 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 28 Apr 2015 15:33:26 +0000
Subject: [PATCH] testing the DDR stream
---
.../revisions/unb1_test_10GbE/hdllib.cfg | 7 +----
.../unb1_test/src/vhdl/ddr_stream_test.vhd | 27 +++++++++++++------
.../unb1_test/src/vhdl/udp_stream_test.vhd | 16 +++++------
.../designs/unb1_test/src/vhdl/unb1_test.vhd | 17 +++++++++++-
.../unb1_test/tb/python/tc_unb1_test.py | 21 +++++++++++++++
5 files changed, 63 insertions(+), 25 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 955e472351..532b58bf58 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_10GbE
hdl_library_clause_name = unb1_test_10GbE_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv
@@ -51,8 +51,3 @@ quartus_qip_files =
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
-modelsim_search_libraries =
-# stratixiv only
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd
index 45e61614e8..cc482ef0d6 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd
@@ -134,6 +134,7 @@ ARCHITECTURE str OF ddr_stream_test IS
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
+ SIGNAL ddr_ref_rst : STD_LOGIC;
SIGNAL ddr_out_clk_i : STD_LOGIC;
SIGNAL ddr_out_rst_i : STD_LOGIC;
@@ -158,13 +159,13 @@ BEGIN
dp_clk => dp_clk,
en_sync => '1',
- out_sosi_arr => block_gen_src_out_arr,--block_gen_src_1GbE_out_arr,
- out_siso_arr => block_gen_src_in_arr,--block_gen_src_1GbE_in_arr,
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,--reg_diag_bg_1GbE_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,--reg_diag_bg_1GbE_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,--ram_diag_bg_1GbE_mosi,
- ram_bg_data_miso => ram_diag_bg_miso --ram_diag_bg_1GbE_miso
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
);
@@ -210,7 +211,6 @@ BEGIN
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
- --in_sync => diag_data_buf_snk_in_arr(0).sop,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
@@ -257,6 +257,17 @@ BEGIN
);
+ u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ PORT MAP(
+ clk => dp_clk,
+ in_rst => '0',
+ out_rst => ddr_ref_rst
+ );
+
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
@@ -284,7 +295,7 @@ BEGIN
-- DDR reference clock
ctlr_ref_clk => dp_clk,
- ctlr_ref_rst => dp_rst,
+ ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk_i,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
index b7cb00e69c..f0e63d91b8 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
@@ -166,13 +166,13 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- out_sosi_arr => block_gen_src_out_arr,--block_gen_src_1GbE_out_arr,
- out_siso_arr => block_gen_src_in_arr,--block_gen_src_1GbE_in_arr,
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,--reg_diag_bg_1GbE_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,--reg_diag_bg_1GbE_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,--ram_diag_bg_1GbE_mosi,
- ram_bg_data_miso => ram_diag_bg_miso --ram_diag_bg_1GbE_miso
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
);
gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE
@@ -196,9 +196,6 @@ BEGIN
);
END GENERATE;
- --gen_bg_src_out_arr : FOR i IN 0 TO g_nof_streams-1 GENERATE
- -- bg_src_out_arr(i) <= fifo_block_gen_src_out_arr(i);
- --END GENERATE;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
@@ -336,7 +333,6 @@ BEGIN
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
- --in_sync => diag_data_buf_snk_in_arr(0).sop,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 919dd5e424..d8e8c22cb3 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -169,6 +169,21 @@ ARCHITECTURE str OF unb1_test IS
CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
+ -- ddr
+ CONSTANT c_wr_chunksize : POSITIVE := 256;
+ CONSTANT c_wr_nof_chunks : POSITIVE := 1;
+ CONSTANT c_rd_chunksize : POSITIVE := 32;
+ CONSTANT c_rd_nof_chunks : POSITIVE := 8;
+ CONSTANT c_rd_interval : POSITIVE := 32;
+ CONSTANT c_gapsize : NATURAL := 0;
+ CONSTANT c_nof_blocks : POSITIVE := 32;
+ CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_rd_interval,
+ c_gapsize,
+ c_nof_blocks);
+
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
@@ -824,7 +839,7 @@ BEGIN
g_bg_gapsize => c_bg_gapsize,
g_bg_blocks_per_sync => c_bg_blocks_per_sync,
g_tech_ddr => c_ddr_master,
- g_reorder_seq => c_reorder_seq_same,
+ g_reorder_seq => c_reorder_seq_conf,--c_reorder_seq_same,
g_ena_pre_transp => FALSE
)
PORT MAP (
diff --git a/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py b/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
index 1e175e50fa..814ccb8d9f 100644
--- a/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
+++ b/boards/uniboard1/designs/unb1_test/tb/python/tc_unb1_test.py
@@ -63,6 +63,7 @@ import pi_bsn_monitor
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_debug_wave
+import pi_io_ddr
from tools import *
from common import *
@@ -122,6 +123,10 @@ def test_BG_to_DB(tc,io,cmd):
Bg.write_enable()
+ ddr = pi_io_ddr.PiIoDdr(tc,io,nof_inst=1)
+ if tc.sim == True:
+ do_until_eq(ddr.read_init_done, ms_retry=1000, val=1, s_timeout=13600) # 110000
+
bg_ram = []
for s in tc.gpNumbers:
ram = Bg.read_waveform_ram(channelNr=s,vLevel=5)
@@ -133,6 +138,12 @@ def test_BG_to_DB(tc,io,cmd):
rram.append(ram_10G)
bg_ram.append(rram)
+
+ # Poll the databuffer to check if the response is there.
+ # Retry after 3 seconds so we don't issue too many MM reads in case of simulation.
+ do_until_ge(Db.read_nof_words, ms_retry=3000, val=blocksize, s_timeout=3600)
+
+
db_ram = []
for s in tc.gpNumbers:
databuf = Db.read_data_buffer(streamNr=s,vLevel=5)
@@ -278,6 +289,15 @@ def test_tr_10GbE(tc,io,cmd):
verify_10GbE_status(tc,stat_name,tr10.read_reg(tc.nodeNrs,'REG_TR_10GBE',inst_offs+(REGMAP[stat_name][2][0]),1))
+def test_ddr_stat(tc,io,cmd):
+ tc.set_section_id('DDR3 status - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ from pi_io_ddr import REGMAP,PiIoDdr
+ on_execute(class_definition=PiIoDdr,regmap=REGMAP)
+
def test_bsn_mon(tc,io,cmd):
tc.set_section_id('Read BSN monitor status - ')
@@ -483,6 +503,7 @@ Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_RE
Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
Cmd['XAUI'] = (test_tr_xaui, 'using pi_tr_xaui to read xaui status (access REG_TR_XAUI)','(-r for addressing streams)')
Cmd['10GBE'] = (test_tr_10GbE,'using pi_tr_10GbE to read 10GbE status (access REG_TR_10GBE)','(-r for addressing streams)')
+Cmd['DDR'] = (test_ddr_stat,'using pi_io_ddr to read DDR3 status (access REG_IO_DDR)','')
Cmd['BSN'] = (test_bsn_mon, 'using pi_bsn_monitor to read BSN monitor (access REG_BSN_MONITOR)','')
Cmd['BGDB'] = (test_BG_to_DB,'using BG (pi_diag_block_gen.py) and DB (pi_diag_data_buffer.py)','(-r and -s for addressing streams, -n1 for use pps)')
Cmd['BGs00100'] = (write_BG_00100,'set test BG pattern ...000000000010000000000...','(-r and -s for addressing streams)')
--
GitLab