From 70174216485217bde6fc0b4ef72ba412631949b6 Mon Sep 17 00:00:00 2001 From: Eric Kooistra <kooistra@astron.nl> Date: Fri, 25 Jun 2021 13:11:16 +0200 Subject: [PATCH] Updated mmap gold files for beamformer with N_beamsets = 2. --- .../lofar2_unb2b_sdp_station.mmap.gold | 24 +++++++++---------- .../lofar2_unb2b_sdp_station.mmap.qsys.gold | 24 +++++++++---------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold index 6bf27f1614..4ded0a3d24 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold @@ -110,7 +110,7 @@ number_of_columns = 13 - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - - - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - - - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - - - REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - 12 1 + REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2 REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - - - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - - - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - - @@ -130,24 +130,24 @@ number_of_columns = 13 - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - - - - - - - 0x00028007 - - - b[31:0] b[63:32] - - - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - - - REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - 48 4 + REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4 - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - - - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - - - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - - - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - - - RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - 16384 1024 - REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] 48 4 + RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024 + REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] - 4 - - - - - 0x00030001 - - - b[31:0] b[63:32] - - - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - - - - - - - 0x00030003 - - - b[31:0] b[63:32] - - - REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - 24 2 + REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - - 2 - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - - - RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - 16384 1024 + RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - - 1024 REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - - - RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - 16384 1024 - RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - 8192 1024 + RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - - 1024 + RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024 REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - - - RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] 16384 2048 + RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] - 2048 - - - - - 0x00042001 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - - @@ -242,10 +242,10 @@ number_of_columns = 13 - - - - - 0x0005a027 - - - b[15:0] b[47:32] - - - - - - eth_destination_mac 0x0005a028 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x0005a029 - - - b[15:0] b[47:32] - - - REG_DP_XONOFF 2 1 REG enable_stream 0x0005c000 1 RW uint32 b[0:0] - 1 1 - RAM_ST_BST 1 1 RAM data 0x0005e000 1952 RW uint64 b[31:0] b[31:0] - - + REG_DP_XONOFF 2 1 REG enable_stream 0x0005c000 1 RW uint32 b[0:0] - 2 2 + RAM_ST_BST 2 1 RAM data 0x0005e000 1952 RW uint64 b[31:0] b[31:0] 2048 2048 - - - - - 0x0005c001 - - - b[21:0] b[53:32] - - - REG_STAT_ENABLE_BST 2 1 REG enable 0x00060000 1 RW uint32 b[0:0] - 1 1 + REG_STAT_ENABLE_BST 2 1 REG enable 0x00060000 1 RW uint32 b[0:0] - 2 2 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] 64 64 - - - - - 0x00062001 - - - b[31:0] b[63:32] - - - - - - block_period 0x00062002 1 RW uint32 b[15:0] - - - diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold index 2a5f980881..916d6e2848 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold @@ -110,7 +110,7 @@ number_of_columns = 13 - - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - - - - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - - - - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - - - REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - 16 1 + REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2 REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000df0 1 RW uint32 b[0:0] - - - - - - - dp_on_pps 0x00000df0 1 RW uint32 b[1:1] - - - - - - - nof_block_per_sync 0x00000df1 1 RW uint32 b[31:0] - - - @@ -130,24 +130,24 @@ number_of_columns = 13 - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - - - - - - - 0x00000107 - - - b[31:0] b[63:32] - - - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - - - REG_WG 1 12 REG mode 0x00000cc0 1 RW uint32 b[7:0] - 64 4 + REG_WG 1 12 REG mode 0x00000cc0 1 RW uint32 b[7:0] - - 4 - - - - nof_samples 0x00000cc0 1 RW uint32 b[31:16] - - - - - - - phase 0x00000cc1 1 RW uint32 b[15:0] - - - - - - - freq 0x00000cc2 1 RW uint32 b[30:0] - - - - - - - ampl 0x00000cc3 1 RW uint32 b[16:0] - - - - RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - 16384 1024 - REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d00 1 RO int64 b[31:0] b[31:0] 64 4 + RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024 + REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d00 1 RO int64 b[31:0] b[31:0] - 4 - - - - - 0x00000d01 - - - b[31:0] b[63:32] - - - - - - power_sum 0x00000d02 1 RO int64 b[31:0] b[31:0] - - - - - - - 0x00000d03 - - - b[31:0] b[63:32] - - - REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - 32 2 + REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2 - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - - - RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - 16384 1024 + RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024 REG_SI 1 1 REG enable 0x0002d028 1 RW uint32 b[0:0] - - - - RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - 16384 1024 - RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - 8192 1024 + RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024 + RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024 REG_DP_SELECTOR 1 1 REG input_select 0x0002d024 1 RW uint32 b[0:0] - - - - RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] 16384 2048 + RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] - 2048 - - - - - 0x0002d025 - - - b[21:0] b[53:32] - - REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d01e 1 RW uint32 b[0:0] - - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] - - @@ -242,10 +242,10 @@ number_of_columns = 13 - - - - - 0x000000a7 - - - b[15:0] b[47:32] - - - - - - eth_destination_mac 0x000000a8 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x000000a9 - - - b[15:0] b[47:32] - - - REG_DP_XONOFF 2 1 REG enable_stream 0x0002d010 1 RW uint32 b[0:0] - 1 1 - RAM_ST_BST 1 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] - - + REG_DP_XONOFF 2 1 REG enable_stream 0x0002d010 1 RW uint32 b[0:0] - 2 2 + RAM_ST_BST 2 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] 2048 2048 - - - - - 0x0002d011 - - - b[21:0] b[53:32] - - - REG_STAT_ENABLE_BST 2 1 REG enable 0x00000000 1 RW uint32 b[0:0] - 1 1 + REG_STAT_ENABLE_BST 2 1 REG enable 0x00000000 1 RW uint32 b[0:0] - 2 2 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000000 1 RW uint64 b[31:0] b[31:0] 64 64 - - - - - 0x00000001 - - - b[31:0] b[63:32] - - - - - - block_period 0x00000002 1 RW uint32 b[15:0] - - - -- GitLab