From 7011060fff0c7ce0dda76bdd8349cca2973f6fe2 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 11 May 2016 13:01:26 +0000
Subject: [PATCH] Added regression_test_vhdl key with some VHDL tb.
---
libraries/dsp/filter/hdllib.cfg | 4 ++++
libraries/dsp/rTwoSDF/hdllib.cfg | 3 +++
libraries/dsp/st/hdllib.cfg | 4 ++++
libraries/io/aduh/hdllib.cfg | 7 +++++++
4 files changed, 18 insertions(+)
diff --git a/libraries/dsp/filter/hdllib.cfg b/libraries/dsp/filter/hdllib.cfg
index 05f00bc170..06bbfcb9bf 100644
--- a/libraries/dsp/filter/hdllib.cfg
+++ b/libraries/dsp/filter/hdllib.cfg
@@ -15,6 +15,10 @@ test_bench_files =
tb/vhdl/tb_fil_ppf_single.vhd
tb/vhdl/tb_fil_ppf_wide.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_fil_ppf_single.vhd
+ tb/vhdl/tb_fil_ppf_wide.vhd
+
[modelsim_project_file]
modelsim_copy_files = src/hex hex
diff --git a/libraries/dsp/rTwoSDF/hdllib.cfg b/libraries/dsp/rTwoSDF/hdllib.cfg
index e8c3fbef0b..2a0b2fbbe5 100644
--- a/libraries/dsp/rTwoSDF/hdllib.cfg
+++ b/libraries/dsp/rTwoSDF/hdllib.cfg
@@ -20,6 +20,9 @@ test_bench_files =
tb/vhdl/tb_tb_rTwoSDF.vhd
tb/vhdl/tb_rTwoOrder.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_rTwoSDF.vhd
+
[modelsim_project_file]
modelsim_copy_files = tb/data data
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index da029b5947..660c6f533c 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -16,6 +16,10 @@ test_bench_files =
tb/vhdl/tb_st_calc.vhd
tb/vhdl/tb_mmf_st_sst.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_st_acc.vhd
+ #tb/vhdl/tb_st_calc.vhd -- tb is not self checking yet
+
[modelsim_project_file]
diff --git a/libraries/io/aduh/hdllib.cfg b/libraries/io/aduh/hdllib.cfg
index d2e7e76aea..5ae338934a 100644
--- a/libraries/io/aduh/hdllib.cfg
+++ b/libraries/io/aduh/hdllib.cfg
@@ -37,6 +37,13 @@ test_bench_files =
tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_aduh_dd.vhd
+ tb/vhdl/tb_aduh_verify.vhd
+ tb/vhdl/tb_mms_aduh_quad.vhd
+ tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
+ tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+
[modelsim_project_file]
--
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