diff --git a/libraries/dsp/filter/hdllib.cfg b/libraries/dsp/filter/hdllib.cfg
index 05f00bc1701b13a85c41f0b619412314f66846ef..06bbfcb9bf820f03c04d0c9802d7d70e6075128a 100644
--- a/libraries/dsp/filter/hdllib.cfg
+++ b/libraries/dsp/filter/hdllib.cfg
@@ -15,6 +15,10 @@ test_bench_files =
     tb/vhdl/tb_fil_ppf_single.vhd 
     tb/vhdl/tb_fil_ppf_wide.vhd 
 
+regression_test_vhdl = 
+    tb/vhdl/tb_fil_ppf_single.vhd 
+    tb/vhdl/tb_fil_ppf_wide.vhd 
+
 
 [modelsim_project_file]
 modelsim_copy_files = src/hex hex                                                   
diff --git a/libraries/dsp/rTwoSDF/hdllib.cfg b/libraries/dsp/rTwoSDF/hdllib.cfg
index e8c3fbef0bbd907d59314e1483aa0876acdd0cf9..2a0b2fbbe5fb2b1d331b0fda42042f3944c38f01 100644
--- a/libraries/dsp/rTwoSDF/hdllib.cfg
+++ b/libraries/dsp/rTwoSDF/hdllib.cfg
@@ -20,6 +20,9 @@ test_bench_files =
     tb/vhdl/tb_tb_rTwoSDF.vhd 
     tb/vhdl/tb_rTwoOrder.vhd 
 
+regression_test_vhdl = 
+    tb/vhdl/tb_rTwoSDF.vhd 
+
 
 [modelsim_project_file]
 modelsim_copy_files = tb/data data                                                   
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index da029b594799a82d0751b9f92c07c7aff3eab9a0..660c6f533ce2a2b0b6ce93d12acab8a7683d0441 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -16,6 +16,10 @@ test_bench_files =
     tb/vhdl/tb_st_calc.vhd 
     tb/vhdl/tb_mmf_st_sst.vhd   
 
+regression_test_vhdl = 
+    tb/vhdl/tb_st_acc.vhd 
+    #tb/vhdl/tb_st_calc.vhd   -- tb is not self checking yet
+
 
 [modelsim_project_file]
 
diff --git a/libraries/io/aduh/hdllib.cfg b/libraries/io/aduh/hdllib.cfg
index d2e7e76aea5adf01c94f1c28d09c484fa7419f49..5ae338934a3de6cee3ca3b0566ba617d6976eb87 100644
--- a/libraries/io/aduh/hdllib.cfg
+++ b/libraries/io/aduh/hdllib.cfg
@@ -37,6 +37,13 @@ test_bench_files =
     tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
     tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_aduh_dd.vhd
+    tb/vhdl/tb_aduh_verify.vhd
+    tb/vhdl/tb_mms_aduh_quad.vhd
+    tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
+    tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+
 
 [modelsim_project_file]