diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
index 7fab26f9bd22f644055ece606d24b2c9f6cddc53..f0cb4cceee5dbee92840328c7cb808b95ec7c304 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
@@ -22,18 +22,25 @@
-- Purpose:
-- . Test bench for dp_xonoff
-- Description:
+-- . The dp_xonoff provides flow control per packet.
+-- . If extra dp_xonoff are placed in series then it will take as many extra
+-- input packets before they are output again.
+--
-- . Block diagram:
--
--- p_stimuli_st proc_dp_verify_*()
+-- p_stimuli_st proc_dp_verify_*()
--
--- stimuli_src_in verify_snk_out
--- stimuli_src_out verify_snk_in
--- | ____________________________ |
--- | | DUT | |
--- | | | |
--- <-----| dut_snk_out dut_src_in |<-----
--- ----->| dut_snk_in dut_src_out|----->
--- |____________________________|
+-- stimuli_src_in verify_snk_out
+-- stimuli_src_out verify_snk_in
+-- | _____ _____ _____ _____ |
+-- | |DUT| |DUT| |DUT| |DUT| |
+-- | | | | | | | | | |
+-- <-----| 0 |<--| 1 |<--| 2 |<-- <--|nof|<-----
+-- ----->| |-->| |-->| |--> -->|dut|----->
+-- | | | | | | | -1|
+-- |___| |___| |___| |___|
+--
+-- _arr[-1] [0] [1] [2] [g_nof_dut-1]
--
--
-- Usage:
@@ -63,6 +70,7 @@ ENTITY tb_dp_xonoff IS
g_in_dat_w : NATURAL := 32;
g_in_nof_words : NATURAL := 1;
g_nof_repeat : NATURAL := 5;
+ g_nof_dut : NATURAL := 10;
g_pkt_len : NATURAL := 16; -- must be a multiple of g_in_nof_words
g_pkt_gap : NATURAL := 4
);
@@ -72,6 +80,7 @@ END tb_dp_xonoff;
ARCHITECTURE tb OF tb_dp_xonoff IS
CONSTANT c_rl : NATURAL := 1;
+ CONSTANT c_nof_repeat : NATURAL := g_nof_repeat + g_nof_dut;
CONSTANT c_pulse_active : NATURAL := g_in_nof_words;
CONSTANT c_pulse_period : NATURAL := g_in_nof_words;
@@ -101,11 +110,8 @@ ARCHITECTURE tb OF tb_dp_xonoff IS
SIGNAL stimuli_src_out : t_dp_sosi;
SIGNAL stimuli_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
- SIGNAL dut_snk_out : t_dp_siso;
- SIGNAL dut_snk_in : t_dp_sosi;
-
- SIGNAL dut_src_in : t_dp_siso;
- SIGNAL dut_src_out : t_dp_sosi;
+ SIGNAL dut_siso_arr : t_dp_siso_arr(g_nof_dut-1 DOWNTO -1);
+ SIGNAL dut_sosi_arr : t_dp_sosi_arr(g_nof_dut-1 DOWNTO -1);
SIGNAL prev_verify_snk_out : t_dp_siso;
SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy;
@@ -121,6 +127,8 @@ ARCHITECTURE tb OF tb_dp_xonoff IS
SIGNAL verify_done : STD_LOGIC := '0';
SIGNAL expected_verify_snk_in : t_dp_sosi;
+ SIGNAL exp_size : NATURAL;
+ SIGNAL cnt_size : NATURAL;
BEGIN
@@ -165,7 +173,7 @@ BEGIN
proc_common_wait_some_cycles(clk, 5);
-- Generate c_nof_repeat packets
- FOR I IN 0 TO g_nof_repeat-1 LOOP
+ FOR I IN 0 TO c_nof_repeat-1 LOOP
-- Auto increment v_sosi field values for this packet
v_sosi.bsn := INCR_UVEC(v_sosi.bsn, 1);
v_sosi.sync := sel_a_b((UNSIGNED(v_sosi.bsn) MOD c_sync_period) = c_sync_offset, '1', '0'); -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
@@ -183,9 +191,9 @@ BEGIN
-- Determine expected sosi field values after end of stimuli
-- . e_qual
- v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
- v_sosi.channel := TO_DP_CHANNEL(c_channel_init + g_nof_repeat-1);
- v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat-1);
+ v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + c_nof_repeat-1);
+ v_sosi.channel := TO_DP_CHANNEL(c_channel_init + c_nof_repeat-1);
+ v_sosi.err := TO_DP_ERROR(c_err_init + c_nof_repeat-1);
-- . account for g_pkt_len
v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len-1);
v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
@@ -202,7 +210,8 @@ BEGIN
------------------------------------------------------------------------------
-- DATA VERIFICATION
- ------------------------------------------------------------------------------
+ -------------------------------- proc_common_wait_until_hi_lo(clk, dut_snk_in.sop);
+----------------------------------------------
-- Start verify after first valid, sop or eop
verify_en_valid <= '1' WHEN verify_snk_in.valid='1' AND rising_edge(clk);
@@ -219,7 +228,7 @@ BEGIN
--proc_dp_verify_value("verify_snk_in.err", e_equal, clk, verify_done, expected_verify_snk_in.err, verify_snk_in.err);
-- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
+ --proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
--proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
--proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
--proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
@@ -230,36 +239,52 @@ BEGIN
-- Verify output packet ctrl
proc_dp_verify_sop_and_eop(clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, verify_hold_sop);
+ -- Verify output packet block size
+ exp_size <= g_pkt_len;
+
+ proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size);
+
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
+ p_verify_xonoff : PROCESS
+ BEGIN
+ verify_snk_out.xon <= '1';
+ proc_common_wait_until_hi_lo(clk, stimuli_src_out.sop);
+ verify_snk_out.xon <= '0';
+ proc_common_wait_until_hi_lo(clk, stimuli_src_out.sop);
+ verify_snk_out.xon <= '1';
+
+ WAIT;
+ END PROCESS;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
-- Connect stimuli input stream to DUT sink
- stimuli_src_in <= dut_snk_out;
- dut_snk_in <= stimuli_src_out;
+ stimuli_src_in.ready <= dut_siso_arr(-1).ready;
+ stimuli_src_in.xon <= '1';
+ dut_sosi_arr(-1) <= stimuli_src_out;
-- DUT function
- u_dut : ENTITY work.dp_xonoff
- PORT MAP (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => dut_snk_out,
- in_sosi => dut_snk_in,
- -- Frame out
- out_siso => dut_src_in, -- flush control via out_siso.xon
- out_sosi => dut_src_out
- );
-
-
+ gen_dut : FOR I IN 0 TO g_nof_dut-1 GENERATE
+ u_dut : ENTITY work.dp_xonoff
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => dut_siso_arr(I-1),
+ in_sosi => dut_sosi_arr(I-1),
+ -- Frame out
+ out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
+ out_sosi => dut_sosi_arr(I)
+ );
+ END GENERATE;
-- Connect DUT source output stream to verification
- dut_src_in <= verify_snk_out;
- verify_snk_in <= dut_src_out;
+ dut_siso_arr(g_nof_dut-1) <= verify_snk_out;
+ verify_snk_in <= dut_sosi_arr(g_nof_dut-1);
------------------------------------------------------------------------------