diff --git a/boards/uniboard2b/designs/unb2b_jesd/doc/README b/boards/uniboard2b/designs/unb2b_jesd/doc/README
index 834b38f1d711fb31e834273dfcebd139b2cd3a1a..a8ee798172b26c69d51affd65034e1d8b8b5b3c6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/doc/README
+++ b/boards/uniboard2b/designs/unb2b_jesd/doc/README
@@ -1,3 +1,10 @@
+-> JESD204B core referece doc:
+   https://www.intel.com/content/www/us/en/programmable/documentation/bhc1411117158599.html
+
+-> JESD204B example design doc:
+   https://www.intel.com/content/www/us/en/programmable/documentation/dsy1488866740587.html#uja1488433315226
+
+
 -> See also the doc/README files in the revision directories
 
 Quick steps to compile and use design [unb2b_jesd] in RadionHDL
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 26f2d420e2b35dc8526a05e07c7ed824e63ad5f2..bc7abac851ef417315feb804c3ae425820bd7424 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -41,7 +41,6 @@ ENTITY unb2b_jesd_node0 IS
     g_stamp_date        : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time        : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn         : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_factory_image     : BOOLEAN := TRUE;
     g_protect_addr_range: BOOLEAN := FALSE
   );
   PORT (
@@ -96,7 +95,6 @@ BEGIN
     g_stamp_date        => g_stamp_date,
     g_stamp_time        => g_stamp_time,
     g_stamp_svn         => g_stamp_svn,
-    g_factory_image     => g_factory_image,
     g_protect_addr_range => g_protect_addr_range
   )
   PORT MAP (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 5899faf0a9563806d29a754ef6698a3c6b2aa078..088b8a43361758e264335b41250b1f188a3aff3e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -41,7 +41,6 @@ ENTITY unb2b_jesd_node3 IS
     g_stamp_date        : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time        : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn         : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_factory_image     : BOOLEAN := TRUE;
     g_protect_addr_range: BOOLEAN := FALSE
   );
   PORT (
@@ -96,7 +95,6 @@ BEGIN
     g_stamp_date        => g_stamp_date,
     g_stamp_time        => g_stamp_time,
     g_stamp_svn         => g_stamp_svn,
-    g_factory_image     => g_factory_image,
     g_protect_addr_range => g_protect_addr_range
   )
   PORT MAP (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 8a9c73c57cf06601bb8f2b3b8ff36b0faf98be44..6ff3fffd7c30bbae5b60df32b0fbebd6340306a9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -41,7 +41,7 @@ ENTITY unb2b_jesd IS
     g_stamp_date        : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time        : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn         : NATURAL := 0;  -- SVN revision    -- set by QSF
-    g_factory_image     : BOOLEAN := TRUE;
+    g_factory_image     : BOOLEAN := FALSE;
     g_protect_addr_range: BOOLEAN := FALSE
   );
   PORT (
@@ -169,7 +169,6 @@ ARCHITECTURE str OF unb2b_jesd IS
   SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
 
   -- JESD signals
-  signal pll_locked : std_logic;
 
   signal jesd204_rx_link_error : std_logic;
   signal jesd204_rx_link_data  : std_logic_vector(31 downto 0);
@@ -304,9 +303,7 @@ BEGIN
     -- . 1GbE Control Interface
     ETH_clk                  => ETH_CLK,
     ETH_SGIN                 => ETH_SGIN,
-    ETH_SGOUT                => ETH_SGOUT,
-
-    pll_locked => pll_locked
+    ETH_SGOUT                => ETH_SGOUT
   );
 
   -----------------------------------------------------------------------------
@@ -398,7 +395,6 @@ BEGIN
     jesd204_device_clk       => st_clk
   );
 
-  QSFP_LED(0)          <= pll_locked;
   CLK                  <= jesd204_device_clk;
   --PPS                  <= jesd204_rx_sysref;
   jesd204_rx_sysref_n  <= NOT jesd204_rx_sysref;