diff --git a/libraries/technology/xaui/hdllib.cfg b/libraries/technology/xaui/hdllib.cfg
index ab10d00edc47b63e603f8a396ffb75b78ceb40ba..940e2321818aca82aad610cb8893d140376e0671 100644
--- a/libraries/technology/xaui/hdllib.cfg
+++ b/libraries/technology/xaui/hdllib.cfg
@@ -8,5 +8,8 @@ build_synth_dir = $HDL_BUILD_DIR
synth_files =
tech_xaui_component_pkg.vhd
+ tech_xaui_pkg.vhd
+ tech_xaui_stratixiv.vhd
+ tech_xaui.vhd
test_bench_files =
diff --git a/libraries/technology/xaui/tech_xaui.vhd b/libraries/technology/xaui/tech_xaui.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2798395d03149dba8d97aa119c5ecaec6359e709
--- /dev/null
+++ b/libraries/technology/xaui/tech_xaui.vhd
@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.tech_xaui_component_pkg.ALL;
+USE work.tech_xaui_pkg.ALL;
+
+ENTITY tech_xaui IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_xaui : NATURAL := 1 -- Up to 3 (hard XAUI only) supported
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_clk : IN STD_LOGIC;
+ trc_rst : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC;
+
+ tx_clk : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+ rx_clk : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ crc_rx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
+ crc_tx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ a_rx_channelaligned : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ xgmii_tx_dc : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+ xgmii_rx_dc : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+
+ xaui_rx : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
+ xaui_tx : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
+
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ xaui_miso : OUT t_mem_miso
+ );
+END tech_xaui;
+
+
+ARCHITECTURE str OF tech_xaui IS
+
+BEGIN
+
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ENTITY work.tech_xaui_stratixiv
+ GENERIC MAP (g_nof_xaui)
+ PORT MAP (tr_clk, trc_rst, mm_clk, mm_rst, cal_rec_clk, tx_clk, rx_clk,
+ crc_rx_ready, crc_tx_ready, a_rx_channelaligned,
+ xgmii_tx_dc, xgmii_rx_dc,
+ xaui_rx, xaui_tx,
+ xaui_mosi, xaui_miso);
+ END GENERATE;
+
+END str;
+
diff --git a/libraries/technology/xaui/tech_xaui_pkg.vhd b/libraries/technology/xaui/tech_xaui_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cdc772a0f4d303f2e8856ca6b8603fe7f3222284
--- /dev/null
+++ b/libraries/technology/xaui/tech_xaui_pkg.vhd
@@ -0,0 +1,145 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE tech_xaui_pkg IS
+
+ CONSTANT c_nof_xaui_lanes : NATURAL := 4;
+
+ CONSTANT c_xgmii_data_w : NATURAL := 64;
+ CONSTANT c_xgmii_nof_lanes : NATURAL := 8;
+
+ CONSTANT c_xgmii_ctrl_w : NATURAL := c_xgmii_nof_lanes;
+ CONSTANT c_xgmii_lane_data_w : NATURAL := c_xgmii_data_w / c_xgmii_nof_lanes;
+ CONSTANT c_xgmii_w : NATURAL := c_xgmii_data_w + c_xgmii_ctrl_w;
+
+ CONSTANT c_xgmii_d_idle : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0) := x"0707070707070707";
+ CONSTANT c_xgmii_d_start : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0) := x"00000000000000FB";
+ CONSTANT c_xgmii_d_term : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0) := x"07070707FD000000";
+
+ CONSTANT c_xgmii_c_init : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0) := x"11"; -- During (re)initialization
+ CONSTANT c_xgmii_c_idle : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0) := x"FF";
+ CONSTANT c_xgmii_c_data : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0) := x"00";
+ CONSTANT c_xgmii_c_start : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0) := x"01"; --b'00000001' as byte 0 contains START word FB
+ CONSTANT c_xgmii_c_term : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0) := x"F8"; --b'11111000' as byte 3 contains TERMINATE word FD, bytes 7..4 are IDLE.
+
+ FUNCTION xgmii_dc( data : IN STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0); ctrl : IN STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR;
+ FUNCTION xgmii_d( data_ctrl: IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR;
+ FUNCTION xgmii_c( data_ctrl: IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR;
+
+ TYPE t_xaui_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0);
+
+ TYPE t_xgmii_dc_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);
+ TYPE t_xgmii_d_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0);
+ TYPE t_xgmii_c_arr IS ARRAY(INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0);
+
+ END tech_xaui_pkg;
+
+PACKAGE BODY tech_xaui_pkg IS
+
+ -- Refer to the 10GBASE-R PHY IP Core section of the Altera Transceiver PHY IP Core User Guide
+ -- (November 2011) page 3-11: SDR XGMII Tx Interface for the proper mapping.
+
+ -- Combine separate data and control bits into one XGMII SLV.
+ FUNCTION xgmii_dc( data : IN STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0); ctrl : IN STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
+ VARIABLE data_ctrl_out : STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);
+ BEGIN
+ -- Lane 0:
+ data_ctrl_out( 7 DOWNTO 0) := data( 7 DOWNTO 0);
+ data_ctrl_out( 8) := ctrl(0);
+ -- Lane 1:
+ data_ctrl_out(16 DOWNTO 9) := data(15 DOWNTO 8);
+ data_ctrl_out(17) := ctrl(1);
+ -- Lane 2:
+ data_ctrl_out(25 DOWNTO 18) := data(23 DOWNTO 16);
+ data_ctrl_out(26) := ctrl(2);
+ -- Lane 3:
+ data_ctrl_out(34 DOWNTO 27) := data(31 DOWNTO 24);
+ data_ctrl_out(35) := ctrl(3);
+ -- Lane 4:
+ data_ctrl_out(43 DOWNTO 36) := data(39 DOWNTO 32);
+ data_ctrl_out(44) := ctrl(4);
+ -- Lane 5:
+ data_ctrl_out(52 DOWNTO 45) := data(47 DOWNTO 40);
+ data_ctrl_out(53) := ctrl(5);
+ -- Lane 6:
+ data_ctrl_out(61 DOWNTO 54) := data(55 DOWNTO 48);
+ data_ctrl_out(62) := ctrl(6);
+ -- Lane 7:
+ data_ctrl_out(70 DOWNTO 63) := data(63 DOWNTO 56);
+ data_ctrl_out(71) := ctrl(7);
+
+ RETURN data_ctrl_out;
+ END;
+
+ -- Extract the data bits from combined data+ctrl XGMII SLV.
+ FUNCTION xgmii_d( data_ctrl: IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
+ VARIABLE data_out : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0);
+ BEGIN
+ -- Lane 0:
+ data_out( 7 DOWNTO 0) := data_ctrl( 7 DOWNTO 0);
+ -- Lane 1:
+ data_out(15 DOWNTO 8) := data_ctrl(16 DOWNTO 9);
+ -- Lane 2:
+ data_out(23 DOWNTO 16) := data_ctrl(25 DOWNTO 18);
+ -- Lane 3:
+ data_out(31 DOWNTO 24) := data_ctrl(34 DOWNTO 27);
+ -- Lane 4:
+ data_out(39 DOWNTO 32) := data_ctrl(43 DOWNTO 36);
+ -- Lane 5:
+ data_out(47 DOWNTO 40) := data_ctrl(52 DOWNTO 45);
+ -- Lane 6:
+ data_out(55 DOWNTO 48) := data_ctrl(61 DOWNTO 54);
+ -- Lane 7:
+ data_out(63 DOWNTO 56) := data_ctrl(70 DOWNTO 63);
+
+ RETURN data_out;
+ END;
+
+ -- Extract the control bits from combined data+ctrl XGMII SLV.
+ FUNCTION xgmii_c( data_ctrl: IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
+ VARIABLE ctrl_out : STD_LOGIC_VECTOR(c_xgmii_nof_lanes-1 DOWNTO 0);
+ BEGIN
+ -- Lane 0:
+ ctrl_out(0) := data_ctrl( 8);
+ -- Lane 1:
+ ctrl_out(1) := data_ctrl(17);
+ -- Lane 2:
+ ctrl_out(2) := data_ctrl(26);
+ -- Lane 3:
+ ctrl_out(3) := data_ctrl(35);
+ -- Lane 4:
+ ctrl_out(4) := data_ctrl(44);
+ -- Lane 5:
+ ctrl_out(5) := data_ctrl(53);
+ -- Lane 6:
+ ctrl_out(6) := data_ctrl(62);
+ -- Lane 7:
+ ctrl_out(7) := data_ctrl(71);
+
+ RETURN ctrl_out;
+ END;
+
+END tech_xaui_pkg;
+
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0c7728f3b08c30bafc8dee4adfcb7a3e88ee17b3
--- /dev/null
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -0,0 +1,265 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_stratixiv_lib, ip_stratixiv_phy_xaui_lib;
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.tech_xaui_component_pkg.ALL;
+USE work.tech_xaui_pkg.ALL;
+
+ENTITY tech_xaui_stratixiv IS
+ GENERIC (
+ g_nof_xaui : NATURAL := 1 -- Up to 3 (hard XAUI only) supported
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_clk : IN STD_LOGIC;
+ trc_rst : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC;
+
+ tx_clk : IN STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+ rx_clk : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ crc_rx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0); --crc = synchronous to Cal_Rec_Clk
+ crc_tx_ready : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ a_rx_channelaligned : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
+
+ xgmii_tx_dc : IN t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+ xgmii_rx_dc : OUT t_xgmii_dc_arr(g_nof_xaui-1 DOWNTO 0);
+
+ xaui_rx : IN t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
+ xaui_tx : OUT t_xaui_arr(g_nof_xaui-1 DOWNTO 0);
+
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ xaui_miso : OUT t_mem_miso
+ );
+END tech_xaui_stratixiv;
+
+
+ARCHITECTURE str OF tech_xaui_stratixiv IS
+
+ CONSTANT c_reconf_togxb_bus_w : NATURAL := 4;
+ CONSTANT c_reconf_fromgxb_bus_w : NATURAL := 17;
+ CONSTANT c_reconf_soft_fromgxb_bus_w : NATURAL := 4*c_reconf_fromgxb_bus_w;
+
+ CONSTANT c_xaui_mosi_addr_w : NATURAL := 9;
+
+ SIGNAL reconfig_togxb : STD_LOGIC_VECTOR(c_reconf_togxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_fromgxb : STD_LOGIC_VECTOR(c_reconf_fromgxb_bus_w-1 DOWNTO 0);
+
+ SIGNAL reconfig_soft_togxb : STD_LOGIC_VECTOR(c_reconf_togxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_soft_fromgxb : STD_LOGIC_VECTOR(c_reconf_soft_fromgxb_bus_w-1 DOWNTO 0);
+
+ SIGNAL reconfig_0_togxb : STD_LOGIC_VECTOR(c_reconf_togxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_0_fromgxb : STD_LOGIC_VECTOR(c_reconf_fromgxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_1_togxb : STD_LOGIC_VECTOR(c_reconf_togxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_1_fromgxb : STD_LOGIC_VECTOR(c_reconf_fromgxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_2_togxb : STD_LOGIC_VECTOR(c_reconf_togxb_bus_w-1 DOWNTO 0);
+ SIGNAL reconfig_2_fromgxb : STD_LOGIC_VECTOR(c_reconf_fromgxb_bus_w-1 DOWNTO 0);
+
+ SIGNAL xaui_mosi_arr : t_mem_mosi_arr(g_nof_xaui-1 DOWNTO 0);
+ SIGNAL xaui_miso_arr : t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0);
+
+BEGIN
+
+ gen_nof_xaui : FOR i IN g_nof_xaui-1 DOWNTO 0 GENERATE
+
+ gen_hard_xaui_0: IF i=0 GENERATE
+ u_ip_phy_xaui : ip_stratixiv_phy_xaui_0
+ PORT MAP (
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk(i),
+ xgmii_rx_clk => rx_clk(i),
+ xgmii_rx_dc => xgmii_rx_dc(i),
+ xgmii_tx_dc => xgmii_tx_dc(i),
+ xaui_rx_serial_data => xaui_rx(i),
+ xaui_tx_serial_data => xaui_tx(i),
+ rx_ready => crc_rx_ready(i),
+ tx_ready => crc_tx_ready(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+
+ rx_channelaligned => a_rx_channelaligned(i),
+
+ -- Reconfig block connections
+ reconfig_to_xcvr => reconfig_0_togxb,
+ reconfig_from_xcvr => reconfig_0_fromgxb
+ );
+
+ u_ip_gxb_reconfig : ip_stratixiv_gxb_reconfig_v111
+ PORT MAP (
+ reconfig_clk => cal_rec_clk,
+ reconfig_fromgxb => reconfig_0_fromgxb,
+ busy => OPEN,
+ reconfig_togxb => reconfig_0_togxb
+ );
+ END GENERATE;
+
+ gen_hard_xaui_1: IF i=1 GENERATE
+ u_ip_phy_xaui : ip_stratixiv_phy_xaui_1
+ PORT MAP (
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk(i),
+ xgmii_rx_clk => rx_clk(i),
+ xgmii_rx_dc => xgmii_rx_dc(i),
+ xgmii_tx_dc => xgmii_tx_dc(i),
+ xaui_rx_serial_data => xaui_rx(i),
+ xaui_tx_serial_data => xaui_tx(i),
+ rx_ready => crc_rx_ready(i),
+ tx_ready => crc_tx_ready(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+
+ rx_channelaligned => a_rx_channelaligned(i),
+
+ -- Reconfig block connections
+ reconfig_to_xcvr => reconfig_1_togxb,
+ reconfig_from_xcvr => reconfig_1_fromgxb
+ );
+
+ u_ip_gxb_reconfig : ip_stratixiv_gxb_reconfig_v111
+ PORT MAP (
+ reconfig_clk => cal_rec_clk,
+ reconfig_fromgxb => reconfig_1_fromgxb,
+ busy => OPEN,
+ reconfig_togxb => reconfig_1_togxb
+ );
+ END GENERATE;
+
+ gen_hard_xaui_2: IF i=2 GENERATE
+ u_ip_phy_xaui : ip_stratixiv_phy_xaui_2
+ PORT MAP (
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk(i),
+ xgmii_rx_clk => rx_clk(i),
+ xgmii_rx_dc => xgmii_rx_dc(i),
+ xgmii_tx_dc => xgmii_tx_dc(i),
+ xaui_rx_serial_data => xaui_rx(i),
+ xaui_tx_serial_data => xaui_tx(i),
+ rx_ready => crc_rx_ready(i),
+ tx_ready => crc_tx_ready(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+
+ rx_channelaligned => a_rx_channelaligned(i),
+
+ -- Reconfig block connections
+ reconfig_to_xcvr => reconfig_2_togxb,
+ reconfig_from_xcvr => reconfig_2_fromgxb
+ );
+
+ u_ip_gxb_reconfig : ip_stratixiv_gxb_reconfig_v111
+ PORT MAP (
+ reconfig_clk => cal_rec_clk,
+ reconfig_fromgxb => reconfig_2_fromgxb,
+ busy => OPEN,
+ reconfig_togxb => reconfig_2_togxb
+ );
+ END GENERATE;
+
+ gen_soft_xaui: IF i=3 GENERATE -- NOTE: this 4th (soft) instance makes the Quartus fitter (11.1, no SP) fail, so is not supported.
+ u_ip_phy_xaui : ip_stratixiv_ip_stratixiv_phy_xaui_soft
+ PORT MAP (
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk(i),
+ xgmii_rx_clk => rx_clk(i),
+ xgmii_rx_dc => xgmii_rx_dc(i),
+ xgmii_tx_dc => xgmii_tx_dc(i),
+ xaui_rx_serial_data => xaui_rx(i),
+ xaui_tx_serial_data => xaui_tx(i),
+ rx_ready => crc_rx_ready(i),
+ tx_ready => crc_tx_ready(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w-1 DOWNTO 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+
+ rx_channelaligned => a_rx_channelaligned(i),
+
+ -- Reconfig block connections
+ reconfig_to_xcvr => reconfig_soft_togxb,
+ reconfig_from_xcvr => reconfig_soft_fromgxb
+ );
+
+ u_ip_gxb_reconfig : ip_stratixiv_gxb_reconfig_v111
+ GENERIC MAP (
+ g_soft => TRUE
+ )
+ PORT MAP (
+ reconfig_clk => cal_rec_clk,
+ reconfig_fromgxb => reconfig_soft_fromgxb,
+ busy => OPEN,
+ reconfig_togxb => reconfig_soft_togxb
+ );
+ END GENERATE;
+
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_xaui,
+ g_mult_addr_w => c_xaui_mosi_addr_w
+ )
+ PORT MAP (
+ mosi => xaui_mosi,
+ miso => xaui_miso,
+ mosi_arr => xaui_mosi_arr,
+ miso_arr => xaui_miso_arr
+ );
+
+END str;
+