diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
index d80778d4147dd8afeef1fa309fd9eb4d0348cbaf..f2e2c0667939a5a81e493dc9aaef0509a40bba71 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
@@ -11,50 +11,50 @@ peripherals:
# Factory / minimal (from ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
- slave_port_names:
+ mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
- slave_port_names:
+ mm_port_names:
- PIO_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
- slave_port_names:
+ mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2b_board/ram_scrap
- slave_port_names:
+ mm_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
- slave_port_names:
+ mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
- slave_port_names:
+ mm_port_names:
- PIO_PPS
- peripheral_name: epcs/epcs
- slave_port_names:
+ mm_port_names:
- REG_EPCS
- peripheral_name: dp/dpmm
- slave_port_names:
+ mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
- slave_port_names:
+ mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
- slave_port_names:
+ mm_port_names:
- REG_REMU
#############################################################################
@@ -62,11 +62,11 @@ peripherals:
#############################################################################
- peripheral_name: tech_jesd204b/jesd_ctrl
- slave_port_names:
+ mm_port_names:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
- slave_port_names:
+ mm_port_names:
- JESD204B
- peripheral_name: dp/dp_shiftram
@@ -74,13 +74,13 @@ peripherals:
- { name: g_nof_streams, value: 12 } # = S_pn
- { name: g_nof_words, value: 4096 }
- { name: g_data_w, value: 16 }
- slave_port_names:
+ mm_port_names:
- REG_DP_SHIFTRAM
- peripheral_name: dp/dp_bsn_source
parameter_overrides:
- { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
- slave_port_names:
+ mm_port_names:
- REG_BSN_SOURCE
# TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
@@ -89,29 +89,29 @@ peripherals:
# - { name: g_nof_clk_per_sync, value: 200000000 } # = f_adc
# - { name: g_block_size, value: 1024 } # = N_fft
# - { name: g_bsn_time_offset_w, value: 10 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
- #slave_port_names:
+ #mm_port_names:
# - REG_BSN_SOURCE_V2
- peripheral_name: dp/dp_bsn_scheduler
- slave_port_names:
+ mm_port_names:
- REG_BSN_SCHEDULER
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
- slave_port_names:
+ mm_port_names:
- REG_BSN_MONITOR_INPUT
- peripheral_name: diag/diag_wg_wideband
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
- slave_port_names:
+ mm_port_names:
- REG_DIAG_WG
- RAM_DIAG_WG
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
- slave_port_names:
+ mm_port_names:
- REG_ADUH_MON
# Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
@@ -122,7 +122,7 @@ peripherals:
# - { name: g_nof_symbols_per_data, value: 1 }
# - { name: g_buffer_nof_symbols, value: 512 }
# - { name: g_buffer_use_sync, value: true }
- # slave_port_names:
+ # mm_port_names:
# - RAM_ADUH_MON
- peripheral_name: diag/diag_data_buffer
@@ -131,7 +131,7 @@ peripherals:
- { name: g_nof_streams, value: 12 } # = S_pn
- { name: g_data_w, value: 16 }
- { name: g_nof_data, value: 1024 }
- slave_port_names:
+ mm_port_names:
- REG_DIAG_DATA_BUF_BSN
- RAM_DIAG_DATA_BUF_BSN
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index de9540b6f918488b48dd31f3dc9fe227ddcbec0e..15c8d9491520943af0974a751f9a88452407ecdf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -38,50 +38,50 @@ peripherals:
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
- slave_port_names:
+ mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
- slave_port_names:
+ mm_port_names:
- PIO_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
- slave_port_names:
+ mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2b_board/ram_scrap
- slave_port_names:
+ mm_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
- slave_port_names:
+ mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
- slave_port_names:
+ mm_port_names:
- PIO_PPS
- peripheral_name: epcs/epcs
- slave_port_names:
+ mm_port_names:
- REG_EPCS
- peripheral_name: dp/dpmm
- slave_port_names:
+ mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
- slave_port_names:
+ mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
- slave_port_names:
+ mm_port_names:
- REG_REMU
#############################################################################
@@ -89,11 +89,11 @@ peripherals:
#############################################################################
- peripheral_name: tech_jesd204b/jesd_ctrl
- slave_port_names:
+ mm_port_names:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
- slave_port_names:
+ mm_port_names:
- JESD204B
- peripheral_name: dp/dp_shiftram
@@ -101,13 +101,13 @@ peripherals:
- { name: g_nof_streams, value: c_S_pn }
- { name: g_nof_words, value: c_V_sample_delay }
- { name: g_data_w, value: c_W_adc_jesd }
- slave_port_names:
+ mm_port_names:
- REG_DP_SHIFTRAM
- peripheral_name: dp/dp_bsn_source
parameter_overrides:
- { name: g_nof_block_per_sync, value: c_nof_block_per_sync }
- slave_port_names:
+ mm_port_names:
- REG_BSN_SOURCE
# TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
@@ -116,29 +116,29 @@ peripherals:
# - { name: g_nof_clk_per_sync, value: c_nof_clk_per_pps }
# - { name: g_block_size, value: c_N_fft }
# - { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
- #slave_port_names:
+ #mm_port_names:
# - REG_BSN_SOURCE_V2
- peripheral_name: dp/dp_bsn_scheduler
- slave_port_names:
+ mm_port_names:
- REG_BSN_SCHEDULER
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
- slave_port_names:
+ mm_port_names:
- REG_BSN_MONITOR_INPUT
- peripheral_name: diag/diag_wg_wideband
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
- slave_port_names:
+ mm_port_names:
- REG_DIAG_WG
- RAM_DIAG_WG
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
- slave_port_names:
+ mm_port_names:
- REG_ADUH_MON
# Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
@@ -149,7 +149,7 @@ peripherals:
# - { name: g_nof_symbols_per_data, value: 1 }
# - { name: g_buffer_nof_symbols, value: 512 }
# - { name: g_buffer_use_sync, value: True }
- # slave_port_names:
+ # mm_port_names:
# - RAM_ADUH_MON
- peripheral_name: diag/diag_data_buffer
@@ -158,7 +158,7 @@ peripherals:
- { name: g_nof_streams, value: c_S_pn }
- { name: g_data_w, value: c_W_adc_jesd }
- { name: g_nof_data, value: c_V_si_db }
- slave_port_names:
+ mm_port_names:
- REG_DIAG_DATA_BUF_BSN
- RAM_DIAG_DATA_BUF_BSN
@@ -167,7 +167,7 @@ peripherals:
#############################################################################
- peripheral_name: si/si
- slave_port_names:
+ mm_port_names:
- REG_SI
- peripheral_name: filter/fil_ppf_w
@@ -175,29 +175,29 @@ peripherals:
- { name: g_nof_taps, value: c_N_taps }
- { name: g_nof_bands, value: c_N_fft }
- { name: g_coef_dat_w, value: c_W_fir_coef }
- slave_port_names:
+ mm_port_names:
- RAM_FIL_COEFS
- peripheral_name: sdp/sdp_subband_equalizer
- slave_port_names:
+ mm_port_names:
- RAM_EQUALIZER_GAINS
- peripheral_name: dp/dp_selector
- slave_port_names:
+ mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
- peripheral_name: st/st_sst_for_sdp
- slave_port_names:
+ mm_port_names:
- RAM_ST_SST
- peripheral_name: common/common_variable_delay
peripheral_group: sst
- slave_port_names:
+ mm_port_names:
- REG_STAT_ENABLE
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
peripheral_group: sst
- slave_port_names:
+ mm_port_names:
- REG_STAT_HDR_INFO
#############################################################################
@@ -205,7 +205,7 @@ peripherals:
#############################################################################
- peripheral_name: sdp/sdp_info
- slave_port_names:
+ mm_port_names:
- REG_SDP_INFO
- peripheral_name: reorder/reorder_col_wide
@@ -214,7 +214,7 @@ peripherals:
- { name: g_wb_factor, value: c_P_pfb }
- { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
- { name: g_nof_ch_sel, value: c_S_sub_bf * c_Q_fft }
- slave_port_names:
+ mm_port_names:
- RAM_SS_SS_WIDE
- peripheral_name: sdp/sdp_bf_weights
@@ -222,7 +222,7 @@ peripherals:
parameter_overrides:
- { name: g_nof_instances, value: c_N_pol_bf * c_A_pn } # A_pn = P_pfb = 6
- { name: g_nof_gains, value: c_N_pol * c_S_sub_bf } # N_pol = Q_fft = 2
- slave_port_names:
+ mm_port_names:
- RAM_BF_WEIGHTS
- peripheral_name: sdp/sdp_bf_scale
@@ -230,12 +230,12 @@ peripherals:
parameter_overrides:
- { name: g_gain_w, value: c_W_beamlet_scale }
- { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
- slave_port_names:
+ mm_port_names:
- REG_BF_SCALE
- peripheral_name: sdp/sdp_beamformer_output_hdr_dat
number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
- slave_port_names:
+ mm_port_names:
- REG_HDR_DAT
- peripheral_name: dp/dp_xonoff
@@ -243,35 +243,35 @@ peripherals:
parameter_overrides:
- { name: g_nof_streams, value: 1 }
- { name: g_combine_streams, value: False }
- slave_port_names:
+ mm_port_names:
- REG_DP_XONOFF
- peripheral_name: st/st_bst_for_sdp
- slave_port_names:
+ mm_port_names:
- RAM_ST_BST
- peripheral_name: common/common_variable_delay
peripheral_group: bst
- slave_port_names:
+ mm_port_names:
- REG_STAT_ENABLE_BST
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
peripheral_group: bst
- slave_port_names:
+ mm_port_names:
- REG_STAT_HDR_INFO_BST
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy
peripheral_group: beamlet_output
parameter_overrides:
- { name: g_nof_macs, value: 1 }
- slave_port_names:
+ mm_port_names:
- REG_NW_10GBE_MAC
- peripheral_name: nw_10GbE/nw_10GbE_eth10g
peripheral_group: beamlet_output
parameter_overrides:
- { name: g_nof_macs, value: 1 }
- slave_port_names:
+ mm_port_names:
- REG_NW_10GBE_ETH10G
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
index e67ea2505228fe54f7bb96bad02b7c7ce9f4f7fe..8913b3d218334598cac6e04fa4428ffba9c867ed 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -11,50 +11,50 @@ peripherals:
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
- slave_port_names:
+ mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
- slave_port_names:
+ mm_port_names:
- PIO_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
- slave_port_names:
+ mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2b_board/ram_scrap
- slave_port_names:
+ mm_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
- slave_port_names:
+ mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
- slave_port_names:
+ mm_port_names:
- PIO_PPS
- peripheral_name: epcs/epcs
- slave_port_names:
+ mm_port_names:
- REG_EPCS
- peripheral_name: dp/dpmm
- slave_port_names:
+ mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
- slave_port_names:
+ mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
- slave_port_names:
+ mm_port_names:
- REG_REMU
#############################################################################
@@ -62,11 +62,11 @@ peripherals:
#############################################################################
- peripheral_name: tech_jesd204b/jesd_ctrl
- slave_port_names:
+ mm_port_names:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
- slave_port_names:
+ mm_port_names:
- JESD204B
- peripheral_name: dp/dp_shiftram
@@ -74,13 +74,13 @@ peripherals:
- { name: g_nof_streams, value: 12 } # = S_pn
- { name: g_nof_words, value: 4096 }
- { name: g_data_w, value: 16 }
- slave_port_names:
+ mm_port_names:
- REG_DP_SHIFTRAM
- peripheral_name: dp/dp_bsn_source
parameter_overrides:
- { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
- slave_port_names:
+ mm_port_names:
- REG_BSN_SOURCE
# TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
@@ -89,29 +89,29 @@ peripherals:
# - { name: g_nof_clk_per_sync, value: 200000000 } # = f_adc
# - { name: g_block_size, value: 1024 } # = N_fft
# - { name: g_bsn_time_offset_w, value: 10 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
- #slave_port_names:
+ #mm_port_names:
# - REG_BSN_SOURCE_V2
- peripheral_name: dp/dp_bsn_scheduler
- slave_port_names:
+ mm_port_names:
- REG_BSN_SCHEDULER
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
- slave_port_names:
+ mm_port_names:
- REG_BSN_MONITOR_INPUT
- peripheral_name: diag/diag_wg_wideband
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
- slave_port_names:
+ mm_port_names:
- REG_DIAG_WG
- RAM_DIAG_WG
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
- slave_port_names:
+ mm_port_names:
- REG_ADUH_MON
# Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
@@ -122,7 +122,7 @@ peripherals:
# - { name: g_nof_symbols_per_data, value: 1 }
# - { name: g_buffer_nof_symbols, value: 512 }
# - { name: g_buffer_use_sync, value: true }
- # slave_port_names:
+ # mm_port_names:
# - RAM_ADUH_MON
- peripheral_name: diag/diag_data_buffer
@@ -131,7 +131,7 @@ peripherals:
- { name: g_nof_streams, value: 12 } # = S_pn
- { name: g_data_w, value: 16 }
- { name: g_nof_data, value: 1024 }
- slave_port_names:
+ mm_port_names:
- REG_DIAG_DATA_BUF_BSN
- RAM_DIAG_DATA_BUF_BSN
@@ -140,7 +140,7 @@ peripherals:
#############################################################################
- peripheral_name: si/si
- slave_port_names:
+ mm_port_names:
- REG_SI
- peripheral_name: filter/fil_ppf_w
@@ -149,25 +149,25 @@ peripherals:
- { name: g_nof_taps, value: 16 } # = N_taps
- { name: g_nof_bands, value: 1024 } # = N_fft
- { name: g_coef_dat_w, value: 16 } # = W_fir_coef
- slave_port_names:
+ mm_port_names:
- RAM_FIL_COEFS
- peripheral_name: sdp/sdp_subband_equalizer
- slave_port_names:
+ mm_port_names:
- RAM_EQUALIZER_GAINS
- peripheral_name: dp/dp_selector
- slave_port_names:
+ mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
- peripheral_name: st/st_sst_for_sdp
- slave_port_names:
+ mm_port_names:
- RAM_ST_SST
- peripheral_name: common/common_variable_delay
- slave_port_names:
+ mm_port_names:
- REG_STAT_ENABLE
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
- slave_port_names:
+ mm_port_names:
- REG_STAT_HDR_INFO
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
index 88f2140b6f59c94fea39c199cb4d881f3f913ede..b9ad15bbbc80f89fafefa2a7b4e206061810d813 100644
--- a/libraries/base/common/common.peripheral.yaml
+++ b/libraries/base/common/common.peripheral.yaml
@@ -13,11 +13,11 @@ peripherals:
can be different for different instances.
The delay is not programmable, but delayed output pulse can be enabled when enable = 1
or disabled when enable = 0."
- slave_ports:
+ mm_ports:
# MM port for mms_common_variable_delay.vhd / mms_common_reg.vhd
- - slave_name: REG_COMMON_VARIABLE_DELAY
- slave_type: REG
- slave_description: ""
+ - mm_port_name: REG_COMMON_VARIABLE_DELAY
+ mm_port_type: REG
+ mm_port_description: ""
fields:
- - field_name: enable
field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index 6369308df94344a9e2cf815b0101a55d468ad42f..c92c4a5823e36e62d9b5d26da9d022fb043b7b96 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -11,12 +11,12 @@ peripherals:
parameters:
# Parameters of mms_diag_wg_wideband_arr.vhd
- { name: g_nof_streams, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for diag_wg_wideband_reg.vhd
- - slave_name: REG_DIAG_WG
- slave_description: "Waveform control."
- slave_type: REG
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_DIAG_WG
+ mm_port_description: "Waveform control."
+ mm_port_type: REG
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: nof_samples
field_description: "Number of samples in WG period."
@@ -49,10 +49,10 @@ peripherals:
bit_offset: 0
address_offset: 0xC
# MM port for mms_diag_wg_wideband.vhd
- - slave_name: RAM_DIAG_WG
- slave_description: "Waveform buffer."
- slave_type: RAM
- number_of_slaves: g_nof_streams
+ - mm_port_name: RAM_DIAG_WG
+ mm_port_description: "Waveform buffer."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
@@ -68,12 +68,12 @@ peripherals:
- { name: g_data_w, value: 16 }
- { name: g_nof_data, value: 1024 }
- { name: g_use_in_sync, value: True }
- slave_ports:
+ mm_ports:
# MM port for mms_diag_data_buffer.vhd
- - slave_name: REG_DIAG_DB
- slave_description: "Data buffer status."
- slave_type: REG
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_DIAG_DB
+ mm_port_description: "Data buffer status."
+ mm_port_type: REG
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: sync_cnt
field_description: "Number of times the DB has been written."
@@ -84,10 +84,10 @@ peripherals:
access_mode: RO
address_offset: 0x4
# MM port for mms_diag_data_buffer.vhd
- - slave_name: RAM_DIAG_DB
- slave_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
- slave_type: RAM
- number_of_slaves: g_nof_streams
+ - mm_port_name: RAM_DIAG_DB
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: ""
@@ -95,228 +95,3 @@ peripherals:
address_offset: 0x0
number_of_fields: g_nof_data
-
-# - peripheral_name: block_gen
-# peripheral_description: "Block generator"
-# parameters:
-# - { name: g_nof_streams, value: 1 }
-# - { name: g_buf_dat_w , value: 32 }
-# - { name: g_buf_addr_w , value: 7 }
-# slave_ports:
-# # actual hdl name: reg_diag_bg
-# - slave_name: ctrl
-# slave_description: ""
-# slave_type: REG
-# fields:
-# - - field_name: Enable
-# field_description: "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
-# width: 2
-# address_offset: 0x0
-#
-# - - field_name: Samples_per_packet
-# field_description: "This REG specifies the number samples in a packet"
-# width: 16
-# address_offset: 0x4
-# reset_value: 256
-#
-# - - field_name: Blocks_per_sync
-# field_description: "This REG specifies the number of packets in a sync period"
-# width: 16
-# address_offset: 0x8
-# reset_value: 781250
-#
-# - - field_name: Gapsize
-# field_description: "This REG specifies the gap in number of clock cycles between two consecutive packets"
-# width: 16
-# address_offset: 0xc
-# reset_value: 80
-#
-# - - field_name: Mem_low_address
-# field_description: "This REG specifies the starting address for reading from the waveform memory"
-# width: 8
-# address_offset: 0x10
-#
-# - - field_name: Mem_high_address
-# field_description: "This REG specifies the last address to be read when from the waveform memory"
-# width: 8
-# address_offset: 0x14
-#
-# - - field_name: BSN_init_low
-# field_description: "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
-# address_offset: 0x18
-#
-# - - field_name: BSN_init_high
-# field_description: "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
-# address_offset: 0x1c
-#
-# # actual hdl name: ram_diag_bg
-# - slave_name: wave_data
-# slave_description: ""
-# slave_type: RAM
-# number_of_slaves: g_nof_streams
-# fields:
-# - - field_name: diag_bg
-# width: g_buf_dat_w
-# number_of_fields: 2**g_buf_addr_w
-# field_description: |
-# "Contains the Waveform data for the data-streams to be send"
-#
-# - peripheral_name: data_buffer
-# peripheral_description: |
-# "Peripheral diag_data_buffer
-#
-# Memory map RAM_DIAG_DATA_BUFFER
-#
-# If there is only one instance then the RAM name is RAM_DIAG_DATA_BUFFER, else it
-# gets an instanceName as post fix so RAM_DIAG_DATA_BUFFER_<instanceName|.
-#
-# The diag_data_buffer can store multiple streams in parallel. For example
-# 1024 data words for 16 streams the memory map becomes: 16
-#
-#
-# streamNr = 0:
-# +------------------------------------------------------------+
-# | byte 3 | byte 2 | byte 1 | byte 0 | wi |
-# |------------------------------------------------------------|
-# | data_0[31:0] | 0 |
-# | data_1[31:0] | 1 |
-# | ... | .. |
-# | data_1023[31:0] | 1023 |
-# +------------------------------------------------------------+
-#
-#
-# streamNr = 1:
-# +------------------------------------------------------------+
-# | byte 3 | byte 2 | byte 1 | byte 0 | wi |
-# |------------------------------------------------------------|
-# | data_0[31:0] | 1024 |
-# | data_1[31:0] | 1025 |
-# | ... | .. |
-# | data_1023[31:0] | 2047 |
-# +------------------------------------------------------------+
-#
-#
-# streamNr = 15:
-# +------------------------------------------------------------+
-# | byte 3 | byte 2 | byte 1 | byte 0 | wi |
-# |------------------------------------------------------------|
-# | data_0[31:0] | 15360 |
-# | data_1[31:0] | 15361 |
-# | ... | .. |
-# | data_1023[31:0] | 16383 |
-# +------------------------------------------------------------+
-#
-#
-# Remarks:
-# - The data buffer stores valid data samples until it is full.
-# - The data buffer fills again after an external sync pulse or after the
-# last data word was read via the MM bus, dependend on whether the generic
-# g_use_in_sync is TRUE or FALSE in diag_data_buffer.vhd.
-# - The actual data width depends on the generic g_data_w in
-# diag_data_buffer.vhd. The value of unused MSBits is undefined.
-#
-#
-# Memory map REG_DIAG_DATA_BUFFER (one for each stream like the RAM above)
-#
-# +----------------------------------------------------------------------------+
-# | byte 3 | byte 2 | byte 1 | byte 0 | wi |
-# |----------------------------------------------------------------------------|
-# | sync_cnt[31:0] | 0 RO (Version 0 and 1) |
-# | word_cnt[31:0] | 1 RO (Version 0 and 1) |
-# | R = valid_cnt[31:0] W = arm_enable | 2 RW (Version 1 only) |
-# | reg_sync_delay[31:0] | 3 RW (Version 1 only) |
-# | RESERVED | 4 (Version 1 only) |
-# | RESERVED | 5 (Version 1 only) |
-# | RESERVED | 6 (Version 1 only) |
-# | version[31:0] | 7 RO (Version 1 only) |
-# +----------------------------------------------------------------------------+
-#
-#
-# There are 3 access_modes of operation of the data_buffer.
-# Version 0 supports access_Mode 1 and access_Mode 2
-# Version 1 supports access_Mode 1, access_Mode 2 and access_Mode 3
-#
-# (1) NON-SYNC access_MODE: g_use_in_sync = FALSE
-# In this access_mode the first g_nof_data valid data input words are stored in the
-# data buffer. A new set of data will be stored when the last word is read
-# from the buffer via the MM interface.
-#
-# (2) SYNC-access_MODE: g_use_in_sync = TRUE and reg_sync_delay = 0
-# On every received sync pulse a number of g_nof_data valid words are written
-# to the databuffer. Data will be overwritten on every new sync pulse. It is
-# up to the user to read out the data in time in between two sync pulses
-#
-# (3) ARM-access_MODE: g_use_in_sync = TRUE and reg_sync_delay | 0
-# First the reg_sync_delay should be written with a desired delay value. Then
-# the arm REG must be written. After being armed the databuffer will wait
-# for the first sync pulse to arrive. When it has arrived it will wait for
-# reg_sync_delay valid cycles before g_nof_data valid words are written to the
-# databuffer. The data can then be read out through the MM interface. New data
-# will only be written if the databuffer is being armed again.
-#
-# - Sync_cnt contains the nof times the buffer (ST) has received a sync pulse
-# since the last MM read (cleared when the last data word from the buffer is
-# read);
-# - Word_cnt indicates the number of word currently (ST) written in the buffer.
-# Cleared on (ST) re-write of buffer.
-# - valid_cnt contains the number of valid cycles since the last sync pulse.
-# Cleared on every sync pulse.
-# - arm_enable. Write to this REG to arm the system. After the system is
-# armed the next syn pulse will truigger the acquisition of data.
-# - reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
-# before the data is written to the databuffer.
-# - version contains the version number of the databuffer peripheral."
-#
-# parameters:
-# - { name: g_nof_streams , value: 1 }
-# - { name: g_data_w , value: 32 }
-# - { name: g_buf_nof_data, value: 1024 }
-#
-# slave_ports:
-# # actual hdl name: reg_diag_data_buffer
-# - slave_name: status
-# slave_description: ""
-# slave_type: REG
-# fields:
-# - - field_name: Sync_cnt
-# field_description: |
-# "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
-# (cleared when the last data word from the buffer is read)"
-# access_mode: RO
-# address_offset: 0x0
-#
-# - - field_name: Word_cnt
-# field_description: |
-# "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
-# access_mode: RO
-# address_offset: 0x4
-#
-# - - field_name: Valid_cnt_arm_ena
-# field_description: |
-# "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
-# Arm_enable: Write to this REG to arm the system.
-# After the system is armed the next syn pulse will trigger the acquisition of data."
-# address_offset: 0x8
-#
-# - - field_name: Reg_sync_delay
-# field_description: |
-# "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
-# before the data is written to the databuffer."
-# address_offset: 0xc
-#
-# - - field_name: Version
-# field_description: "Version contains the version number of the databuffer peripheral."
-# access_mode: RO
-# address_offset: 0x1c
-#
-# # actual hdl name: ram_diag_data_buffer
-# - slave_name: data
-# slave_description: ""
-# slave_type: RAM
-# number_of_slaves: g_nof_streams
-# fields:
-# - - field_name: ram
-# width: g_data_w
-# number_of_fields: g_buf_nof_data
-# field_description: "Contains the data that is being captured."
-
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index d5c525b5dbf92d87bbaa4480bf373711d4fbf4e2..2d2b0570c3c965e81927fb4b479bb79817c3d709 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -8,20 +8,20 @@ hdl_library_description: "Data path (DP) peripherals for streaming data."
peripherals:
- peripheral_name: dpmm # pi_dpmm.py
peripheral_description: "DP to MM FIFO to provide memory mapped MM read access from Data Path (DP) streaming interface."
- slave_ports:
+ mm_ports:
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm_reg.vhd
- - slave_name: REG_DPMM_CTRL
- slave_type: REG
- slave_description: "DPMM = Monitor the DP to MM read FIFO."
+ - mm_port_name: REG_DPMM_CTRL
+ mm_port_type: REG
+ mm_port_description: "DPMM = Monitor the DP to MM read FIFO."
fields:
- - field_name: rd_usedw
field_description: "Number of words that can be read from the FIFO."
access_mode: RO
address_offset: 0x0
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
- - slave_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match slave_port_name in pi_dpmm.py
- slave_type: FIFO
- slave_description: "DPMM = read word from the DP to MM read FIFO"
+ - mm_port_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_dpmm.py
+ mm_port_type: FIFO
+ mm_port_description: "DPMM = read word from the DP to MM read FIFO"
fields:
- - field_name: rd_data
field_description: "Read data from the FIFO."
@@ -31,11 +31,11 @@ peripherals:
- peripheral_name: mmdp # pi_mmdp.py
peripheral_description: "MM to DP FIFO to provide memory mapped MM write access to Data Path (DP) streaming interface."
- slave_ports:
+ mm_ports:
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm_reg.vhd
- - slave_name: REG_MMDP_CTRL
- slave_type: REG
- slave_description: "MMDP = Monitor the MM to DP write FIFO."
+ - mm_port_name: REG_MMDP_CTRL
+ mm_port_type: REG
+ mm_port_description: "MMDP = Monitor the MM to DP write FIFO."
fields:
- - field_name: wr_usedw
field_description: "Number of words that are in the write FIFO."
@@ -47,9 +47,9 @@ peripherals:
access_mode: RO
address_offset: 0x4
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
- - slave_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match slave_port_name in pi_mmdp.py
- slave_type: FIFO
- slave_description: "MMDP = write word to the MM to DP write FIFO."
+ - mm_port_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_mmdp.py
+ mm_port_type: FIFO
+ mm_port_description: "MMDP = write word to the MM to DP write FIFO."
fields:
- - field_name: data
field_description: "Write data to the FIFO."
@@ -63,11 +63,11 @@ peripherals:
# Parameters of mms_dp_xonoff.vhd
- { name: g_nof_streams, value: 1 }
- { name: g_combine_streams, value: False }
- slave_ports:
+ mm_ports:
# MM port for mms_dp_xonoff.vhd
- - slave_name: REG_DP_XONOFF
- slave_type: REG
- slave_description: "When g_combine_streams = False then there is one enable bit per stream, else there is one enable bit for all streams."
+ - mm_port_name: REG_DP_XONOFF
+ mm_port_type: REG
+ mm_port_description: "When g_combine_streams = False then there is one enable bit per stream, else there is one enable bit for all streams."
fields:
- - field_name: enable_stream
field_description: |
@@ -86,12 +86,12 @@ peripherals:
- { name: g_nof_streams, value: 1 }
- { name: g_nof_words, value: 1024 }
- { name: g_data_w, value: 16 }
- slave_ports:
+ mm_ports:
# MM port for dp_shiftram.vhd
- - slave_name: REG_DP_SHIFTRAM
- slave_type: REG
- slave_description: ""
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_DP_SHIFTRAM
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: shift
field_description: "Fill level of the sample delay buffer in number of data samples."
@@ -105,11 +105,11 @@ peripherals:
parameters:
# Parameters of dp_bsn_source_reg.vhd
- { name: g_nof_block_per_sync, value: 20 }
- slave_ports:
+ mm_ports:
# MM port for dp_bsn_source_reg.vhd
- - slave_name: REG_DP_BSN_SOURCE
- slave_type: REG
- slave_description: ""
+ - mm_port_name: REG_DP_BSN_SOURCE
+ mm_port_type: REG
+ mm_port_description: ""
fields:
- - field_name: dp_on
field_description: |
@@ -151,11 +151,11 @@ peripherals:
- { name: g_nof_clk_per_sync, value: 200000000 }
- { name: g_block_size, value: 256 }
- { name: g_bsn_time_offset_w, value: 8 } # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
- slave_ports:
+ mm_ports:
# MM port for dp_bsn_source_reg_v2.vhd
- - slave_name: REG_DP_BSN_SOURCE_V2
- slave_type: REG
- slave_description: ""
+ - mm_port_name: REG_DP_BSN_SOURCE_V2
+ mm_port_type: REG
+ mm_port_description: ""
fields:
- - field_name: dp_on
field_description: |
@@ -197,11 +197,11 @@ peripherals:
- peripheral_name: dp_bsn_scheduler # pi_dp_bsn_scheduler.py
peripheral_description: "Schedule a trigger at a certain Block Sequence Number (BSN) instant."
- slave_ports:
+ mm_ports:
# MM port for dp_bsn_scheduler_reg.vhd
- - slave_name: REG_DP_BSN_SCHEDULER
- slave_type: REG
- slave_description: ""
+ - mm_port_name: REG_DP_BSN_SCHEDULER
+ mm_port_type: REG
+ mm_port_description: ""
fields:
#- - field_name: scheduled_bsn_lo
# field_description: "Write scheduled BSN lo, read current BSN lo. First access lo, then hi."
@@ -223,12 +223,12 @@ peripherals:
parameters:
# Parameters of mms_dp_bsn_monitor.vhd
- { name: g_nof_streams, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for dp_bsn_monitor_reg.vhd
- - slave_name: REG_DP_BSN_MONITOR
- slave_type: REG
- slave_description: ""
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_DP_BSN_MONITOR
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
@@ -297,12 +297,12 @@ peripherals:
parameters:
# Parameters of mms_dp_bsn_monitor_v2.vhd
- { name: g_nof_streams, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for dp_bsn_monitor_reg_v2.vhd
- - slave_name: REG_DP_BSN_MONITOR_V2
- slave_type: REG
- slave_description: ""
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_DP_BSN_MONITOR_V2
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
@@ -355,11 +355,11 @@ peripherals:
- peripheral_name: dp_selector # pi_dp_selector.py
peripheral_description: "Select between two data streams or between two arrays of data streams."
- slave_ports:
+ mm_ports:
# MM port for dp_selector_arr.vhd
- - slave_name: REG_DP_SELECTOR
- slave_type: REG
- slave_description: ""
+ - mm_port_name: REG_DP_SELECTOR
+ mm_port_type: REG
+ mm_port_description: ""
fields:
- - field_name: input_select
field_description: |
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
index 77d3417d71cb0ae94c0a84cd8a552e651bf87193..d74d0333fecd7b8a8243da6ffa36e6847b71716a 100644
--- a/libraries/base/reorder/reorder.peripheral.yaml
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -19,12 +19,12 @@ peripherals:
- { name: g_wb_factor, value: 1 }
- { name: g_nof_ch_in, value: 256 }
- { name: g_nof_ch_sel, value: 192 } # g_nof_ch_sel < g_nof_ch_in
- slave_ports:
+ mm_ports:
# MM port for reorder_col_wide.vhd / reorder_col.vhd
- - slave_name: RAM_SS_SS_WIDE
- slave_description: ""
- slave_type: RAM
- number_of_slaves: g_wb_factor
+ - mm_port_name: RAM_SS_SS_WIDE
+ mm_port_description: ""
+ mm_port_type: RAM
+ number_of_mm_ports: g_wb_factor
fields:
- - field_name: index
field_description: ""
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
index a9d61075825e5e97ac9f65cde3ff69016d75bec6..af75840c8d526380dcf05aeb4acab04678f8e6de 100644
--- a/libraries/dsp/filter/filter.peripheral.yaml
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -21,10 +21,10 @@ peripherals:
- { name: g_nof_taps, value: 8 }
- { name: g_nof_bands, value: 256 }
- { name: g_coef_dat_w, value: 16 }
- slave_ports:
+ mm_ports:
# MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
- - slave_name: RAM_FIL_COEFS
- slave_description: |
+ - mm_port_name: RAM_FIL_COEFS
+ mm_port_description: |
"The FIR filter coefficients are stored in blocks of g_nof_bands/g_wb_factor real
coefficients:
@@ -34,8 +34,8 @@ peripherals:
coefficients:
(int16)coefs[g_nof_taps][g_nof_bands]"
- slave_type: RAM
- number_of_slaves: g_wb_factor * g_nof_taps
+ mm_port_type: RAM
+ number_of_mm_ports: g_wb_factor * g_nof_taps
fields:
- - field_name: coef
field_description: "Real FIR filter coefficient"
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
index c8310c476acdf661fc6406027aaaad5ea77d6bb2..470bac8cdd0d81af50ff66cb9e581e19edb23db2 100644
--- a/libraries/dsp/si/si.peripheral.yaml
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -8,11 +8,11 @@ hdl_library_description: "Spectral Inversion (SI)"
peripherals:
- peripheral_name: si # pi_si.py
peripheral_description: "Spectral Inversion control."
- slave_ports:
+ mm_ports:
# MM port for si_arr.vhd
- - slave_name: REG_SI
- slave_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
- slave_type: REG
+ - mm_port_name: REG_SI
+ mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
+ mm_port_type: REG
fields:
- - field_name: enable
field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 346577aa51c26a934bcffeee521c76caddece2ac..c7c9f0c1f8718215ec467035485555bc0c4dac51 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -19,17 +19,17 @@ peripherals:
- { name: g_xst_enable, value: False } # False for auto powers, True for cross powers
- { name: g_stat_data_w, value: 64 } # statistics accumulator width in bits
- { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words
- slave_ports:
+ mm_ports:
# MM port for st_sst.vhd
- - slave_name: RAM_ST_SST
- slave_description: |
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
"The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
There are g_nof_instances parallel time multiplexed data streams.
The statistic power values have g_stat_data_w bits. The memory format is:
. g_xst_enable = False, for real powers : (uint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]
. g_xst_enable = True, for complex powers : (cuint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]"
- slave_type: RAM
- number_of_slaves: g_nof_instances
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
@@ -48,18 +48,18 @@ peripherals:
- { name: g_nof_stat, value: 1024 } # nof accumulators: N_sub * Q_fft = 512 * 2 = 1024
- { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
- slave_ports:
+ mm_ports:
# MM port for st_sst.vhd
- - slave_name: RAM_ST_SST
- slave_description: |
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
"The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
N_sub * Q_fft = 512 * 2 = 1024 real values as:
(uint64)SST[g_nof_instances]_[g_nof_stat] = (uint64)SST[S_pn/Q_fft]_[N_sub][Q_fft]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- slave_type: RAM
- number_of_slaves: g_nof_instances
+ mm_port_type: RAM
+ number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
@@ -79,17 +79,17 @@ peripherals:
- { name: g_nof_stat, value: 976 } # nof accumulators: S_sub_bf * N_pol_bf = 488 * 2 = 976
- { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
- slave_ports:
+ mm_ports:
# MM port for st_sst.vhd
- - slave_name: RAM_ST_SST
- slave_description: |
+ - mm_port_name: RAM_ST_SST
+ mm_port_description: |
"The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
(uint64)BST[g_nof_stat] = (uint64)BST[S_sub_bf][N_pol_bf]
where N_pol_bf = 2 and S_sub_bf = 488 are defined in sdp_pkg.vhd."
- slave_type: RAM
- number_of_slaves: 1
+ mm_port_type: RAM
+ number_of_mm_ports: 1
fields:
- - field_name: power
field_description: ""
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
index 403480b22f33ef9c1c4ce2b7d3de47612b93ded6..c364451f0f3de254af4406b59b016b9535923307 100644
--- a/libraries/io/aduh/aduh.peripheral.yaml
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -11,12 +11,12 @@ peripherals:
parameters:
# Parameters of mms_aduh_monitor_arr.vhd
- { name: g_nof_streams, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for mms_aduh_monitor_arr.vhd / aduh_monitor_reg.vhd
- - slave_name: REG_ADUH_MON
- slave_type: REG
- slave_description: "Sum of samples and sample powers during a sync interval."
- number_of_slaves: g_nof_streams
+ - mm_port_name: REG_ADUH_MON
+ mm_port_type: REG
+ mm_port_description: "Sum of samples and sample powers during a sync interval."
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: mean_sum_lo
field_description: "Mean sum[31:0] of samples during a sync interval."
@@ -44,12 +44,12 @@ peripherals:
- { name: g_nof_symbols_per_data, value: 1 }
- { name: g_buffer_nof_symbols, value: 512 }
- { name: g_buffer_use_sync, value: True }
- slave_ports:
+ mm_port_ports:
# MM port for mms_aduh_monitor_arr.vhd
- - slave_name: RAM_ADUH_MON
- slave_type: RAM
- slave_description: "Data buffer memory, gets filled after the sync when g_buffer_use_sync = True, else after the last word was read."
- number_of_slaves: g_nof_streams
+ - mm_port_name: RAM_ADUH_MON
+ mm_port_type: RAM
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_buffer_use_sync = True, else after the last word was read."
+ number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: ""
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index 892dc8bcbc896fc8649b915b4f5ea6ba75e3b592..2026d2bdf28c1bf9ae67ec48f00edf13fb94b0f5 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -19,11 +19,11 @@ peripherals:
# parameters of mms_epcs.vhd / epcs_reg.vhd
- {name: "g_epcs_addr_w", value: 24}
- slave_ports:
+ mm_ports:
# MM port for epcs_reg.vhd
- - slave_name: REG_EPCS # pi_epcs.py
- slave_type: REG
- slave_description: "Handle the read, erase and write of the flash memory chip."
+ - mm_port_name: REG_EPCS # pi_epcs.py
+ mm_port_type: REG
+ mm_port_description: "Handle the read, erase and write of the flash memory chip."
fields:
- - field_name: addr
field_description: "Address to write to or read from."
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 5290f2b942389caadb9f8379f3cadfd3f942b783..5593e60c884be463d06bf6bce75c1443c9f71e7c 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -14,11 +14,11 @@ peripherals:
[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
[2] https://git.astron.nl/desp/hdl/-/blob/master/libraries/io/eth/doc/ASTRON_RP_396_eth_1gb_module.pdf"
- slave_ports:
+ mm_ports:
# MM port for registers in the TSE IP [1]
- - slave_name: AVS_ETH_0_TSE
- slave_type: REG
- slave_description: "Registers in the TSE IP [1], handled by the microprocessor."
+ - mm_port_name: AVS_ETH_0_TSE
+ mm_port_type: REG
+ mm_port_description: "Registers in the TSE IP [1], handled by the microprocessor."
fields:
- - field_name: status
field_description: ""
@@ -27,9 +27,9 @@ peripherals:
number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- - slave_name: AVS_ETH_0_REG
- slave_type: REG
- slave_description: "Registers in the ETH module [2], handled by the microprocessor."
+ - mm_port_name: AVS_ETH_0_REG
+ mm_port_type: REG
+ mm_port_description: "Registers in the ETH module [2], handled by the microprocessor."
fields:
- - field_name: status
field_description: ""
@@ -38,9 +38,9 @@ peripherals:
number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd
# MM port for ETH packet packet buffers in eth.vhd
- - slave_name: AVS_ETH_0_RAM
- slave_type: RAM
- slave_description: |
+ - mm_port_name: AVS_ETH_0_RAM
+ mm_port_type: RAM
+ mm_port_description: |
"Buffer RAM for request packets (Rx) and response packets (Tx) via 1GbE, used by the microprocessor
to receive and transmit packets via the ETH module."
fields:
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index ea93bed46fa0b98954cf8603d0915b3618978938..c70b59c3b9abca3930868c04f33f630373978632 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -23,13 +23,13 @@ peripherals:
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for reg_mac_mosi = mac_mosi in ip_arria10_e1sg_eth_10g.vhd
# Use nw_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses
- - slave_name: REG_NW_10GBE_MAC
- slave_type: REG
- slave_description: "MAC registers"
- number_of_slaves: g_nof_macs
+ - mm_port_name: REG_NW_10GBE_MAC
+ mm_port_type: REG
+ mm_port_description: "MAC registers"
+ number_of_mm_ports: g_nof_macs
fields:
- - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
@@ -152,12 +152,12 @@ peripherals:
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
- slave_ports:
+ mm_ports:
# MM port for reg_eth10g_mosi in ip_arria10_e1sg_eth_10g.vhd / common_reg_r_w_dc.vhd
- - slave_name: REG_NW_10GBE_ETH10G
- slave_type: REG
- slave_description: ""
- number_of_slaves: g_nof_macs
+ - mm_port_name: REG_NW_10GBE_ETH10G
+ mm_port_type: REG
+ mm_port_description: ""
+ number_of_mm_ports: g_nof_macs
fields:
- - field_name: tx_snk_out_xon
field_description: ""
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index 52c7a2d891d15c4c4ff4b8899fe6389e01c4c7bc..e732647b7504398f8be33e9bb3c96763b2d1396b 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -18,11 +18,11 @@ peripherals:
- { name: g_cross_clock_domain, value: TRUE }
- { name: g_st_clk_freq, value: 200 * 10**6 }
- slave_ports:
+ mm_ports:
# MM port for ppsh_reg.vhd
- - slave_name: PIO_PPS # pi_ppsh.py and in QSYS system.h
- slave_type: REG
- slave_description: "Monitor and control PPS input."
+ - mm_port_name: PIO_PPS # pi_ppsh.py and in QSYS system.h
+ mm_port_type: REG
+ mm_port_description: "Monitor and control PPS input."
dual_clock: g_cross_clock_domain
fields:
- - field_name: capture_cnt
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index 3c332f25cd26b382d873adeddac68a01c02163ec..eb13be5b392fb259f245e132111fe583b06b5837 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -16,11 +16,11 @@ peripherals:
# parameters of remu_reg.vhd
- { name: g_data_w, value: 24 }
- slave_ports:
+ mm_ports:
# MM port for remu_reg.vhd
- - slave_name: REG_REMU # pi_remu.py and in QSYS system.h
- slave_type: REG
- slave_description: "Remote update."
+ - mm_port_name: REG_REMU # pi_remu.py and in QSYS system.h
+ mm_port_type: REG
+ mm_port_description: "Remote update."
fields:
- - field_name: reconfigure
field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."