From 6f67251d42ec0044b02c8c3b0d87e46a90b72745 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 24 Oct 2022 17:50:44 +0200
Subject: [PATCH] Add p_mm stimuli.
---
libraries/io/eth/tb/vhdl/tb_eth_tester.vhd | 106 ++++++++++++++++++---
1 file changed, 91 insertions(+), 15 deletions(-)
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 0966b345eb..446a40361b 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -20,23 +20,40 @@
-- AUthor: E. Kooistra
-- Purpose: Test bench for eth_tester
-- Description: See detailed design in [1]
---
+-- The g_nof_streams >= 1 are tested independently.
+-- Usage:
+-- > as 8
+-- > run -a
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, dp_lib, diag_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-
+USE dp_lib.dp_components_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.eth_tester_pkg.ALL;
+USE work.tb_eth_tester_pkg.ALL;
ENTITY tb_eth_tester IS
GENERIC (
- g_nof_streams : NATURAL := 1
+ g_nof_streams : NATURAL := 1;
+
+ -- sl: enable
+ -- sl: enable_sync
+ -- nat: samples_per_packet
+ -- nat: blocks_per_sync
+ -- nat: gapsize
+ -- nat: mem_low_adrs
+ -- nat: mem_high_adrs
+ -- nat: bsn_init
+ g_bg_ctrl_int : t_diag_block_gen_integer := ('1', '1', 50, 20, 100, 0, 30, 0)
);
END tb_eth_tester;
@@ -46,18 +63,24 @@ ARCHITECTURE tb OF tb_eth_tester IS
CONSTANT mm_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT st_clk_period : TIME := 5 ns; -- 200 MHz
+ -- Use same bg_ctrl for all streams, this provides sufficient test coverage
+ CONSTANT c_bg_ctrl_int_arr : t_diag_block_gen_integer_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => g_bg_ctrl_int);
+
+ -- Use sim default src MAC, IP, UDP port from eth_tester_pkg.vhd and based on c_gn_index
+ CONSTANT c_gn_index : NATURAL := 17; -- global node index
+ CONSTANT c_gn_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16 & func_eth_tester_gn_index_to_mac_15_0(c_gn_index);
+ CONSTANT c_gn_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16 & func_eth_tester_gn_index_to_ip_15_0(c_gn_index);
+ CONSTANT c_gn_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8 & TO_UVEC(c_gn_index, 8);
+
-- Clocks and reset
SIGNAL mm_rst : STD_LOGIC := '1';
- SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC := '1';
SIGNAL st_rst : STD_LOGIC := '1';
- SIGNAL st_clk : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC := '1';
SIGNAL st_pps : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
-- ETH UDP data path interface
- SIGNAL eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
-
SIGNAL tx_udp_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL tx_udp_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL rx_udp_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
@@ -78,10 +101,63 @@ ARCHITECTURE tb OF tb_eth_tester IS
SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
+ SIGNAL tx_count : NATURAL;
+ SIGNAL rx_count : NATURAL;
+
BEGIN
- mm_clk <= NOT mm_clk AFTER mm_clk_period/2;
- st_clk <= NOT st_clk AFTER st_clk_period/2;
+ mm_clk <= (NOT mm_clk) OR tb_end AFTER mm_clk_period/2;
+ st_clk <= (NOT st_clk) OR tb_end AFTER st_clk_period/2;
+ mm_rst <= '1', '0' AFTER mm_clk_period*5;
+ st_rst <= '1', '0' AFTER st_clk_period*5;
+
+ gen_mm : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE
+ p_mm : PROCESS
+ VARIABLE v_offset : NATURAL;
+ BEGIN
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Stimuli
+ v_offset := I * c_diag_bg_reg_nof_dat;
+ proc_mem_mm_bus_wr(v_offset + 1, c_bg_ctrl_int_arr(I).samples_per_packet, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.nof samples per block
+ proc_mem_mm_bus_wr(v_offset + 2, c_bg_ctrl_int_arr(I).blocks_per_sync, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.nof blocks per sync
+ proc_mem_mm_bus_wr(v_offset + 3, c_bg_ctrl_int_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.gapsize
+ proc_mem_mm_bus_wr(v_offset + 4, c_bg_ctrl_int_arr(I).mem_low_adrs, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.mem low address
+ proc_mem_mm_bus_wr(v_offset + 5, c_bg_ctrl_int_arr(I).mem_high_adrs, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.mem high address
+ proc_mem_mm_bus_wr(v_offset + 6, c_bg_ctrl_int_arr(I).bsn_init, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.lower part of the initial bsn
+ proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi); -- Set bg_ctrl.higher part of the initial bsn
+ -- Enable the BG at st_pps pulse.
+ proc_mem_mm_bus_wr(v_offset + 0, 3, mm_clk, reg_bg_ctrl_copi);
+ proc_common_wait_some_cycles(mm_clk, 10);
+ -- Issue an st_pps pulse to start the enabled BG
+ proc_common_gen_pulse(st_clk, st_pps);
+
+ -- Run test
+ proc_common_wait_some_cycles(st_clk, 1000);
+
+ -- Disable the BG
+ proc_mem_mm_bus_wr(v_offset + 0, 0, mm_clk, reg_bg_ctrl_copi);
+ proc_common_wait_some_cycles(mm_clk, 100);
+
+ -- Verification: total nof Tx packets = total nof Rx packets
+ -- . read low part, ignore high part (= 0)
+ v_offset := I * c_dp_strobe_total_count_reg_adr_span;
+ proc_mem_mm_bus_rd(v_offset + 0, mm_clk, reg_strobe_total_count_tx_cipo, reg_strobe_total_count_tx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ tx_count <= TO_UINT(reg_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(v_offset + 0, mm_clk, reg_strobe_total_count_rx_cipo, reg_strobe_total_count_rx_copi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rx_count <= TO_UINT(reg_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT tx_count = rx_count REPORT "Wrong total block count, Tx count(" & NATURAL'IMAGE(tx_count) & ") /= "
+ & NATURAL'IMAGE(rx_count) & " = Rx count" SEVERITY ERROR;
+
+ -- End of test
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+ END GENERATE;
-- Wire Tx to Rx
rx_udp_sosi_arr <= tx_udp_sosi_arr;
@@ -99,9 +175,9 @@ BEGIN
st_pps => st_pps,
-- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
+ eth_src_mac => c_gn_eth_src_mac,
+ ip_src_addr => c_gn_ip_src_addr,
+ udp_src_port => c_gn_udp_src_port,
tx_udp_sosi_arr => tx_udp_sosi_arr,
tx_udp_siso_arr => tx_udp_siso_arr,
--
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