From 6f61c32677b0e8bc381f25d03b7c9f93b2bf8f14 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Sun, 18 Oct 2015 13:04:46 +0000
Subject: [PATCH] Added and pass on g_technology.
---
.../base/diag/src/vhdl/diag_data_buffer.vhd | 17 +++++++++-------
libraries/base/diag/src/vhdl/diag_wg.vhd | 4 +++-
.../base/diag/src/vhdl/diag_wg_wideband.vhd | 6 +++++-
.../base/diag/src/vhdl/mms_diag_block_gen.vhd | 6 +++++-
.../diag/src/vhdl/mms_diag_data_buffer.vhd | 5 ++++-
.../diag/src/vhdl/mms_diag_wg_wideband.vhd | 5 ++++-
.../diagnostics/src/vhdl/mm_rx_logger.vhd | 6 +++++-
.../diagnostics/src/vhdl/mm_tx_framer.vhd | 5 ++++-
.../base/reorder/src/vhdl/reorder_col.vhd | 18 ++++++++++-------
.../reorder/src/vhdl/reorder_col_wide.vhd | 17 +++++++++-------
.../base/reorder/src/vhdl/reorder_matrix.vhd | 19 +++++++++++-------
.../base/reorder/src/vhdl/reorder_row.vhd | 17 +++++++++-------
.../reorder/src/vhdl/reorder_transpose.vhd | 7 +++++--
libraries/base/ss/src/vhdl/ss.vhd | 18 ++++++++++-------
libraries/base/ss/src/vhdl/ss_parallel.vhd | 19 +++++++++++-------
libraries/base/ss/src/vhdl/ss_reorder.vhd | 17 +++++++++-------
libraries/base/ss/src/vhdl/ss_wide.vhd | 17 +++++++++-------
.../base/uth/src/vhdl/uth_terminal_bidir.vhd | 6 +++++-
.../base/uth/src/vhdl/uth_terminal_rx.vhd | 20 +++++++++++--------
.../base/uth/src/vhdl/uth_terminal_tx.vhd | 17 +++++++++-------
20 files changed, 158 insertions(+), 88 deletions(-)
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index 90c8091662..6b98600c5b 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE work.diag_pkg.ALL;
-
-- Purpose : Capture a block of streaming data for analysis via MM access
-- Description :
-- The first g_nof_data valid streaming data input words are stored in the
@@ -50,8 +43,17 @@ USE work.diag_pkg.ALL;
-- power of 2 multiple of 32b the user can enforce using splitting the data
-- a c_word_w parts.
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY diag_data_buffer IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 32;
g_nof_data : NATURAL := 1024;
g_use_in_sync : BOOLEAN := FALSE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
@@ -191,6 +193,7 @@ BEGIN
u_buf : ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP (
+ g_technology => g_technology,
g_ram_a => c_buf_mm,
g_ram_b => c_buf_st,
g_init_file => "UNUSED"
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 49969fea16..30cc28f317 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -21,14 +21,16 @@
-- Based on diag_waveproc from LOFAR
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY diag_wg IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_buf_dat_w : NATURAL := 18; -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
g_buf_addr_w : NATURAL := 11; -- Waveform buffer size 2**g_buf_addr_w nof samples
-- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 61e77a2ab4..ed54b89182 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -24,15 +24,17 @@
-- Remarks:
-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg.
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY diag_wg_wideband IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
g_buf_dir : STRING := "../../../src/data/";
@@ -109,6 +111,7 @@ BEGIN
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_buf,
g_init_file => c_buf_file
)
@@ -134,6 +137,7 @@ BEGIN
-- Waveform generator
u_wg : ENTITY work.diag_wg
GENERIC MAP (
+ g_technology => g_technology,
g_buf_dat_w => g_buf_dat_w,
g_buf_addr_w => g_buf_addr_w,
g_rate_factor => g_wideband_factor,
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 1a6857d425..051b6cbe9f 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -93,16 +93,18 @@
-- . A nice new feature would be to support a BG burst of N blocks.
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_diag_block_gen IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Generate configurations
g_use_usr_input : BOOLEAN := FALSE;
g_use_bg : BOOLEAN := TRUE;
@@ -241,6 +243,7 @@ BEGIN
gen_buffer_ram : IF g_use_bg_buffer_ram=TRUE GENERATE
u_buffer_ram : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_buf,
-- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & NATURAL'IMAGE(g_file_index_arr(I)) & c_post_buf_file)
@@ -336,6 +339,7 @@ BEGIN
u_dp_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
+ g_technology => g_technology,
-- MUX
g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
g_nof_input => c_mux_nof_input, -- >= 1
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index e6d4af85a1..2c3c6fbcc0 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -57,16 +57,18 @@
-- detects an error. By delaying the trigger somewhat it the DB can then
-- capture some data before and after the trigger event.
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_diag_data_buffer IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Generate configurations
g_use_db : BOOLEAN := TRUE;
g_use_rx_seq : BOOLEAN := FALSE;
@@ -163,6 +165,7 @@ BEGIN
u_diag_data_buffer : ENTITY work.diag_data_buffer
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_nof_data => g_buf_nof_data,
g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index a83c1efefd..89b3fc07fe 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -26,15 +26,17 @@
-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg. Hence
-- no need to make a mms_diag_wg.vhd.
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.diag_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_diag_wg_wideband IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_cross_clock_domain : BOOLEAN := TRUE;
@@ -102,6 +104,7 @@ BEGIN
u_wg_wideband : ENTITY work.diag_wg_wideband
GENERIC MAP (
+ g_technology => g_technology,
-- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
g_buf_dir => g_buf_dir,
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 5a5dc379b1..0d994f17fe 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -20,16 +20,18 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, diag_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, diag_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mm_rx_logger IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_dat_w : NATURAL;
g_fifo_wr_depth : NATURAL := 128 -- Only put powers of 2 here.
);
@@ -144,6 +146,7 @@ BEGIN
-- that to flush the FIFO on the src side.
u_data_log_fifo : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_dat_w,
g_use_ctrl => FALSE,
g_fifo_size => g_fifo_wr_depth
@@ -188,6 +191,7 @@ BEGIN
u_data_dpmm_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => g_dat_w,
g_rd_data_w => c_word_w,
g_use_ctrl => FALSE,
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index de0163d8ec..0fd8c8587d 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -20,15 +20,17 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mm_tx_framer IS
GENERIC(
+ g_technology : NATURAL := c_tech_select_default;
g_dat_out_w : NATURAL;
g_rd_fifo_depth : NATURAL := 128
);
@@ -92,6 +94,7 @@ BEGIN
u_mm_to_dp_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => c_word_w,
g_rd_data_w => g_dat_out_w,
g_use_ctrl => FALSE,
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index f280a7d5ac..8755636c57 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Reorder packet
-- Description:
-- Select g_nof_ch_sel complex samples from an input block of g_nof_ch_in
@@ -57,8 +50,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- is assumed that the reorder_col source is always fast enough. The reorder_col sink could
-- support the input_siso signal, e.g. based on store_done and retrieve_done.
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY reorder_col IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_output_rl_adapter : BOOLEAN := FALSE; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
g_dsp_data_w : NATURAL := 18;
g_nof_ch_in : NATURAL := 512;
@@ -165,6 +167,7 @@ BEGIN
u_store_buf : ENTITY common_lib.common_paged_ram_r_w
GENERIC MAP (
+ g_technology => g_technology,
g_str => "use_adr",
g_data_w => c_store_buf.dat_w,
g_nof_pages => c_data_nof_pages,
@@ -189,6 +192,7 @@ BEGIN
u_select_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_select_buf,
g_init_file => g_select_file_name
)
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index e011101e24..90ae619edf 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Select and/or reorder data on multiple streams.
--
-- Description:
@@ -38,8 +31,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY reorder_col_wide IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_wb_factor : NATURAL := 4;
g_dsp_data_w : NATURAL := 18;
g_nof_ch_in : NATURAL := 256;
@@ -100,6 +102,7 @@ BEGIN
gen_ss_singles : FOR I IN 0 TO g_wb_factor-1 GENERATE
u_single_ss : ENTITY work.reorder_col
GENERIC MAP (
+ g_technology => g_technology,
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => c_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel,
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 5457aa8e80..4f8a4f764f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Select a subset of the input data. Reorder the input data. Redistribute data over multiple outputs.
--
-- Description: This unit creates a parallel set of output streams where each
@@ -53,8 +46,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY reorder_matrix IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_nof_inputs : NATURAL := 24;
g_nof_internals : NATURAL := 64;
g_nof_outputs : NATURAL := 64;
@@ -116,6 +118,7 @@ BEGIN
-----------------------------------------------------------------------------
u_input_reorder : ENTITY work.reorder_row
GENERIC MAP(
+ g_technology => g_technology,
g_nof_inputs => g_nof_inputs,
g_nof_outputs => g_nof_internals,
g_dsp_data_w => g_dsp_data_w,
@@ -145,6 +148,7 @@ BEGIN
-----------------------------------------------------------------------------
u_ss_wide : ENTITY work.reorder_col_wide
GENERIC MAP (
+ g_technology => g_technology,
g_wb_factor => g_nof_internals,
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => g_frame_size_in,
@@ -172,6 +176,7 @@ BEGIN
-----------------------------------------------------------------------------
u_output_reorder : ENTITY work.reorder_row
GENERIC MAP(
+ g_technology => g_technology,
g_nof_inputs => g_nof_internals,
g_nof_outputs => g_nof_outputs,
g_dsp_data_w => g_dsp_data_w,
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index 917296eac5..2a23f5a48b 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Subband Select Reordering.
--
-- Description: For every clock cycle within a frame a different output
@@ -38,8 +31,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY reorder_row IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_dsp_data_w : NATURAL := 16;
g_frame_size : NATURAL := 256;
g_nof_inputs : NATURAL := 8;
@@ -152,6 +154,7 @@ BEGIN
---------------------------------------------------------------
u_select_buf : ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP(
+ g_technology => g_technology,
g_ram_a => c_select_buf_mm,
g_ram_b => c_select_buf_dp,
g_init_file => g_ram_init_file
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index f16e931abf..f205bb92fa 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -63,17 +63,18 @@
--
-- Remarks:
-
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.reorder_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY reorder_transpose IS
GENERIC(
+ g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL := 4;
g_in_dat_w : NATURAL := 8;
g_frame_size_in : NATURAL := 256;
@@ -221,6 +222,7 @@ BEGIN
u_single_ss : ENTITY work.reorder_col
GENERIC MAP (
+ g_technology => g_technology,
g_dsp_data_w => c_data_w_pre,
g_nof_ch_in => c_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel,
@@ -288,6 +290,7 @@ BEGIN
u_sync_bsn_fifo : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 2 words deep.
g_reset => FALSE,
g_init => FALSE,
diff --git a/libraries/base/ss/src/vhdl/ss.vhd b/libraries/base/ss/src/vhdl/ss.vhd
index 17e7f250ad..f9d70c483d 100644
--- a/libraries/base/ss/src/vhdl/ss.vhd
+++ b/libraries/base/ss/src/vhdl/ss.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Subband select
-- Description:
-- Select g_nof_ch_sel complex samples from an input block of g_nof_ch_in
@@ -57,8 +50,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- is assumed that the SS source is always fast enough. The SS sink could
-- support the input_siso signal, e.g. based on store_done and retrieve_done.
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY ss IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_use_output_rl_adapter : BOOLEAN := FALSE; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
g_dsp_data_w : NATURAL := 18;
g_nof_ch_in : NATURAL := 512;
@@ -165,6 +167,7 @@ BEGIN
u_store_buf : ENTITY common_lib.common_paged_ram_r_w
GENERIC MAP (
+ g_technology => g_technology,
g_str => "use_adr",
g_data_w => c_store_buf.dat_w,
g_nof_pages => c_data_nof_pages,
@@ -189,6 +192,7 @@ BEGIN
u_select_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_select_buf,
g_init_file => g_select_file_name
)
diff --git a/libraries/base/ss/src/vhdl/ss_parallel.vhd b/libraries/base/ss/src/vhdl/ss_parallel.vhd
index ffab5c993e..990a35c7ef 100644
--- a/libraries/base/ss/src/vhdl/ss_parallel.vhd
+++ b/libraries/base/ss/src/vhdl/ss_parallel.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Select a subset of the input data. Reorder the input data. Redistribute data over multiple outputs.
--
-- Description: This unit creates a parallel set of output streams where each
@@ -53,8 +46,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY ss_parallel IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_nof_inputs : NATURAL := 8;
g_nof_internals : NATURAL := 16;
g_nof_outputs : NATURAL := 16;
@@ -116,6 +118,7 @@ BEGIN
-----------------------------------------------------------------------------
u_input_reorder : ENTITY work.ss_reorder
GENERIC MAP(
+ g_technology => g_technology,
g_nof_inputs => g_nof_inputs,
g_nof_outputs => g_nof_internals,
g_dsp_data_w => g_dsp_data_w,
@@ -145,6 +148,7 @@ BEGIN
-----------------------------------------------------------------------------
u_ss_wide : ENTITY work.ss_wide
GENERIC MAP (
+ g_technology => g_technology,
g_wb_factor => g_nof_internals,
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => g_frame_size_in,
@@ -172,6 +176,7 @@ BEGIN
-----------------------------------------------------------------------------
u_output_reorder : ENTITY work.ss_reorder
GENERIC MAP(
+ g_technology => g_technology,
g_nof_inputs => g_nof_internals,
g_nof_outputs => g_nof_outputs,
g_dsp_data_w => g_dsp_data_w,
diff --git a/libraries/base/ss/src/vhdl/ss_reorder.vhd b/libraries/base/ss/src/vhdl/ss_reorder.vhd
index ecbf0fc6ca..65868b94c9 100644
--- a/libraries/base/ss/src/vhdl/ss_reorder.vhd
+++ b/libraries/base/ss/src/vhdl/ss_reorder.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Subband Select Reordering.
--
-- Description: For every clock cycle within a frame a different output
@@ -38,8 +31,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY ss_reorder IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_dsp_data_w : NATURAL := 16;
g_frame_size : NATURAL := 256;
g_nof_inputs : NATURAL := 8;
@@ -151,6 +153,7 @@ BEGIN
---------------------------------------------------------------
u_select_buf : ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP(
+ g_technology => g_technology,
g_ram_a => c_select_buf_mm,
g_ram_b => c_select_buf_dp,
g_init_file => g_ram_init_file
diff --git a/libraries/base/ss/src/vhdl/ss_wide.vhd b/libraries/base/ss/src/vhdl/ss_wide.vhd
index 263ea831b6..f9b23dee97 100644
--- a/libraries/base/ss/src/vhdl/ss_wide.vhd
+++ b/libraries/base/ss/src/vhdl/ss_wide.vhd
@@ -19,13 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-- Purpose: Select and/or reorder data on multiple streams.
--
-- Description:
@@ -38,8 +31,17 @@ USE dp_lib.dp_stream_pkg.ALL;
-- Remarks:
--
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY ss_wide IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_wb_factor : NATURAL := 4;
g_dsp_data_w : NATURAL := 18;
g_nof_ch_in : NATURAL := 256;
@@ -100,6 +102,7 @@ BEGIN
gen_ss_singles : FOR I IN 0 TO g_wb_factor-1 GENERATE
u_single_ss : ENTITY work.ss
GENERIC MAP (
+ g_technology => g_technology,
g_dsp_data_w => g_dsp_data_w,
g_nof_ch_in => c_nof_ch_in,
g_nof_ch_sel => c_nof_ch_sel,
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
index 5234411a43..6222e1a790 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
@@ -29,16 +29,18 @@
-- application needs so.
-LIBRARY IEEE, common_lib, dp_lib, uth_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, uth_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.dp_packet_pkg.ALL;
USE work.uth_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY uth_terminal_bidir IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- User
g_usr_nof_streams : NATURAL := 4; -- number of user streams per bus
g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
@@ -124,6 +126,7 @@ BEGIN
gen_tx : IF g_use_tx=TRUE GENERATE
u_uth_terminal_tx : ENTITY work.uth_terminal_tx
GENERIC MAP (
+ g_technology => g_technology,
-- Terminal IO
g_nof_input => g_usr_nof_streams,
g_nof_output => g_phy_nof_serial,
@@ -171,6 +174,7 @@ BEGIN
gen_rx : IF g_use_rx=TRUE GENERATE
u_uth_terminal_rx : ENTITY work.uth_terminal_rx
GENERIC MAP (
+ g_technology => g_technology,
-- Terminal IO
g_nof_input => g_phy_nof_serial,
g_nof_output => g_usr_nof_streams,
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
index 3d529c7f57..6349411858 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
@@ -19,14 +19,6 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE work.uth_pkg.ALL;
-
-
-- Purpose: Receive UTH frames from n = g_nof_input input streams via m =
-- g_nof_output SOSI data output streams.
-- Description:
@@ -47,8 +39,17 @@ USE work.uth_pkg.ALL;
-- . The g_use_uth_err can be used to insert the UTH rx error bit (based on
-- the CRC) in the original DP packet err field at bit index g_uth_err_bi.
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.uth_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
ENTITY uth_terminal_rx IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Terminal IO
g_nof_input : NATURAL := 4; -- >= 1
g_nof_output : NATURAL := 3; -- >= 1
@@ -128,6 +129,7 @@ BEGIN
-- Input FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_packet_data_w,
g_fifo_fill => g_input_fifo_fill,
g_fifo_af_margin => g_input_fifo_af_margin,
@@ -184,6 +186,7 @@ BEGIN
u_distribute : ENTITY dp_lib.dp_distribute
GENERIC MAP (
+ g_technology => g_technology,
-- Distribution IO
g_tx => FALSE,
g_nof_input => g_nof_input,
@@ -223,6 +226,7 @@ BEGIN
-- However if g_use_uth_err=TRUE then the Uthernet CRC error status is passed on via the sosi error field using 1 bit.
u_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_packet_data_w,
g_error_w => c_uth_crc_err_w, -- = 1, one bit CRC error status from uth_rx
g_use_error => g_use_uth_err,
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
index b2e82a193b..c2c49bdca6 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
@@ -19,13 +19,6 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-
-- Purpose: Transmit SOSI data from n input streams via m UTH output streams.
-- Description:
-- Data flow:
@@ -45,9 +38,16 @@ USE dp_lib.dp_stream_pkg.ALL;
-- By filling the FIFO sufficiently it can be ensured that the UTH packets
-- are then output without data not valid gaps during the packet.
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY uth_terminal_tx IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
-- Terminal IO
g_nof_input : NATURAL := 4; -- >= 1
g_nof_output : NATURAL := 3; -- >= 1
@@ -139,6 +139,7 @@ BEGIN
gen_fifo : IF g_input_use_fifo=TRUE GENERATE
u_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_bsn_w => g_input_bsn_w,
g_empty_w => g_input_empty_w,
@@ -195,6 +196,7 @@ BEGIN
------------------------------------------------------------------------------
u_distribute : ENTITY dp_lib.dp_distribute
GENERIC MAP (
+ g_technology => g_technology,
-- Distribution IO
g_tx => TRUE,
g_nof_input => g_nof_input,
@@ -256,6 +258,7 @@ BEGIN
-- Output FIFO passes DP/Uthernet packets, so the sosi control fields (sync, bsn, empty, channel and error) are encoded in the packet data
u_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_packet_data_w,
g_fifo_fill => g_output_fifo_fill,
g_fifo_size => g_output_fifo_size,
--
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