diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
index e2386ac9f6c28921ff25b2c4c35c85182638d725..d4cdb1bed7da2be475ed2080c23c8bfc9f534897 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>2048</ipxact:value>
+ <ipxact:value>32768</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>8</ipxact:right>
+ <ipxact:right>12</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>8</ipxact:right>
+ <ipxact:right>12</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>9</ipxact:value>
+ <ipxact:value>13</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1532,4 +1532,4 @@
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
+</ipxact:component>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
index edcedddfd7a88e4048ddd50ff3803d55483a58c2..df43c598c332adeb7d603cb4ad1770ac91f39c9f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
@@ -22,7 +22,7 @@
{
datum baseAddress
{
- value = "802816";
+ value = "835584";
type = "String";
}
}
@@ -62,7 +62,7 @@
{
datum baseAddress
{
- value = "806912";
+ value = "14336";
type = "String";
}
}
@@ -78,7 +78,7 @@
{
datum baseAddress
{
- value = "786432";
+ value = "819200";
type = "String";
}
}
@@ -197,7 +197,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "786432";
type = "String";
}
}
@@ -245,7 +245,7 @@
{
datum baseAddress
{
- value = "14336";
+ value = "32768";
type = "String";
}
}
@@ -341,7 +341,7 @@
{
datum baseAddress
{
- value = "49152";
+ value = "802816";
type = "String";
}
}
@@ -4894,36 +4894,39 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>clk_in</name>
+ <name>clk</name>
<type>clock</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>in_clk</name>
+ <name>clk_out</name>
<role>clk</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
<entry>
<key>externallyDriven</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
@@ -4932,13 +4935,13 @@
</parameters>
</interface>
<interface>
- <name>clk_in_reset</name>
- <type>reset</type>
+ <name>clk_in</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>in_clk</name>
+ <role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4949,59 +4952,56 @@
<assignmentValueMap>
<entry>
<key>qsys.ui.export_name</key>
- <value>reset</value>
+ <value>clk</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>100000000</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
+ <name>clk_in_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>100000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
@@ -5704,7 +5704,7 @@
<name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -6264,7 +6264,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_dp_shiftram.mem' start='0x3040' end='0x3060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x30C0' end='0x30D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30E8' end='0x30F0' datawidth='32' /><slave name='pio_pps.mem' start='0x30F0' end='0x30F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30F8' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x8000' end='0xC000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0xC000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x80000' end='0xC0000' datawidth='32' /><slave name='jesd204b.mem' start='0xC0000' end='0xC4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0xC4000' end='0xC5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xC5000' end='0xC5800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_dp_shiftram.mem' start='0x3040' end='0x3060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x30C0' end='0x30D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30E8' end='0x30F0' datawidth='32' /><slave name='pio_pps.mem' start='0x30F0' end='0x30F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30F8' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x80000' end='0xC0000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0xC0000' end='0xC4000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0xC4000' end='0xC8000' datawidth='32' /><slave name='jesd204b.mem' start='0xC8000' end='0xCC000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0xCC000' end='0xCD000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -6302,11 +6302,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xC5000' end='0xC5800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>20</value>
+ <value>18</value>
</entry>
</consumedSystemInfos>
</value>
@@ -6950,7 +6950,7 @@
<name>i_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7232,7 +7232,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x000c5020</value>
+ <value>0x00003820</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -7328,7 +7328,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
- <value>20</value>
+ <value>18</value>
</entry>
<entry>
<key>embeddedsw.CMacro.OCI_VERSION</key>
@@ -17324,7 +17324,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17393,7 +17393,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17622,7 +17622,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17800,11 +17800,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17904,7 +17904,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17943,21 +17943,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -17973,7 +17969,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17997,7 +17993,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -18202,7 +18197,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43676,7 +43671,7 @@
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c5000" />
+ <parameter name="baseAddress" value="0x3800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -43976,7 +43971,7 @@
start="cpu_0.data_master"
end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c0000" />
+ <parameter name="baseAddress" value="0x000c8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -44096,7 +44091,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xc000" />
+ <parameter name="baseAddress" value="0x000c4000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -44156,7 +44151,7 @@
start="cpu_0.data_master"
end="ram_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x000c0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -44236,7 +44231,7 @@
start="cpu_0.data_master"
end="ram_st_histogram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -44256,7 +44251,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c4000" />
+ <parameter name="baseAddress" value="0x000cc000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -44376,7 +44371,7 @@
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c5000" />
+ <parameter name="baseAddress" value="0x3800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 9f644a019c6749a95ba31afe1463e9bb55cd372d..3e011316ea457d360c03b806a64ec96fc07c972a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -457,7 +457,7 @@ BEGIN
ram_st_histogram_clk_export => OPEN,
ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(9-1 DOWNTO 0),
+ ram_st_histogram_address_export => ram_st_histogram_mosi.address(13-1 DOWNTO 0),
ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 569a57101c53f0a7cb66e014dbdf9a3a5afcd2e2..5af3d90a4334f27ad011c6f84dad772ee03179e2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -149,7 +149,8 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
CONSTANT c_st_histogram_in_data_w : NATURAL := 14;
CONSTANT c_st_histogram_nof_bins : NATURAL := 512;
CONSTANT c_st_histogram_str : STRING := "freq.density";
-
+ SIGNAL ram_st_histogram_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL ram_st_histogram_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -498,27 +499,41 @@ BEGIN
-- Histogram
-----------------------------------------------------------------------------
- u_st_histogram : ENTITY st_lib.st_histogram
+ gen_st_histogram : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ u_st_histogram : ENTITY st_lib.st_histogram
+ GENERIC MAP (
+ g_in_data_w => c_st_histogram_in_data_w, -- 14, -- c_data_w,
+ g_nof_bins => c_st_histogram_nof_bins, -- 512,
+ g_nof_data => c_lofar2_sample_clk_freq,
+ g_str => c_st_histogram_str,
+ g_ram_miso_sim_mode => FALSE --g_sim -- is the specific output data even allowed when g_sim is TRUE ??
+ )
+ PORT MAP (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ -- Streaming
+ snk_in => st_sosi_arr(I),
+
+ -- DP clocked memory bus
+ sla_in_ram_mosi => ram_st_histogram_mosi_arr(I), -- Beware, works in dp clock domain !
+ sla_out_ram_miso => ram_st_histogram_miso_arr(I), -- '' !
+
+ -- Debug bus
+ dbg_ram_miso => OPEN -- '' !
+ );
+ END GENERATE;
+
+ u_mem_mux_histogram : ENTITY common_lib.common_mem_mux
GENERIC MAP (
- g_in_data_w => c_st_histogram_in_data_w, -- 14, -- c_data_w,
- g_nof_bins => c_st_histogram_nof_bins, -- 512,
- g_nof_data => c_lofar2_sample_clk_freq,
- g_str => c_st_histogram_str,
- g_ram_miso_sim_mode => FALSE --g_sim -- is the specific output data even allowed when g_sim is TRUE ??
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(c_st_histogram_nof_bins)
)
PORT MAP (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- -- Streaming
- snk_in => st_sosi_arr(0),
-
- -- DP clocked memory bus
- sla_in_ram_mosi => ram_st_histogram_mosi, -- Beware, works in dp clock domain !
- sla_out_ram_miso => ram_st_histogram_miso, -- '' !
-
- -- Debug bus
- dbg_ram_miso => OPEN -- '' !
+ mosi => ram_st_histogram_mosi,
+ miso => ram_st_histogram_miso,
+ mosi_arr => ram_st_histogram_mosi_arr,
+ miso_arr => ram_st_histogram_miso_arr
);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index 4504baf1645a3fec65591819d6fb2ea47ec07039..96569b1842f0771e6ecc3f876e8be59dc4a359d3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -242,7 +242,7 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
reg_diag_data_buf_bsn_write_export : out std_logic; -- export
reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(8 downto 0);
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0);
ram_st_histogram_clk_export : out std_logic;
ram_st_histogram_read_export : out std_logic;
ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');