diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index 3aca57d567e20b6ed2bbcfddf4a92a75b2120303..c4632c5a4dabd728e680b782578f57d77e06c7f4 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -36,198 +36,31 @@ peripherals:
slave_type: REG
slave_description: ""
fields:
- - - field_name: rx_dll_ctrl
- field_description: ""
- width: 17
- bit_offset: 0
- access_mode: RW
- address_offset: 0x50
-
- - - field_name: rx_syncn_sysref_ctrl
- field_description: ""
- width: 25
- bit_offset: 0
- access_mode: RW
- address_offset: 0x54
-
- - - field_name: rx_csr_lmfc_offset
- field_description: ""
- width: 8
- bit_offset: 12
- access_mode: RW
- address_offset: 0x54
-
- - - field_name: rx_csr_rbd_offset
- field_description: ""
- width: 8
- bit_offset: 3
- access_mode: RW
- address_offset: 0x54
-
- - - field_name: rx_csr_sysref_always_on
- field_description: ""
- width: 1
- bit_offset: 1
- access_mode: RW
- address_offset: 0x54
-
- - - field_name: rx_err0
- field_description: ""
- width: 9
- bit_offset: 0
- access_mode: RW
- address_offset: 0x60
-
- - - field_name: rx_err1
- field_description: ""
- width: 10 # from pdf
- bit_offset: 0
- access_mode: RW
- address_offset: 0x64
-
- - - field_name: csr_rbd_count
- field_description: ""
- width: 8
- bit_offset: 3
- access_mode: RO
- address_offset: 0x80
-
- - - field_name: csr_dev_syncn
- field_description: ""
- width: 1
- bit_offset: 0
- access_mode: RO
- address_offset: 0x80
-
- - - field_name: rx_status1
- field_description: ""
- width: 24
- bit_offset: 0
- access_mode: RW
- address_offset: 0x84
-
- - - field_name: rx_status2
- field_description: ""
- width: 24
- bit_offset: 0
- access_mode: RW
- address_offset: 0x88
-
- - - field_name: rx_status3
- field_description: ""
- width: 8
- bit_offset: 0
- access_mode: RW
- address_offset: 0x8C
-
- - - field_name: rx_ilas_csr_m
- field_description: ""
- width: 8
- bit_offset: 24
- access_mode: RW
- address_offset: 0x94
-
- - - field_name: rx_ilas_csr_k
- field_description: ""
- width: 5
- bit_offset: 16
- access_mode: RW
- address_offset: 0x94
-
- - - field_name: rx_ilas_csr_f
- field_description: ""
- width: 8
- bit_offset: 8
- access_mode: RW
- address_offset: 0x94
-
- - - field_name: rx_ilas_csr_l
- field_description: ""
- width: 5
- bit_offset: 0
- access_mode: RW
- address_offset: 0x94
-
- - - field_name: rx_ilas_csr_hd
- field_description: ""
- width: 1
- bit_offset: 31
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_cf
- field_description: ""
- width: 5
- bit_offset: 24
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_jesdv
- field_description: ""
- width: 3
- bit_offset: 21
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_s
- field_description: ""
- width: 5
- bit_offset: 16
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_subclassv
- field_description: ""
- width: 3
- bit_offset: 13
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_np
- field_description: ""
- width: 5
- bit_offset: 8
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_cs
- field_description: ""
- width: 2
- bit_offset: 6
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_ilas_csr_n
- field_description: ""
- width: 5
- bit_offset: 0
- access_mode: RW
- address_offset: 0x98
-
- - - field_name: rx_status4
- field_description: ""
- width: 16
- bit_offset: 0
- access_mode: RW
- address_offset: 0xF0
-
- - - field_name: rx_status5
- field_description: ""
- width: 16
- bit_offset: 0
- access_mode: RW
- address_offset: 0xF4
-
- - - field_name: rx_status6
- field_description: ""
- width: 24
- bit_offset: 0
- access_mode: RW
- address_offset: 0xF8
-
- - - field_name: rx_status7
- field_description: ""
- width: 32
- bit_offset: 0
- access_mode: RO
- address_offset: 0xFC
+ - - {field_name: rx_dll_ctrl, width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
+ - - {field_name: rx_syncn_sysref_ctrl, width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_lmfc_offset, width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_rbd_offset, width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_always_on, width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_err0, width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
+ - - {field_name: rx_err1, width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
+ - - {field_name: csr_rbd_count, width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
+ - - {field_name: csr_dev_syncn, width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
+ - - {field_name: rx_status1, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
+ - - {field_name: rx_status2, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
+ - - {field_name: rx_status3, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
+ - - {field_name: rx_ilas_csr_m, width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_k, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_f, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_l, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_hd, width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cf, width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_jesdv, width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_s, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_subclassv, width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_np, width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cs, width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_n, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_status4, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
+ - - {field_name: rx_status5, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
+ - - {field_name: rx_status6, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
+ - - {field_name: rx_status7, width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}