diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 535e1c1055ad9bac89cc8458305338a61da4f057..955bb5968ff5487340784c8025c9f4f5c1667e7e 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -129,6 +129,7 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
   SIGNAL wr_eop_cnt       : NATURAL := 0;
   SIGNAL rd_eop_cnt       : NATURAL := 0;
 
+  -- EOP count can be negative when a packet is sent out without having received the eop. This can be the case when g_fifo_fill has been reached.
   SIGNAL eop_cnt          : INTEGER := 0;
   SIGNAL nxt_eop_cnt      : INTEGER := 0; 
 
@@ -259,7 +260,7 @@ BEGIN
     );
 
     p_dc: PROCESS(wr_clk, wr_rst)
-    VARIABLE v_wr_eop_cnt: NATURAL;
+      VARIABLE v_wr_eop_cnt: NATURAL;
     BEGIN
       IF wr_rst='1' THEN
         wr_eop_busy <= '0';
@@ -304,6 +305,7 @@ BEGIN
         xon_reg   <= '0';
         state     <= s_idle;
         i_src_out <= c_dp_sosi_rst;
+        eop_cnt   <= 0;
       ELSIF rising_edge(rd_clk) THEN
         xon_reg   <= nxt_xon_reg;
         state     <= nxt_state;