diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd index db779b159b695afba479a7f6087be0b08618ca77..5a0b695ca775ab35d8cec916171c79c716a12ceb 100644 --- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd +++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd @@ -19,7 +19,7 @@ -- ------------------------------------------------------------------------------- -LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib; +LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, io_ddr_lib; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE common_lib.common_pkg.ALL; @@ -28,6 +28,7 @@ USE common_lib.tb_common_mem_pkg.ALL; USE common_lib.common_field_pkg.ALL; USE common_lib.common_network_total_header_pkg.ALL; USE common_lib.common_network_layers_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; USE unb1_board_lib.unb1_board_pkg.ALL; USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE mm_lib.mm_file_pkg.ALL; @@ -46,7 +47,8 @@ ENTITY mmm_unb1_test IS g_sim_node_nr : NATURAL := 0; g_nof_streams : NATURAL; g_bg_block_size : NATURAL; - g_hdr_field_arr : t_common_field_arr + g_hdr_field_arr : t_common_field_arr; + g_nof_MB : NATURAL := 2 ); PORT ( xo_clk : IN STD_LOGIC; @@ -142,7 +144,10 @@ ENTITY mmm_unb1_test IS reg_tr_10GbE_mosi : OUT t_mem_mosi; reg_tr_10GbE_miso : IN t_mem_miso; reg_tr_xaui_mosi : OUT t_mem_mosi; - reg_tr_xaui_miso : IN t_mem_miso + reg_tr_xaui_miso : IN t_mem_miso; + + reg_ddr3_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_MB-1); + reg_ddr3_miso_arr : IN t_mem_miso_arr(0 TO g_nof_MB-1) ); END mmm_unb1_test; @@ -181,6 +186,13 @@ ARCHITECTURE str OF mmm_unb1_test IS CONSTANT c_reg_tr_xaui_adr_w : NATURAL := 9; CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_tr_xaui_adr_w)); + CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control intrastructure for two MB's + + -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32 + CONSTANT c_mm_reg_ddr3_addr_w : NATURAL := ceil_log2(7); + CONSTANT c_mm_reg_diagnostics_addr_w : NATURAL := ceil_log2(40); + + -- BSN monitors CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w)); @@ -296,6 +308,13 @@ BEGIN u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER") PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso); + u_mm_file_reg_ddr3_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_0") + PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(0), reg_ddr3_miso_arr(0) ); + + u_mm_file_reg_ddr3_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDR3_1") + PORT MAP(mm_rst, i_mm_clk, reg_ddr3_mosi_arr(1), reg_ddr3_miso_arr(1) ); + + -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway. u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); @@ -590,7 +609,25 @@ BEGIN reg_diag_data_buffer_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0), reg_diag_data_buffer_reset_export => OPEN, reg_diag_data_buffer_write_export => reg_diag_data_buf_mosi.wr, - reg_diag_data_buffer_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0) + reg_diag_data_buffer_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0), + + -- the_reg_ddr3_0 + reg_ddr3_0_clk_export => OPEN, + reg_ddr3_0_reset_export => OPEN, + reg_ddr3_0_address_export => reg_ddr3_mosi_arr(0).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0), + reg_ddr3_0_read_export => reg_ddr3_mosi_arr(0).rd, + reg_ddr3_0_readdata_export => reg_ddr3_miso_arr(0).rddata(c_word_w-1 DOWNTO 0), + reg_ddr3_0_write_export => reg_ddr3_mosi_arr(0).wr, + reg_ddr3_0_writedata_export => reg_ddr3_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0), + + -- the_reg_ddr3_1 + reg_ddr3_1_clk_export => OPEN, + reg_ddr3_1_reset_export => OPEN, + reg_ddr3_1_address_export => reg_ddr3_mosi_arr(1).address(c_mm_reg_ddr3_addr_w-1 DOWNTO 0), + reg_ddr3_1_read_export => reg_ddr3_mosi_arr(1).rd, + reg_ddr3_1_readdata_export => reg_ddr3_miso_arr(1).rddata(c_word_w-1 DOWNTO 0), + reg_ddr3_1_write_export => reg_ddr3_mosi_arr(1).wr, + reg_ddr3_1_writedata_export => reg_ddr3_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0) ); END GENERATE; diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd index 00a494b3301b037cb45af5f5e0cce494691c6443..cdb56c57754966ba6cc2706db11a4bd77248212c 100644 --- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd +++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd @@ -217,7 +217,25 @@ PACKAGE qsys_unb1_test_pkg IS ram_diag_bg_write_export : out std_logic; -- export ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export ram_diag_bg_clk_export : out std_logic; -- export - ram_diag_bg_reset_export : out std_logic -- export + ram_diag_bg_reset_export : out std_logic; -- export + + -- the_reg_ddr3_0 + reg_ddr3_0_clk_export : out std_logic; -- export + reg_ddr3_0_reset_export : out std_logic; -- export + reg_ddr3_0_address_export : out std_logic_vector(2 downto 0); -- export + reg_ddr3_0_read_export : out std_logic; -- export + reg_ddr3_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_ddr3_0_write_export : out std_logic; -- export + reg_ddr3_0_writedata_export : out std_logic_vector(31 downto 0); -- export + + -- the_reg_ddr3_1 + reg_ddr3_1_clk_export : out std_logic; -- export + reg_ddr3_1_reset_export : out std_logic; -- export + reg_ddr3_1_address_export : out std_logic_vector(2 downto 0); -- export + reg_ddr3_1_read_export : out std_logic; -- export + reg_ddr3_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export + reg_ddr3_1_write_export : out std_logic; -- export + reg_ddr3_1_writedata_export : out std_logic_vector(31 downto 0) -- export ); end component qsys_unb1_test;